/* Position of cpu flags bitfiled. */
-/* i186 or better required */
-#define Cpu186 0
-/* i286 or better required */
-#define Cpu286 (Cpu186 + 1)
-/* i386 or better required */
-#define Cpu386 (Cpu286 + 1)
-/* i486 or better required */
-#define Cpu486 (Cpu386 + 1)
-/* i585 or better required */
-#define Cpu586 (Cpu486 + 1)
-/* i686 or better required */
-#define Cpu686 (Cpu586 + 1)
-/* CLFLUSH Instuction support required */
-#define CpuClflush (Cpu686 + 1)
-/* SYSCALL Instuctions support required */
-#define CpuSYSCALL (CpuClflush + 1)
-/* Floating point support required */
-#define Cpu8087 (CpuSYSCALL + 1)
-/* i287 support required */
-#define Cpu287 (Cpu8087 + 1)
-/* i387 support required */
-#define Cpu387 (Cpu287 + 1)
-/* i686 and floating point support required */
-#define Cpu687 (Cpu387 + 1)
-/* SSE3 and floating point support required */
-#define CpuFISTTP (Cpu687 + 1)
-/* MMX support required */
-#define CpuMMX (CpuFISTTP + 1)
-/* SSE support required */
-#define CpuSSE (CpuMMX + 1)
-/* SSE2 support required */
-#define CpuSSE2 (CpuSSE + 1)
-/* 3dnow! support required */
-#define Cpu3dnow (CpuSSE2 + 1)
-/* 3dnow! Extensions support required */
-#define Cpu3dnowA (Cpu3dnow + 1)
-/* SSE3 support required */
-#define CpuSSE3 (Cpu3dnowA + 1)
-/* VIA PadLock required */
-#define CpuPadLock (CpuSSE3 + 1)
-/* AMD Secure Virtual Machine Ext-s required */
-#define CpuSVME (CpuPadLock + 1)
-/* VMX Instructions required */
-#define CpuVMX (CpuSVME + 1)
-/* SMX Instructions required */
-#define CpuSMX (CpuVMX + 1)
-/* SSSE3 support required */
-#define CpuSSSE3 (CpuSMX + 1)
-/* SSE4a support required */
-#define CpuSSE4a (CpuSSSE3 + 1)
-/* ABM New Instructions required */
-#define CpuABM (CpuSSE4a + 1)
-/* SSE4.1 support required */
-#define CpuSSE4_1 (CpuABM + 1)
-/* SSE4.2 support required */
-#define CpuSSE4_2 (CpuSSE4_1 + 1)
-/* AVX support required */
-#define CpuAVX (CpuSSE4_2 + 1)
-/* Intel L1OM support required */
-#define CpuL1OM (CpuAVX + 1)
-/* Xsave/xrstor New Instuctions support required */
-#define CpuXsave (CpuL1OM + 1)
-/* AES support required */
-#define CpuAES (CpuXsave + 1)
-/* PCLMUL support required */
-#define CpuPCLMUL (CpuAES + 1)
-/* FMA support required */
-#define CpuFMA (CpuPCLMUL + 1)
-/* FMA4 support required */
-#define CpuFMA4 (CpuFMA + 1)
-/* MOVBE Instuction support required */
-#define CpuMovbe (CpuFMA4 + 1)
-/* EPT Instructions required */
-#define CpuEPT (CpuMovbe + 1)
-/* RDTSCP Instuction support required */
-#define CpuRdtscp (CpuEPT + 1)
-/* 64bit support available, used by -march= in assembler. */
-#define CpuLM (CpuRdtscp + 1)
-/* 64bit support required */
-#define Cpu64 (CpuLM + 1)
-/* Not supported in the 64bit mode */
-#define CpuNo64 (Cpu64 + 1)
-/* The last bitfield in i386_cpu_flags. */
-#define CpuMax CpuNo64
+enum
+{
+ /* i186 or better required */
+ Cpu186 = 0,
+ /* i286 or better required */
+ Cpu286,
+ /* i386 or better required */
+ Cpu386,
+ /* i486 or better required */
+ Cpu486,
+ /* i585 or better required */
+ Cpu586,
+ /* i686 or better required */
+ Cpu686,
+ /* CLFLUSH Instuction support required */
+ CpuClflush,
+ /* SYSCALL Instuctions support required */
+ CpuSYSCALL,
+ /* Floating point support required */
+ Cpu8087,
+ /* i287 support required */
+ Cpu287,
+ /* i387 support required */
+ Cpu387,
+ /* i686 and floating point support required */
+ Cpu687,
+ /* SSE3 and floating point support required */
+ CpuFISTTP,
+ /* MMX support required */
+ CpuMMX,
+ /* SSE support required */
+ CpuSSE,
+ /* SSE2 support required */
+ CpuSSE2,
+ /* 3dnow! support required */
+ Cpu3dnow,
+ /* 3dnow! Extensions support required */
+ Cpu3dnowA,
+ /* SSE3 support required */
+ CpuSSE3,
+ /* VIA PadLock required */
+ CpuPadLock,
+ /* AMD Secure Virtual Machine Ext-s required */
+ CpuSVME,
+ /* VMX Instructions required */
+ CpuVMX,
+ /* SMX Instructions required */
+ CpuSMX,
+ /* SSSE3 support required */
+ CpuSSSE3,
+ /* SSE4a support required */
+ CpuSSE4a,
+ /* ABM New Instructions required */
+ CpuABM,
+ /* SSE4.1 support required */
+ CpuSSE4_1,
+ /* SSE4.2 support required */
+ CpuSSE4_2,
+ /* AVX support required */
+ CpuAVX,
+ /* Intel L1OM support required */
+ CpuL1OM,
+ /* Xsave/xrstor New Instuctions support required */
+ CpuXsave,
+ /* AES support required */
+ CpuAES,
+ /* PCLMUL support required */
+ CpuPCLMUL,
+ /* FMA support required */
+ CpuFMA,
+ /* FMA4 support required */
+ CpuFMA4,
+ /* MOVBE Instuction support required */
+ CpuMovbe,
+ /* EPT Instructions required */
+ CpuEPT,
+ /* RDTSCP Instuction support required */
+ CpuRdtscp,
+ /* 64bit support available, used by -march= in assembler. */
+ CpuLM,
+ /* 64bit support required */
+ Cpu64,
+ /* Not supported in the 64bit mode */
+ CpuNo64,
+ /* The last bitfield in i386_cpu_flags. */
+ CpuMax = CpuNo64
+};
#define CpuNumOfUints \
(CpuMax / sizeof (unsigned int) / CHAR_BIT + 1)
/* Position of opcode_modifier bits. */
-/* has direction bit. */
-#define D 0
-/* set if operands can be words or dwords encoded the canonical way */
-#define W (D + 1)
-/* Skip the current insn and use the next insn in i386-opc.tbl to swap
- operand in encoding. */
-#define S (W + 1)
-/* insn has a modrm byte. */
-#define Modrm (S + 1)
-/* register is in low 3 bits of opcode */
-#define ShortForm (Modrm + 1)
-/* special case for jump insns. */
-#define Jump (ShortForm + 1)
-/* call and jump */
-#define JumpDword (Jump + 1)
-/* loop and jecxz */
-#define JumpByte (JumpDword + 1)
-/* special case for intersegment leaps/calls */
-#define JumpInterSegment (JumpByte + 1)
-/* FP insn memory format bit, sized by 0x4 */
-#define FloatMF (JumpInterSegment + 1)
-/* src/dest swap for floats. */
-#define FloatR (FloatMF + 1)
-/* has float insn direction bit. */
-#define FloatD (FloatR + 1)
-/* needs size prefix if in 32-bit mode */
-#define Size16 (FloatD + 1)
-/* needs size prefix if in 16-bit mode */
-#define Size32 (Size16 + 1)
-/* needs size prefix if in 64-bit mode */
-#define Size64 (Size32 + 1)
-/* instruction ignores operand size prefix and in Intel mode ignores
- mnemonic size suffix check. */
-#define IgnoreSize (Size64 + 1)
-/* default insn size depends on mode */
-#define DefaultSize (IgnoreSize + 1)
-/* b suffix on instruction illegal */
-#define No_bSuf (DefaultSize + 1)
-/* w suffix on instruction illegal */
-#define No_wSuf (No_bSuf + 1)
-/* l suffix on instruction illegal */
-#define No_lSuf (No_wSuf + 1)
-/* s suffix on instruction illegal */
-#define No_sSuf (No_lSuf + 1)
-/* q suffix on instruction illegal */
-#define No_qSuf (No_sSuf + 1)
-/* long double suffix on instruction illegal */
-#define No_ldSuf (No_qSuf + 1)
-/* instruction needs FWAIT */
-#define FWait (No_ldSuf + 1)
-/* quick test for string instructions */
-#define IsString (FWait + 1)
-/* fake an extra reg operand for clr, imul and special register
- processing for some instructions. */
-#define RegKludge (IsString + 1)
-/* The first operand must be xmm0 */
-#define FirstXmm0 (RegKludge + 1)
-/* An implicit xmm0 as the first operand */
-#define Implicit1stXmm0 (FirstXmm0 + 1)
-/* BYTE is OK in Intel syntax. */
-#define ByteOkIntel (Implicit1stXmm0 + 1)
-/* Convert to DWORD */
-#define ToDword (ByteOkIntel + 1)
-/* Convert to QWORD */
-#define ToQword (ToDword + 1)
-/* Address prefix changes operand 0 */
-#define AddrPrefixOp0 (ToQword + 1)
-/* opcode is a prefix */
-#define IsPrefix (AddrPrefixOp0 + 1)
-/* instruction has extension in 8 bit imm */
-#define ImmExt (IsPrefix + 1)
-/* instruction don't need Rex64 prefix. */
-#define NoRex64 (ImmExt + 1)
-/* instruction require Rex64 prefix. */
-#define Rex64 (NoRex64 + 1)
-/* deprecated fp insn, gets a warning */
-#define Ugh (Rex64 + 1)
-/* insn has VEX prefix:
+enum
+{
+ /* has direction bit. */
+ D = 0,
+ /* set if operands can be words or dwords encoded the canonical way */
+ W,
+ /* Skip the current insn and use the next insn in i386-opc.tbl to swap
+ operand in encoding. */
+ S,
+ /* insn has a modrm byte. */
+ Modrm,
+ /* register is in low 3 bits of opcode */
+ ShortForm,
+ /* special case for jump insns. */
+ Jump,
+ /* call and jump */
+ JumpDword,
+ /* loop and jecxz */
+ JumpByte,
+ /* special case for intersegment leaps/calls */
+ JumpInterSegment,
+ /* FP insn memory format bit, sized by 0x4 */
+ FloatMF,
+ /* src/dest swap for floats. */
+ FloatR,
+ /* has float insn direction bit. */
+ FloatD,
+ /* needs size prefix if in 32-bit mode */
+ Size16,
+ /* needs size prefix if in 16-bit mode */
+ Size32,
+ /* needs size prefix if in 64-bit mode */
+ Size64,
+ /* instruction ignores operand size prefix and in Intel mode ignores
+ mnemonic size suffix check. */
+ IgnoreSize,
+ /* default insn size depends on mode */
+ DefaultSize,
+ /* b suffix on instruction illegal */
+ No_bSuf,
+ /* w suffix on instruction illegal */
+ No_wSuf,
+ /* l suffix on instruction illegal */
+ No_lSuf,
+ /* s suffix on instruction illegal */
+ No_sSuf,
+ /* q suffix on instruction illegal */
+ No_qSuf,
+ /* long double suffix on instruction illegal */
+ No_ldSuf,
+ /* instruction needs FWAIT */
+ FWait,
+ /* quick test for string instructions */
+ IsString,
+ /* fake an extra reg operand for clr, imul and special register
+ processing for some instructions. */
+ RegKludge,
+ /* The first operand must be xmm0 */
+ FirstXmm0,
+ /* An implicit xmm0 as the first operand */
+ Implicit1stXmm0,
+ /* BYTE is OK in Intel syntax. */
+ ByteOkIntel,
+ /* Convert to DWORD */
+ ToDword,
+ /* Convert to QWORD */
+ ToQword,
+ /* Address prefix changes operand 0 */
+ AddrPrefixOp0,
+ /* opcode is a prefix */
+ IsPrefix,
+ /* instruction has extension in 8 bit imm */
+ ImmExt,
+ /* instruction don't need Rex64 prefix. */
+ NoRex64,
+ /* instruction require Rex64 prefix. */
+ Rex64,
+ /* deprecated fp insn, gets a warning */
+ Ugh,
+ /* insn has VEX prefix:
1: 128bit VEX prefix.
2: 256bit VEX prefix.
- */
-#define Vex (Ugh + 1)
-/* insn has VEX NDS. Register-only source is encoded in Vex prefix.
- We use VexNDS on insns with VEX DDS since the register-only source
- is the second source register. */
-#define VexNDS (Vex + 1)
-/* insn has VEX NDD. Register destination is encoded in Vex
- prefix. */
-#define VexNDD (VexNDS + 1)
-/* insn has VEX W0. */
-#define VexW0 (VexNDD + 1)
-/* insn has VEX W1. */
-#define VexW1 (VexW0 + 1)
-/* insn has VEX 0x0F opcode prefix. */
-#define Vex0F (VexW1 + 1)
-/* insn has VEX 0x0F38 opcode prefix. */
-#define Vex0F38 (Vex0F + 1)
-/* insn has VEX 0x0F3A opcode prefix. */
-#define Vex0F3A (Vex0F38 + 1)
-/* insn has VEX prefix with 3 soures. */
-#define Vex3Sources (Vex0F3A + 1)
-/* instruction has VEX 8 bit imm */
-#define VexImmExt (Vex3Sources + 1)
-/* SSE to AVX support required */
-#define SSE2AVX (VexImmExt + 1)
-/* No AVX equivalent */
-#define NoAVX (SSE2AVX + 1)
-/* Compatible with old (<= 2.8.1) versions of gcc */
-#define OldGcc (NoAVX + 1)
-/* AT&T mnemonic. */
-#define ATTMnemonic (OldGcc + 1)
-/* AT&T syntax. */
-#define ATTSyntax (ATTMnemonic + 1)
-/* Intel syntax. */
-#define IntelSyntax (ATTSyntax + 1)
-/* The last bitfield in i386_opcode_modifier. */
-#define Opcode_Modifier_Max IntelSyntax
+ */
+ Vex,
+ /* insn has VEX NDS. Register-only source is encoded in Vex prefix.
+ We use VexNDS on insns with VEX DDS since the register-only source
+ is the second source register. */
+ VexNDS,
+ /* insn has VEX NDD. Register destination is encoded in Vex prefix. */
+ VexNDD,
+ /* insn has VEX W0. */
+ VexW0,
+ /* insn has VEX W1. */
+ VexW1,
+ /* insn has VEX 0x0F opcode prefix. */
+ Vex0F,
+ /* insn has VEX 0x0F38 opcode prefix. */
+ Vex0F38,
+ /* insn has VEX 0x0F3A opcode prefix. */
+ Vex0F3A,
+ /* insn has VEX prefix with 3 soures. */
+ Vex3Sources,
+ /* instruction has VEX 8 bit imm */
+ VexImmExt,
+ /* SSE to AVX support required */
+ SSE2AVX,
+ /* No AVX equivalent */
+ NoAVX,
+ /* Compatible with old (<= 2.8.1) versions of gcc */
+ OldGcc,
+ /* AT&T mnemonic. */
+ ATTMnemonic,
+ /* AT&T syntax. */
+ ATTSyntax,
+ /* Intel syntax. */
+ IntelSyntax,
+ /* The last bitfield in i386_opcode_modifier. */
+ Opcode_Modifier_Max
+};
typedef struct i386_opcode_modifier
{
/* Position of operand_type bits. */
-/* 8bit register */
-#define Reg8 0
-/* 16bit register */
-#define Reg16 (Reg8 + 1)
-/* 32bit register */
-#define Reg32 (Reg16 + 1)
-/* 64bit register */
-#define Reg64 (Reg32 + 1)
-/* Floating pointer stack register */
-#define FloatReg (Reg64 + 1)
-/* MMX register */
-#define RegMMX (FloatReg + 1)
-/* SSE register */
-#define RegXMM (RegMMX + 1)
-/* AVX registers */
-#define RegYMM (RegXMM + 1)
-/* Control register */
-#define Control (RegYMM + 1)
-/* Debug register */
-#define Debug (Control + 1)
-/* Test register */
-#define Test (Debug + 1)
-/* 2 bit segment register */
-#define SReg2 (Test + 1)
-/* 3 bit segment register */
-#define SReg3 (SReg2 + 1)
-/* 1 bit immediate */
-#define Imm1 (SReg3 + 1)
-/* 8 bit immediate */
-#define Imm8 (Imm1 + 1)
-/* 8 bit immediate sign extended */
-#define Imm8S (Imm8 + 1)
-/* 16 bit immediate */
-#define Imm16 (Imm8S + 1)
-/* 32 bit immediate */
-#define Imm32 (Imm16 + 1)
-/* 32 bit immediate sign extended */
-#define Imm32S (Imm32 + 1)
-/* 64 bit immediate */
-#define Imm64 (Imm32S + 1)
-/* 8bit/16bit/32bit displacements are used in different ways,
- depending on the instruction. For jumps, they specify the
- size of the PC relative displacement, for instructions with
- memory operand, they specify the size of the offset relative
- to the base register, and for instructions with memory offset
- such as `mov 1234,%al' they specify the size of the offset
- relative to the segment base. */
-/* 8 bit displacement */
-#define Disp8 (Imm64 + 1)
-/* 16 bit displacement */
-#define Disp16 (Disp8 + 1)
-/* 32 bit displacement */
-#define Disp32 (Disp16 + 1)
-/* 32 bit signed displacement */
-#define Disp32S (Disp32 + 1)
-/* 64 bit displacement */
-#define Disp64 (Disp32S + 1)
-/* Accumulator %al/%ax/%eax/%rax */
-#define Acc (Disp64 + 1)
-/* Floating pointer top stack register %st(0) */
-#define FloatAcc (Acc + 1)
-/* Register which can be used for base or index in memory operand. */
-#define BaseIndex (FloatAcc + 1)
-/* Register to hold in/out port addr = dx */
-#define InOutPortReg (BaseIndex + 1)
-/* Register to hold shift count = cl */
-#define ShiftCount (InOutPortReg + 1)
-/* Absolute address for jump. */
-#define JumpAbsolute (ShiftCount + 1)
-/* String insn operand with fixed es segment */
-#define EsSeg (JumpAbsolute + 1)
-/* RegMem is for instructions with a modrm byte where the register
- destination operand should be encoded in the mod and regmem fields.
- Normally, it will be encoded in the reg field. We add a RegMem
- flag to the destination register operand to indicate that it should
- be encoded in the regmem field. */
-#define RegMem (EsSeg + 1)
-/* Memory. */
-#define Mem (RegMem + 1)
-/* BYTE memory. */
-#define Byte (Mem + 1)
-/* WORD memory. 2 byte */
-#define Word (Byte + 1)
-/* DWORD memory. 4 byte */
-#define Dword (Word + 1)
-/* FWORD memory. 6 byte */
-#define Fword (Dword + 1)
-/* QWORD memory. 8 byte */
-#define Qword (Fword + 1)
-/* TBYTE memory. 10 byte */
-#define Tbyte (Qword + 1)
-/* XMMWORD memory. */
-#define Xmmword (Tbyte + 1)
-/* YMMWORD memory. */
-#define Ymmword (Xmmword + 1)
-/* Unspecified memory size. */
-#define Unspecified (Ymmword + 1)
-/* Any memory size. */
-#define Anysize (Unspecified + 1)
-
-/* The last bitfield in i386_operand_type. */
-#define OTMax Anysize
+enum
+{
+ /* 8bit register */
+ Reg8 = 0,
+ /* 16bit register */
+ Reg16,
+ /* 32bit register */
+ Reg32,
+ /* 64bit register */
+ Reg64,
+ /* Floating pointer stack register */
+ FloatReg,
+ /* MMX register */
+ RegMMX,
+ /* SSE register */
+ RegXMM,
+ /* AVX registers */
+ RegYMM,
+ /* Control register */
+ Control,
+ /* Debug register */
+ Debug,
+ /* Test register */
+ Test,
+ /* 2 bit segment register */
+ SReg2,
+ /* 3 bit segment register */
+ SReg3,
+ /* 1 bit immediate */
+ Imm1,
+ /* 8 bit immediate */
+ Imm8,
+ /* 8 bit immediate sign extended */
+ Imm8S,
+ /* 16 bit immediate */
+ Imm16,
+ /* 32 bit immediate */
+ Imm32,
+ /* 32 bit immediate sign extended */
+ Imm32S,
+ /* 64 bit immediate */
+ Imm64,
+ /* 8bit/16bit/32bit displacements are used in different ways,
+ depending on the instruction. For jumps, they specify the
+ size of the PC relative displacement, for instructions with
+ memory operand, they specify the size of the offset relative
+ to the base register, and for instructions with memory offset
+ such as `mov 1234,%al' they specify the size of the offset
+ relative to the segment base. */
+ /* 8 bit displacement */
+ Disp8,
+ /* 16 bit displacement */
+ Disp16,
+ /* 32 bit displacement */
+ Disp32,
+ /* 32 bit signed displacement */
+ Disp32S,
+ /* 64 bit displacement */
+ Disp64,
+ /* Accumulator %al/%ax/%eax/%rax */
+ Acc,
+ /* Floating pointer top stack register %st(0) */
+ FloatAcc,
+ /* Register which can be used for base or index in memory operand. */
+ BaseIndex,
+ /* Register to hold in/out port addr = dx */
+ InOutPortReg,
+ /* Register to hold shift count = cl */
+ ShiftCount,
+ /* Absolute address for jump. */
+ JumpAbsolute,
+ /* String insn operand with fixed es segment */
+ EsSeg,
+ /* RegMem is for instructions with a modrm byte where the register
+ destination operand should be encoded in the mod and regmem fields.
+ Normally, it will be encoded in the reg field. We add a RegMem
+ flag to the destination register operand to indicate that it should
+ be encoded in the regmem field. */
+ RegMem,
+ /* Memory. */
+ Mem,
+ /* BYTE memory. */
+ Byte,
+ /* WORD memory. 2 byte */
+ Word,
+ /* DWORD memory. 4 byte */
+ Dword,
+ /* FWORD memory. 6 byte */
+ Fword,
+ /* QWORD memory. 8 byte */
+ Qword,
+ /* TBYTE memory. 10 byte */
+ Tbyte,
+ /* XMMWORD memory. */
+ Xmmword,
+ /* YMMWORD memory. */
+ Ymmword,
+ /* Unspecified memory size. */
+ Unspecified,
+ /* Any memory size. */
+ Anysize,
+
+ /* The last bitfield in i386_operand_type. */
+ OTMax
+};
#define OTNumOfUints \
(OTMax / sizeof (unsigned int) / CHAR_BIT + 1)
projects / platform / upstream / binutils.git / commitdiff