auto-generate checks

llvm-svn: 278135

diff --git a/llvm/test/Transforms/InstCombine/pr17827.ll b/llvm/test/Transforms/InstCombine/pr17827.ll
index a8b5926..ac5fb88 100644 (file)
--- a/llvm/test/Transforms/InstCombine/pr17827.ll
+++ b/llvm/test/Transforms/InstCombine/pr17827.ll
@@ -1,10 +1,14 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt < %s -instcombine -S | FileCheck %s
 
 ; With left shift, the comparison should not be modified.
-; CHECK-LABEL: @test_shift_and_cmp_not_changed1(
-; CHECK: icmp slt i8 %andp, 32
 define i1 @test_shift_and_cmp_not_changed1(i8 %p) #0 {
-entry:
+; CHECK-LABEL: @test_shift_and_cmp_not_changed1(
+; CHECK-NEXT:    [[SHLP:%.*]] = shl i8 %p, 5
+; CHECK-NEXT:    [[ANDP:%.*]] = and i8 [[SHLP]], -64
+; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i8 [[ANDP]], 32
+; CHECK-NEXT:    ret i1 [[CMP]]
+;
   %shlp = shl i8 %p, 5
   %andp = and i8 %shlp, -64
   %cmp = icmp slt i8 %andp, 32
@@ -12,10 +16,13 @@ entry:
 }
 
 ; With arithmetic right shift, the comparison should not be modified.
-; CHECK-LABEL: @test_shift_and_cmp_not_changed2(
-; CHECK: icmp slt i8 %andp, 32
 define i1 @test_shift_and_cmp_not_changed2(i8 %p) #0 {
-entry:
+; CHECK-LABEL: @test_shift_and_cmp_not_changed2(
+; CHECK-NEXT:    [[SHLP:%.*]] = ashr i8 %p, 5
+; CHECK-NEXT:    [[ANDP:%.*]] = and i8 [[SHLP]], -64
+; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i8 [[ANDP]], 32
+; CHECK-NEXT:    ret i1 [[CMP]]
+;
   %shlp = ashr i8 %p, 5
   %andp = and i8 %shlp, -64
   %cmp = icmp slt i8 %andp, 32
@@ -24,12 +31,13 @@ entry:
 
 ; This should simplify functionally to the left shift case.
 ; The extra input parameter should be optimized away.
-; CHECK-LABEL: @test_shift_and_cmp_changed1(
-; CHECK:  %andp = shl i8 %p, 5
-; CHECK-NEXT: %shl = and i8 %andp, -64
-; CHECK-NEXT:  %cmp = icmp slt i8 %shl, 32
 define i1 @test_shift_and_cmp_changed1(i8 %p, i8 %q) #0 {
-entry:
+; CHECK-LABEL: @test_shift_and_cmp_changed1(
+; CHECK-NEXT:    [[ANDP:%.*]] = shl i8 %p, 5
+; CHECK-NEXT:    [[SHL:%.*]] = and i8 [[ANDP]], -64
+; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i8 [[SHL]], 32
+; CHECK-NEXT:    ret i1 [[CMP]]
+;
   %andp = and i8 %p, 6
   %andq = and i8 %q, 8
   %or = or i8 %andq, %andp
@@ -40,10 +48,12 @@ entry:
 }
 
 ; Unsigned compare allows a transformation to compare against 0.
-; CHECK-LABEL: @test_shift_and_cmp_changed2(
-; CHECK: icmp eq i8 %andp, 0
 define i1 @test_shift_and_cmp_changed2(i8 %p) #0 {
-entry:
+; CHECK-LABEL: @test_shift_and_cmp_changed2(
+; CHECK-NEXT:    [[ANDP:%.*]] = and i8 %p, 6
+; CHECK-NEXT:    [[CMP:%.*]] = icmp eq i8 [[ANDP]], 0
+; CHECK-NEXT:    ret i1 [[CMP]]
+;
   %shlp = shl i8 %p, 5
   %andp = and i8 %shlp, -64
   %cmp = icmp ult i8 %andp, 32
@@ -51,10 +61,13 @@ entry:
 }
 
 ; nsw on the shift should not affect the comparison.
-; CHECK-LABEL: @test_shift_and_cmp_changed3(
-; CHECK: icmp slt i8 %andp, 32
 define i1 @test_shift_and_cmp_changed3(i8 %p) #0 {
-entry:
+; CHECK-LABEL: @test_shift_and_cmp_changed3(
+; CHECK-NEXT:    [[SHLP:%.*]] = shl nsw i8 %p, 5
+; CHECK-NEXT:    [[ANDP:%.*]] = and i8 [[SHLP]], -64
+; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i8 [[ANDP]], 32
+; CHECK-NEXT:    ret i1 [[CMP]]
+;
   %shlp = shl nsw i8 %p, 5
   %andp = and i8 %shlp, -64
   %cmp = icmp slt i8 %andp, 32
@@ -62,10 +75,10 @@ entry:
 }
 
 ; Logical shift right allows a return true because the 'and' guarantees no bits are set.
-; CHECK-LABEL: @test_shift_and_cmp_changed4(
-; CHECK: ret i1 true
 define i1 @test_shift_and_cmp_changed4(i8 %p) #0 {
-entry:
+; CHECK-LABEL: @test_shift_and_cmp_changed4(
+; CHECK-NEXT:    ret i1 true
+;
   %shlp = lshr i8 %p, 5
   %andp = and i8 %shlp, -64
   %cmp = icmp slt i8 %andp, 32