riscv: dts: microchip: add new peripherals to icicle kit device tree

Add new peripherals to the MPFS, and enable them in the Icicle kit
device tree:

2x SPI, QSPI, 3x GPIO, 2x I2C, Real Time Counter, PCIE controller,
USB host & system controller.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>

diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
index dc5f351..cd2fe80 100644 (file)
--- a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
+++ b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
@@ -80,6 +80,26 @@
        sd-uhs-sdr104;
 };
 
+&spi0 {
+       status = "okay";
+};
+
+&spi1 {
+       status = "okay";
+};
+
+&qspi {
+       status = "okay";
+};
+
+&i2c0 {
+       status = "okay";
+};
+
+&i2c1 {
+       status = "okay";
+};
+
 &i2c2 {
        status = "okay";
 };
@@ -103,6 +123,39 @@
        };
 };
 
+&gpio2 {
+       interrupts = <53>, <53>, <53>, <53>,
+                    <53>, <53>, <53>, <53>,
+                    <53>, <53>, <53>, <53>,
+                    <53>, <53>, <53>, <53>,
+                    <53>, <53>, <53>, <53>,
+                    <53>, <53>, <53>, <53>,
+                    <53>, <53>, <53>, <53>,
+                    <53>, <53>, <53>, <53>;
+       status = "okay";
+};
+
+&rtc {
+       status = "okay";
+};
+
+&usb {
+       status = "okay";
+       dr_mode = "host";
+};
+
+&mbox {
+       status = "okay";
+};
+
+&syscontroller {
+       status = "okay";
+};
+
+&pcie {
+       status = "okay";
+};
+
 &core_pwm0 {
        status = "okay";
 };

diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
index 5e7aaaf..c5c9d13 100644 (file)
--- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
+++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
@@ -266,6 +266,66 @@
                        status = "disabled";
                };
 
+               spi0: spi@20108000 {
+                       compatible = "microchip,mpfs-spi";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       reg = <0x0 0x20108000 0x0 0x1000>;
+                       interrupt-parent = <&plic>;
+                       interrupts = <54>;
+                       clocks = <&clkcfg CLK_SPI0>;
+                       spi-max-frequency = <25000000>;
+                       status = "disabled";
+               };
+
+               spi1: spi@20109000 {
+                       compatible = "microchip,mpfs-spi";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       reg = <0x0 0x20109000 0x0 0x1000>;
+                       interrupt-parent = <&plic>;
+                       interrupts = <55>;
+                       clocks = <&clkcfg CLK_SPI1>;
+                       spi-max-frequency = <25000000>;
+                       status = "disabled";
+               };
+
+               qspi: spi@21000000 {
+                       compatible = "microchip,mpfs-qspi";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       reg = <0x0 0x21000000 0x0 0x1000>;
+                       interrupt-parent = <&plic>;
+                       interrupts = <85>;
+                       clocks = <&clkcfg CLK_QSPI>;
+                       spi-max-frequency = <25000000>;
+                       status = "disabled";
+               };
+
+               i2c0: i2c@2010a000 {
+                       compatible = "microchip,mpfs-i2c", "microchip,corei2c-rtl-v7";
+                       reg = <0x0 0x2010a000 0x0 0x1000>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       interrupt-parent = <&plic>;
+                       interrupts = <58>;
+                       clocks = <&clkcfg CLK_I2C0>;
+                       clock-frequency = <100000>;
+                       status = "disabled";
+               };
+
+               i2c1: i2c@2010b000 {
+                       compatible = "microchip,mpfs-i2c", "microchip,corei2c-rtl-v7";
+                       reg = <0x0 0x2010b000 0x0 0x1000>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       interrupt-parent = <&plic>;
+                       interrupts = <61>;
+                       clocks = <&clkcfg CLK_I2C1>;
+                       clock-frequency = <100000>;
+                       status = "disabled";
+               };
+
                mac0: ethernet@20110000 {
                        compatible = "cdns,macb";
                        reg = <0x0 0x20110000 0x0 0x2000>;
@@ -291,5 +351,105 @@
                        clock-names = "pclk", "hclk";
                        status = "disabled";
                };
+
+               gpio0: gpio@20120000 {
+                       compatible = "microchip,mpfs-gpio";
+                       reg = <0x0 0x20120000 0x0 0x1000>;
+                       interrupt-parent = <&plic>;
+                       interrupt-controller;
+                       #interrupt-cells = <1>;
+                       clocks = <&clkcfg CLK_GPIO0>;
+                       gpio-controller;
+                       #gpio-cells = <2>;
+                       status = "disabled";
+               };
+
+               gpio1: gpio@20121000 {
+                       compatible = "microchip,mpfs-gpio";
+                       reg = <000 0x20121000 0x0 0x1000>;
+                       interrupt-parent = <&plic>;
+                       interrupt-controller;
+                       #interrupt-cells = <1>;
+                       clocks = <&clkcfg CLK_GPIO1>;
+                       gpio-controller;
+                       #gpio-cells = <2>;
+                       status = "disabled";
+               };
+
+               gpio2: gpio@20122000 {
+                       compatible = "microchip,mpfs-gpio";
+                       reg = <0x0 0x20122000 0x0 0x1000>;
+                       interrupt-parent = <&plic>;
+                       interrupt-controller;
+                       #interrupt-cells = <1>;
+                       clocks = <&clkcfg CLK_GPIO2>;
+                       gpio-controller;
+                       #gpio-cells = <2>;
+                       status = "disabled";
+               };
+
+               rtc: rtc@20124000 {
+                       compatible = "microchip,mpfs-rtc";
+                       reg = <0x0 0x20124000 0x0 0x1000>;
+                       interrupt-parent = <&plic>;
+                       interrupts = <80>, <81>;
+                       clocks = <&clkcfg CLK_RTC>;
+                       clock-names = "rtc";
+                       status = "disabled";
+               };
+
+               usb: usb@20201000 {
+                       compatible = "microchip,mpfs-musb";
+                       reg = <0x0 0x20201000 0x0 0x1000>;
+                       interrupt-parent = <&plic>;
+                       interrupts = <86>, <87>;
+                       clocks = <&clkcfg CLK_USB>;
+                       interrupt-names = "dma","mc";
+                       status = "disabled";
+               };
+
+               pcie: pcie@2000000000 {
+                       compatible = "microchip,pcie-host-1.0";
+                       #address-cells = <0x3>;
+                       #interrupt-cells = <0x1>;
+                       #size-cells = <0x2>;
+                       device_type = "pci";
+                       reg = <0x20 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0 0x10000>;
+                       reg-names = "cfg", "apb";
+                       bus-range = <0x0 0x7f>;
+                       interrupt-parent = <&plic>;
+                       interrupts = <119>;
+                       interrupt-map = <0 0 0 1 &pcie_intc 0>,
+                                       <0 0 0 2 &pcie_intc 1>,
+                                       <0 0 0 3 &pcie_intc 2>,
+                                       <0 0 0 4 &pcie_intc 3>;
+                       interrupt-map-mask = <0 0 0 7>;
+                       clocks = <&clkcfg CLK_FIC0>, <&clkcfg CLK_FIC1>, <&clkcfg CLK_FIC3>;
+                       clock-names = "fic0", "fic1", "fic3";
+                       ranges = <0x3000000 0x0 0x8000000 0x20 0x8000000 0x0 0x80000000>;
+                       msi-parent = <&pcie>;
+                       msi-controller;
+                       microchip,axi-m-atr0 = <0x10 0x0>;
+                       status = "disabled";
+                       pcie_intc: legacy-interrupt-controller {
+                               #address-cells = <0>;
+                               #interrupt-cells = <1>;
+                               interrupt-controller;
+                       };
+               };
+
+               mbox: mailbox@37020000 {
+                       compatible = "microchip,mpfs-mailbox";
+                       reg = <0x0 0x37020000 0x0 0x1000>, <0x0 0x2000318C 0x0 0x40>;
+                       interrupt-parent = <&plic>;
+                       interrupts = <96>;
+                       #mbox-cells = <1>;
+                       status = "disabled";
+               };
+
+               syscontroller: syscontroller {
+                       compatible = "microchip,mpfs-sys-controller";
+                       mboxes = <&mbox 0>;
+               };
        };
 };