+2014-06-23 James Greenhalgh <james.greenhalgh@arm.com>
+
+ * config/aarch64/aarch64.md (*addsi3_aarch64): Add alternative in
+ vector registers.
+
2014-05-16 James Greenhalgh <james.greenhalgh@arm.com>
* config/aarch64/aarch64.c (aarch64_rtx_costs): Handle the case
(define_insn "*addsi3_aarch64"
[(set
- (match_operand:SI 0 "register_operand" "=rk,rk,rk")
+ (match_operand:SI 0 "register_operand" "=rk,rk,w,rk")
(plus:SI
- (match_operand:SI 1 "register_operand" "%rk,rk,rk")
- (match_operand:SI 2 "aarch64_plus_operand" "I,r,J")))]
+ (match_operand:SI 1 "register_operand" "%rk,rk,w,rk")
+ (match_operand:SI 2 "aarch64_plus_operand" "I,r,w,J")))]
""
"@
add\\t%w0, %w1, %2
add\\t%w0, %w1, %w2
+ add\\t%0.2s, %1.2s, %2.2s
sub\\t%w0, %w1, #%n2"
- [(set_attr "type" "alu_imm,alu_reg,alu_imm")]
+ [(set_attr "type" "alu_imm,alu_reg,neon_add,alu_imm")]
)
;; zero_extend version of above
return b;
}
/* { dg-final { scan-assembler "sshr\td\[0-9\]+,\ d\[0-9\]+,\ 63" } } */
-/* { dg-final { scan-assembler "shl\td\[0-9\]+,\ d\[0-9\]+,\ 1" } } */
Int32x1
test_corners_sisd_si (Int32x1 b)
return b;
}
/* { dg-final { scan-assembler "sshr\tv\[0-9\]+\.2s,\ v\[0-9\]+\.2s,\ 31" } } */
-/* { dg-final { scan-assembler "shl\tv\[0-9\]+\.2s,\ v\[0-9\]+\.2s,\ 1" } } */