drm/amdgpu: add ras error query count interface for nbio

Add the interface query_ras_error_count for nbio.

Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Guchun Chen <guchun.chen@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h
index c5255a7..9e26b81 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h
@@ -81,6 +81,8 @@ struct amdgpu_nbio_funcs {
        void (*handle_ras_err_event_athub_intr_no_bifring)(struct amdgpu_device *adev);
        int (*init_ras_controller_interrupt)(struct amdgpu_device *adev);
        int (*init_ras_err_event_athub_interrupt)(struct amdgpu_device *adev);
+       void (*query_ras_error_count)(struct amdgpu_device *adev,
+                                       void *ras_error_status);
        int (*ras_late_init)(struct amdgpu_device *adev);
 };
 

diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
index 2d171bf..fa6a891 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
@@ -473,6 +473,11 @@ static int nbio_v7_4_init_ras_err_event_athub_interrupt (struct amdgpu_device *a
        return 0;
 }
 
+static void nbio_v7_4_query_ras_error_count(struct amdgpu_device *adev,
+                                       void *ras_error_status)
+{
+}
+
 const struct amdgpu_nbio_funcs nbio_v7_4_funcs = {
        .get_hdp_flush_req_offset = nbio_v7_4_get_hdp_flush_req_offset,
        .get_hdp_flush_done_offset = nbio_v7_4_get_hdp_flush_done_offset,
@@ -498,5 +503,6 @@ const struct amdgpu_nbio_funcs nbio_v7_4_funcs = {
        .handle_ras_err_event_athub_intr_no_bifring = nbio_v7_4_handle_ras_err_event_athub_intr_no_bifring,
        .init_ras_controller_interrupt = nbio_v7_4_init_ras_controller_interrupt,
        .init_ras_err_event_athub_interrupt = nbio_v7_4_init_ras_err_event_athub_interrupt,
+       .query_ras_error_count = nbio_v7_4_query_ras_error_count,
        .ras_late_init = amdgpu_nbio_ras_late_init,
 };