intel_bios_reader: Add support to dump MIPI Configuration Block #52
authorGaurav K Singh <gaurav.k.singh@intel.com>
Wed, 16 Jul 2014 14:09:32 +0000 (19:39 +0530)
committerDamien Lespiau <damien.lespiau@intel.com>
Fri, 1 Aug 2014 16:48:48 +0000 (17:48 +0100)
Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
tools/intel_bios.h
tools/intel_bios_reader.c

index 832c580..752379a 100644 (file)
@@ -85,6 +85,8 @@ struct bdb_header {
 #define BDB_LVDS_LFP_DATA       42
 #define BDB_LVDS_BACKLIGHT      43
 #define BDB_LVDS_POWER          44
+#define BDB_MIPI_CONFIG                 52
+#define BDB_MIPI_SEQUENCE       53
 #define BDB_SKIP               254     /* VBIOS private block, ignore */
 
 struct bdb_general_features {
@@ -597,6 +599,136 @@ struct bdb_edp {
        uint16_t edp_t3_optimization;
 } __attribute__ ((packed));
 
+
+/* Block 52 contains MiPi Panel info
+ * 6 such enteries will there. Index into correct
+ * entery is based on the panel_index in #40 LFP
+ */
+#define MAX_MIPI_CONFIGURATIONS        6
+struct mipi_config {
+       uint16_t panel_id;
+
+       /* General Params */
+       uint32_t dithering:1;
+       uint32_t rsvd1:1;
+       uint32_t panel_type:1;
+       uint32_t panel_arch_type:2;
+       uint32_t cmd_mode:1;
+       uint32_t vtm:2;
+       uint32_t cabc:1;
+       uint32_t pwm_blc:1;
+
+       /* Bit 13:10
+        * 000 - Reserved, 001 - RGB565, 002 - RGB666,
+        * 011 - RGB666Loosely packed, 100 - RGB888,
+        * others - rsvd
+        */
+       uint32_t videomode_color_format:4;
+
+       /* Bit 15:14
+        * 0 - No rotation, 1 - 90 degree
+        * 2 - 180 degree, 3 - 270 degree
+        */
+       uint32_t rotation:2;
+       uint32_t bta:1;
+       uint32_t rsvd2:15;
+
+       /* 2 byte Port Description */
+       uint16_t dual_link:2;
+       uint16_t lane_cnt:2;
+       uint16_t rsvd3:12;
+
+       /* 2 byte DSI COntroller params */
+       /* 0 - Using DSI PHY, 1 - TE usage */
+       uint16_t dsi_usage:1;
+       uint16_t rsvd4:15;
+
+       uint8_t rsvd5[5];
+       uint32_t dsi_ddr_clk;
+       uint32_t bridge_ref_clk;
+
+       uint8_t byte_clk_sel:2;
+       uint8_t rsvd6:6;
+
+       /* DPHY Flags */
+       uint16_t dphy_param_valid:1;
+       uint16_t eot_disabled:1;
+       uint16_t clk_stop:1;
+       uint16_t rsvd7:13;
+
+       uint32_t hs_tx_timeout;
+       uint32_t lp_rx_timeout;
+       uint32_t turn_around_timeout;
+       uint32_t device_reset_timer;
+       uint32_t master_init_timer;
+       uint32_t dbi_bw_timer;
+       uint32_t lp_byte_clk_val;
+
+       /*  4 byte Dphy Params */
+       uint32_t prepare_cnt:6;
+       uint32_t rsvd8:2;
+       uint32_t clk_zero_cnt:8;
+       uint32_t trail_cnt:5;
+       uint32_t rsvd9:3;
+       uint32_t exit_zero_cnt:6;
+       uint32_t rsvd10:2;
+
+       uint32_t clk_lane_switch_cnt;
+       uint32_t hl_switch_cnt;
+
+       uint32_t rsvd11[6];
+
+       /* timings based on dphy spec */
+       uint8_t tclk_miss;
+       uint8_t tclk_post;
+       uint8_t rsvd12;
+       uint8_t tclk_pre;
+       uint8_t tclk_prepare;
+       uint8_t tclk_settle;
+       uint8_t tclk_term_enable;
+       uint8_t tclk_trail;
+       uint16_t tclk_prepare_clkzero;
+       uint8_t rsvd13;
+       uint8_t td_term_enable;
+       uint8_t teot;
+       uint8_t ths_exit;
+       uint8_t ths_prepare;
+       uint16_t ths_prepare_hszero;
+       uint8_t rsvd14;
+       uint8_t ths_settle;
+       uint8_t ths_skip;
+       uint8_t ths_trail;
+       uint8_t tinit;
+       uint8_t tlpx;
+       uint8_t rsvd15[3];
+
+       /* GPIOs */
+       uint8_t panel_enable;
+       uint8_t bl_enable;
+       uint8_t pwm_enable;
+       uint8_t reset_r_n;
+       uint8_t pwr_down_r;
+       uint8_t stdby_r_n;
+
+} __attribute__ ((packed));
+
+/* Block 52 contains MiPi configuration block
+ * 6 * bdb_mipi_config, followed by 6 pps data
+ * block below
+ */
+struct mipi_pps_data {
+       uint16_t panel_on_delay;
+       uint16_t bl_enable_delay;
+       uint16_t bl_disable_delay;
+       uint16_t panel_off_delay;
+       uint16_t panel_power_cycle_delay;
+} __attribute__ ((packed));
+
+struct bdb_mipi_config {
+       struct mipi_config config[MAX_MIPI_CONFIGURATIONS];
+       struct mipi_pps_data pps[MAX_MIPI_CONFIGURATIONS];
+} __attribute__ ((packed));
+
 /*
  * Driver<->VBIOS interaction occurs through scratch bits in
  * GR18 & SWF*.
index 173772b..9f82481 100644 (file)
@@ -696,6 +696,94 @@ static void dump_sdvo_lvds_options(const struct bdb_block *block)
        printf("\tmisc[3]: %x\n", options->panel_misc_bits_4);
 }
 
+static void dump_mipi_config(const struct bdb_block *block)
+{
+       struct bdb_mipi_config *start = block->data;
+       struct mipi_config *config;
+       struct mipi_pps_data *pps;
+
+       config = &start->config[panel_type];
+       pps = &start->pps[panel_type];
+
+       printf("\tGeneral Param\n");
+       printf("\t\t BTA disable: %s\n", config->bta ? "Disabled" : "Enabled");
+
+       printf("\t\t Video Mode Color Format: ");
+       if (config->videomode_color_format == 0)
+               printf("Not supported\n");
+       else if (config->videomode_color_format == 1)
+               printf("RGB565\n");
+       else if (config->videomode_color_format == 2)
+               printf("RGB666\n");
+       else if (config->videomode_color_format == 3)
+               printf("RGB666 Loosely Packed\n");
+       else if (config->videomode_color_format == 4)
+               printf("RGB888\n");
+       printf("\t\t PPS GPIO Pins: %s \n", config->pwm_blc ? "Using SOC" : "Using PMIC");
+       printf("\t\t CABC Support: %s\n", config->cabc ? "supported" : "not supported");
+       //insert video mode type
+       printf("\t\t Mode: %s\n", config->cmd_mode ? "COMMAND" : "VIDEO");
+       printf("\t\t Dithering: %s\n", config->dithering ? "done in Display Controller" : "done in Panel Controller");
+
+       printf("\tPort Desc\n");
+       //insert pixel overlap count
+       printf("\t\t Lane Count: %d\n", config->lane_cnt + 1);
+       printf("\t\t Dual Link Support: ");
+       if (config->dual_link == 0)
+               printf("not supported\n");
+       else if (config->dual_link == 1)
+               printf("Front Back mode\n");
+       else
+               printf("Pixel Alternative Mode\n");
+
+       printf("\tDphy Flags\n");
+       printf("\t\t Clock Stop: %s\n", config->clk_stop ? "ENABLED" : "DISABLED");
+       printf("\t\t EOT disabled: %s\n\n", config->eot_disabled ? "EOT not to be sent" : "EOT to be sent");
+
+       printf("\tHSTxTimeOut: 0x%x\n", config->hs_tx_timeout);
+       printf("\tLPRXTimeOut: 0x%x\n", config->lp_rx_timeout);
+       printf("\tTurnAroundTimeOut: 0x%x\n", config->turn_around_timeout);
+       printf("\tDeviceResetTimer: 0x%x\n", config->device_reset_timer);
+       printf("\tMasterinitTimer: 0x%x\n", config->master_init_timer);
+       printf("\tDBIBandwidthTimer: 0x%x\n", config->dbi_bw_timer);
+       printf("\tLpByteClkValue: 0x%x\n\n", config->lp_byte_clk_val);
+
+       printf("\tDphy Params\n");
+       printf("\t\tExit to zero Count: 0x%x\n", config->exit_zero_cnt);
+       printf("\t\tTrail Count: 0x%X\n", config->trail_cnt);
+       printf("\t\tClk zero count: 0x%x\n", config->clk_zero_cnt);
+       printf("\t\tPrepare count:0x%x\n\n", config->prepare_cnt);
+
+       printf("\tClockLaneSwitchingCount: 0x%x\n", config->clk_lane_switch_cnt);
+       printf("\tHighToLowSwitchingCount: 0x%x\n\n", config->hl_switch_cnt);
+
+       printf("\tTimings based on Dphy spec\n");
+       printf("\t\tTClkMiss: 0x%x\n", config->tclk_miss);
+       printf("\t\tTClkPost: 0x%x\n", config->tclk_post);
+       printf("\t\tTClkPre: 0x%x\n", config->tclk_pre);
+       printf("\t\tTClkPrepare: 0x%x\n", config->tclk_prepare);
+       printf("\t\tTClkSettle: 0x%x\n", config->tclk_settle);
+       printf("\t\tTClkTermEnable: 0x%x\n\n", config->tclk_term_enable);
+
+       printf("\tTClkTrail: 0x%x\n", config->tclk_trail);
+       printf("\tTClkPrepareTClkZero: 0x%x\n", config->tclk_prepare_clkzero);
+       printf("\tTHSExit: 0x%x\n", config->ths_exit);
+       printf("\tTHsPrepare: 0x%x\n", config->ths_prepare);
+       printf("\tTHsPrepareTHsZero: 0x%x\n", config->ths_prepare_hszero);
+       printf("\tTHSSettle: 0x%x\n", config->ths_settle);
+       printf("\tTHSSkip: 0x%x\n", config->ths_skip);
+       printf("\tTHsTrail: 0x%x\n", config->ths_trail);
+       printf("\tTInit: 0x%x\n", config->tinit);
+       printf("\tTLPX: 0x%x\n", config->tlpx);
+
+       printf("\tMIPI PPS\n");
+       printf("\t\tPanel power ON delay: %d\n", pps->panel_on_delay);
+       printf("\t\tPanel power on to Baklight enable delay: %d\n", pps->bl_enable_delay);
+       printf("\t\tBacklight disable to Panel power OFF delay: %d\n", pps->bl_disable_delay);
+       printf("\t\tPanel power OFF delay: %d\n", pps->panel_off_delay);
+       printf("\t\tPanel power cycle delay: %d\n", pps->panel_power_cycle_delay);
+}
+
 static int
 get_device_id(unsigned char *bios)
 {
@@ -775,6 +863,11 @@ struct dumper dumpers[] = {
                .name = "eDP block",
                .dump = dump_edp,
        },
+       {
+               .id = BDB_MIPI_CONFIG,
+               .name = "MIPI configuration block",
+               .dump = dump_mipi_config,
+       },
 };
 
 static void hex_dump(const struct bdb_block *block)
@@ -948,6 +1041,7 @@ int main(int argc, char **argv)
 
        dump_section(BDB_DRIVER_FEATURES, size);
        dump_section(BDB_EDP, size);
+       dump_section(BDB_MIPI_CONFIG, size);
 
        for (i = 0; i < 256; i++)
                dump_section(i, size);