arm64: dts: qcom: sdm845: Pad addresses to 8 hex digits
authorKonrad Dybcio <konrad.dybcio@linaro.org>
Mon, 2 Jan 2023 09:46:34 +0000 (10:46 +0100)
committerBjorn Andersson <andersson@kernel.org>
Wed, 18 Jan 2023 23:58:10 +0000 (17:58 -0600)
Some addresses were 7-hex-digits long, or less. Fix that.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230102094642.74254-10-konrad.dybcio@linaro.org
arch/arm64/boot/dts/qcom/sdm845.dtsi

index 0f1cb2c..16f8a13 100644 (file)
 
                        iommus = <&apps_smmu 0x720 0x0>,
                                 <&apps_smmu 0x722 0x0>;
-                       reg = <0 0x1e40000 0 0x7000>,
-                             <0 0x1e47000 0 0x2000>,
-                             <0 0x1e04000 0 0x2c000>;
+                       reg = <0 0x01e40000 0 0x7000>,
+                             <0 0x01e47000 0 0x2000>,
+                             <0 0x01e04000 0 0x2c000>;
                        reg-names = "ipa-reg",
                                    "ipa-shared",
                                    "gsi";
                camss: camss@a00000 {
                        compatible = "qcom,sdm845-camss";
 
-                       reg = <0 0xacb3000 0 0x1000>,
-                               <0 0xacba000 0 0x1000>,
-                               <0 0xacc8000 0 0x1000>,
-                               <0 0xac65000 0 0x1000>,
-                               <0 0xac66000 0 0x1000>,
-                               <0 0xac67000 0 0x1000>,
-                               <0 0xac68000 0 0x1000>,
-                               <0 0xacaf000 0 0x4000>,
-                               <0 0xacb6000 0 0x4000>,
-                               <0 0xacc4000 0 0x4000>;
+                       reg = <0 0x0acb3000 0 0x1000>,
+                               <0 0x0acba000 0 0x1000>,
+                               <0 0x0acc8000 0 0x1000>,
+                               <0 0x0ac65000 0 0x1000>,
+                               <0 0x0ac66000 0 0x1000>,
+                               <0 0x0ac67000 0 0x1000>,
+                               <0 0x0ac68000 0 0x1000>,
+                               <0 0x0acaf000 0 0x4000>,
+                               <0 0x0acb6000 0 0x4000>,
+                               <0 0x0acc4000 0 0x4000>;
                        reg-names = "csid0",
                                "csid1",
                                "csid2",
                                status = "disabled";
                                compatible = "qcom,sdm845-dp";
 
-                               reg = <0 0xae90000 0 0x200>,
-                                     <0 0xae90200 0 0x200>,
-                                     <0 0xae90400 0 0x600>,
-                                     <0 0xae90a00 0 0x600>,
-                                     <0 0xae91000 0 0x600>;
+                               reg = <0 0x0ae90000 0 0x200>,
+                                     <0 0x0ae90200 0 0x200>,
+                                     <0 0x0ae90400 0 0x600>,
+                                     <0 0x0ae90a00 0 0x600>,
+                                     <0 0x0ae91000 0 0x600>;
 
                                interrupt-parent = <&mdss>;
                                interrupts = <12>;
                gpu: gpu@5000000 {
                        compatible = "qcom,adreno-630.2", "qcom,adreno";
 
-                       reg = <0 0x5000000 0 0x40000>, <0 0x509e000 0 0x10>;
+                       reg = <0 0x05000000 0 0x40000>, <0 0x509e000 0 0x10>;
                        reg-names = "kgsl_3d0_reg_memory", "cx_mem";
 
                        /*
 
                adreno_smmu: iommu@5040000 {
                        compatible = "qcom,sdm845-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
-                       reg = <0 0x5040000 0 0x10000>;
+                       reg = <0 0x05040000 0 0x10000>;
                        #iommu-cells = <1>;
                        #global-interrupts = <2>;
                        interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
                gmu: gmu@506a000 {
                        compatible = "qcom,adreno-gmu-630.2", "qcom,adreno-gmu";
 
-                       reg = <0 0x506a000 0 0x30000>,
-                             <0 0xb280000 0 0x10000>,
-                             <0 0xb480000 0 0x10000>;
+                       reg = <0 0x0506a000 0 0x30000>,
+                             <0 0x0b280000 0 0x10000>,
+                             <0 0x0b480000 0 0x10000>;
                        reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
 
                        interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,