net/mlx4_core: Add health buffer address capability
authorAlex Vesker <valex@mellanox.com>
Thu, 12 Jul 2018 12:13:15 +0000 (15:13 +0300)
committerDavid S. Miller <davem@davemloft.net>
Fri, 13 Jul 2018 00:37:13 +0000 (17:37 -0700)
Health buffer address is a 32 bit PCI address offset provided by
the FW. This offset is used for reading FW health debug data
located on the shared CR space. Cr space is accessible in both
driver and FW and allows for different queries and configurations.
Health buffer size is always 64B of readable data followed by a
lock which is used to block volatile CR space access.

Signed-off-by: Alex Vesker <valex@mellanox.com>
Signed-off-by: Tariq Toukan <tariqt@mellanox.com>
Signed-off-by: Jiri Pirko <jiri@mellanox.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
drivers/net/ethernet/mellanox/mlx4/fw.c
drivers/net/ethernet/mellanox/mlx4/fw.h
drivers/net/ethernet/mellanox/mlx4/main.c
include/linux/mlx4/device.h

index 46dcbfbe4c5eb0133ce49c2d222ebd7a2c8e7d44..babcfd9c0571fc6ffac47bd222304b62c65824c1 100644 (file)
@@ -825,7 +825,7 @@ int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
 #define QUERY_DEV_CAP_QP_RATE_LIMIT_NUM_OFFSET 0xcc
 #define QUERY_DEV_CAP_QP_RATE_LIMIT_MAX_OFFSET 0xd0
 #define QUERY_DEV_CAP_QP_RATE_LIMIT_MIN_OFFSET 0xd2
-
+#define QUERY_DEV_CAP_HEALTH_BUFFER_ADDRESS_OFFSET     0xe4
 
        dev_cap->flags2 = 0;
        mailbox = mlx4_alloc_cmd_mailbox(dev);
@@ -1082,6 +1082,9 @@ int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
                dev_cap->rl_caps.min_unit = size >> 14;
        }
 
+       MLX4_GET(dev_cap->health_buffer_addrs, outbox,
+                QUERY_DEV_CAP_HEALTH_BUFFER_ADDRESS_OFFSET);
+
        MLX4_GET(field32, outbox, QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET);
        if (field32 & (1 << 16))
                dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_UPDATE_QP;
index cd6399c76bfdb51887a1eba84150b642ef03cc30..650ae08c71def539ed50db6103a6c036170d1eae 100644 (file)
@@ -128,6 +128,7 @@ struct mlx4_dev_cap {
        u32 dmfs_high_rate_qpn_base;
        u32 dmfs_high_rate_qpn_range;
        struct mlx4_rate_limit_caps rl_caps;
+       u32 health_buffer_addrs;
        struct mlx4_port_cap port_cap[MLX4_MAX_PORTS + 1];
        bool wol_port[MLX4_MAX_PORTS + 1];
 };
index c42eddfcd2b5e30423da1b1d1e3704a88ef79770..806d441b3701e311482acaca8ccc4d88d082336f 100644 (file)
@@ -523,6 +523,7 @@ static int mlx4_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
        dev->caps.max_rss_tbl_sz     = dev_cap->max_rss_tbl_sz;
        dev->caps.wol_port[1]          = dev_cap->wol_port[1];
        dev->caps.wol_port[2]          = dev_cap->wol_port[2];
+       dev->caps.health_buffer_addrs  = dev_cap->health_buffer_addrs;
 
        /* Save uar page shift */
        if (!mlx4_is_slave(dev)) {
index 122e7e9d3091b5b55f4ded91ae7a9dccb620d193..e3bfe76aea9816bb55910bb7ac56ca74ee201003 100644 (file)
@@ -630,6 +630,7 @@ struct mlx4_caps {
        u32                     vf_caps;
        bool                    wol_port[MLX4_MAX_PORTS + 1];
        struct mlx4_rate_limit_caps rl_caps;
+       u32                     health_buffer_addrs;
 };
 
 struct mlx4_buf_list {