mt76: mt7915: enable Rx HE rate reporting
authorRyder Lee <ryder.lee@mediatek.com>
Fri, 24 Apr 2020 19:32:28 +0000 (03:32 +0800)
committerFelix Fietkau <nbd@nbd.name>
Tue, 12 May 2020 17:52:35 +0000 (19:52 +0200)
Enable HE rate reporting in Rx path

Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Signed-off-by: Shayne Chen <shayne.chen@mediatek.com>
Signed-off-by: Felix Fietkau <nbd@nbd.name>
drivers/net/wireless/mediatek/mt76/mt7915/init.c
drivers/net/wireless/mediatek/mt76/mt7915/mac.c
drivers/net/wireless/mediatek/mt76/mt7915/mac.h
drivers/net/wireless/mediatek/mt76/mt7915/regs.h

index fb596af..f9384e1 100644 (file)
@@ -43,6 +43,8 @@ static void mt7915_mac_init(struct mt7915_dev *dev)
 
        mt76_rmw_field(dev, MT_DMA_DCR0, MT_DMA_DCR0_MAX_RX_LEN, 1536);
        mt76_rmw_field(dev, MT_MDP_DCR1, MT_MDP_DCR1_MAX_RX_LEN, 1536);
+       /* enable rx rate report */
+       mt76_set(dev, MT_DMA_DCR0, MT_DMA_DCR0_RXD_G5_EN);
        /* disable hardware de-agg */
        mt76_clear(dev, MT_MDP_DCR0, MT_MDP_DCR0_DAMSDU_EN);
 
index ddba360..dd5b30a 100644 (file)
@@ -347,6 +347,22 @@ int mt7915_mac_fill_rx(struct mt7915_dev *dev, struct sk_buff *skb)
                                if (i > 9)
                                        return -EINVAL;
                                break;
+                       case MT_PHY_TYPE_HE_MU:
+                               /* fall through */
+                       case MT_PHY_TYPE_HE_SU:
+                       case MT_PHY_TYPE_HE_EXT_SU:
+                       case MT_PHY_TYPE_HE_TB:
+                               status->nss =
+                                       FIELD_GET(MT_PRXV_NSTS, rxv.v[0]) + 1;
+                               status->encoding = RX_ENC_HE;
+                               i &= GENMASK(3, 0);
+
+                               if (gi <= NL80211_RATE_INFO_HE_GI_3_2)
+                                       status->he_gi = gi;
+
+                               if (idx & MT_PRXV_TX_DCM)
+                                       status->he_dcm = true;
+                               break;
                        default:
                                return -EINVAL;
                        }
@@ -356,7 +372,14 @@ int mt7915_mac_fill_rx(struct mt7915_dev *dev, struct sk_buff *skb)
                        case IEEE80211_STA_RX_BW_20:
                                break;
                        case IEEE80211_STA_RX_BW_40:
-                               status->bw = RATE_INFO_BW_40;
+                               if (rxv.phy & MT_PHY_TYPE_HE_EXT_SU &&
+                                   (idx & MT_PRXV_TX_ER_SU_106T)) {
+                                       status->bw = RATE_INFO_BW_HE_RU;
+                                       status->he_ru =
+                                               NL80211_RATE_INFO_HE_RU_ALLOC_106;
+                               } else {
+                                       status->bw = RATE_INFO_BW_40;
+                               }
                                break;
                        case IEEE80211_STA_RX_BW_80:
                                status->bw = RATE_INFO_BW_80;
@@ -369,7 +392,7 @@ int mt7915_mac_fill_rx(struct mt7915_dev *dev, struct sk_buff *skb)
                        }
 
                        status->enc_flags |= RX_ENC_FLAG_STBC_MASK * stbc;
-                       if (gi)
+                       if (rxv.phy < MT_PHY_TYPE_HE_SU && gi)
                                status->enc_flags |= RX_ENC_FLAG_SHORT_GI;
                }
        }
index 7da7551..7127534 100644 (file)
@@ -97,6 +97,8 @@ enum rx_pkt_type {
 
 /* P-RXV */
 #define MT_PRXV_TX_RATE                        GENMASK(6, 0)
+#define MT_PRXV_TX_DCM                 BIT(4)
+#define MT_PRXV_TX_ER_SU_106T          BIT(5)
 #define MT_PRXV_NSTS                   GENMASK(9, 7)
 #define MT_PRXV_HT_AD_CODE             BIT(11)
 #define MT_PRXV_RCPI3                  GENMASK(31, 24)
index ef87579..572bdc1 100644 (file)
@@ -73,6 +73,7 @@
 
 #define MT_DMA_DCR0                    MT_WF_DMA(0x000)
 #define MT_DMA_DCR0_MAX_RX_LEN         GENMASK(15, 3)
+#define MT_DMA_DCR0_RXD_G5_EN          BIT(23)
 
 /* MIB: band 0(0x24800), band 1(0xa4800) */
 #define MT_WF_MIB_BASE(_band)          ((_band) ? 0xa4800 : 0x24800)