media: hantro: Auto generate the AXI ID to avoid conflicts
authorBenjamin Gaignard <benjamin.gaignard@collabora.com>
Fri, 24 Sep 2021 13:24:47 +0000 (15:24 +0200)
committerMauro Carvalho Chehab <mchehab+huawei@kernel.org>
Tue, 5 Oct 2021 07:40:17 +0000 (09:40 +0200)
The AXI ID is an AXI bus configuration for improve bus performance.
If read and write operations use different IDs the operations can be
paralleled, whereas when they have the same ID the operations will be
serialized. Right now, the write ID is fixed to 0 but we can set it to
0xff to get auto generated IDs to avoid possible conflicts.

This change has no functional changes, but seems reasonable to let the
hardware to autogenerate the ID instead of hardcoding in software.

Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com>
Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
drivers/staging/media/hantro/hantro_g1_h264_dec.c
drivers/staging/media/hantro/hantro_g1_regs.h
drivers/staging/media/hantro/hantro_g1_vp8_dec.c

index 236ce24..f49dbfb 100644 (file)
@@ -29,7 +29,7 @@ static void set_params(struct hantro_ctx *ctx, struct vb2_v4l2_buffer *src_buf)
        u32 reg;
 
        /* Decoder control register 0. */
-       reg = G1_REG_DEC_CTRL0_DEC_AXI_WR_ID(0x0);
+       reg = G1_REG_DEC_CTRL0_DEC_AXI_AUTO;
        if (sps->flags & V4L2_H264_SPS_FLAG_MB_ADAPTIVE_FRAME_FIELD)
                reg |= G1_REG_DEC_CTRL0_SEQ_MBAFF_E;
        if (sps->profile_idc > 66) {
index c1756e3..c623b3b 100644 (file)
@@ -68,6 +68,8 @@
 #define     G1_REG_DEC_CTRL0_PICORD_COUNT_E            BIT(9)
 #define     G1_REG_DEC_CTRL0_DEC_AHB_HLOCK_E           BIT(8)
 #define     G1_REG_DEC_CTRL0_DEC_AXI_WR_ID(x)          (((x) & 0xff) << 0)
+/* Setting AXI ID to 0xff to get auto generated ID to avoid possible conflicts */
+#define     G1_REG_DEC_CTRL0_DEC_AXI_AUTO              G1_REG_DEC_CTRL0_DEC_AXI_WR_ID(0xff)
 #define G1_REG_DEC_CTRL1                               0x010
 #define     G1_REG_DEC_CTRL1_PIC_MB_WIDTH(x)           (((x) & 0x1ff) << 23)
 #define     G1_REG_DEC_CTRL1_MB_WIDTH_OFF(x)           (((x) & 0xf) << 19)
index 6180b23..851eb67 100644 (file)
@@ -463,7 +463,8 @@ int hantro_g1_vp8_dec_run(struct hantro_ctx *ctx)
              G1_REG_CONFIG_DEC_MAX_BURST(16);
        vdpu_write_relaxed(vpu, reg, G1_REG_CONFIG);
 
-       reg = G1_REG_DEC_CTRL0_DEC_MODE(10);
+       reg = G1_REG_DEC_CTRL0_DEC_MODE(10) |
+             G1_REG_DEC_CTRL0_DEC_AXI_AUTO;
        if (!V4L2_VP8_FRAME_IS_KEY_FRAME(hdr))
                reg |= G1_REG_DEC_CTRL0_PIC_INTER_E;
        if (!(hdr->flags & V4L2_VP8_FRAME_FLAG_MB_NO_SKIP_COEFF))