arm: imx: Codingstyle enhancement of include/asm/arch-mx6/crm_regs.h

Add spaces before and after "<<".

Please note that I intentionally didn't wrap the > 80 lines for
the sake of better readability.

Signed-off-by: Stefan Roese <sr@denx.de>

diff --git a/arch/arm/include/asm/arch-mx6/crm_regs.h b/arch/arm/include/asm/arch-mx6/crm_regs.h
index df6f09f5f76c8fa42ebb04e59b90d40a67b99292..f16bd92abcca5303d183296b42911cdb39a6ea2d 100644 (file)
--- a/arch/arm/include/asm/arch-mx6/crm_regs.h
+++ b/arch/arm/include/asm/arch-mx6/crm_regs.h
@@ -420,183 +420,183 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CCGR_CG_MASK                           3
 
 #define MXC_CCM_CCGR0_AIPS_TZ1_OFFSET                  0
-#define MXC_CCM_CCGR0_AIPS_TZ1_MASK                    (3<<MXC_CCM_CCGR0_AIPS_TZ1_OFFSET)
+#define MXC_CCM_CCGR0_AIPS_TZ1_MASK                    (3 << MXC_CCM_CCGR0_AIPS_TZ1_OFFSET)
 #define MXC_CCM_CCGR0_AIPS_TZ2_OFFSET                  2
-#define MXC_CCM_CCGR0_AIPS_TZ2_MASK                    (3<<MXC_CCM_CCGR0_AIPS_TZ2_OFFSET)
+#define MXC_CCM_CCGR0_AIPS_TZ2_MASK                    (3 << MXC_CCM_CCGR0_AIPS_TZ2_OFFSET)
 #define MXC_CCM_CCGR0_APBHDMA_OFFSET                   4
-#define MXC_CCM_CCGR0_APBHDMA_MASK                     (3<<MXC_CCM_CCGR0_APBHDMA_OFFSET)
+#define MXC_CCM_CCGR0_APBHDMA_MASK                     (3 << MXC_CCM_CCGR0_APBHDMA_OFFSET)
 #define MXC_CCM_CCGR0_ASRC_OFFSET                      6
-#define MXC_CCM_CCGR0_ASRC_MASK                                (3<<MXC_CCM_CCGR0_ASRC_OFFSET)
+#define MXC_CCM_CCGR0_ASRC_MASK                                (3 << MXC_CCM_CCGR0_ASRC_OFFSET)
 #define MXC_CCM_CCGR0_CAAM_SECURE_MEM_OFFSET           8
-#define MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK             (3<<MXC_CCM_CCGR0_CAAM_SECURE_MEM_OFFSET)
+#define MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK             (3 << MXC_CCM_CCGR0_CAAM_SECURE_MEM_OFFSET)
 #define MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_OFFSET         10
-#define MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK           (3<<MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_OFFSET)
+#define MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK           (3 << MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_OFFSET)
 #define MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_OFFSET          12
-#define MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK            (3<<MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_OFFSET)
+#define MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK            (3 << MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_OFFSET)
 #define MXC_CCM_CCGR0_CAN1_OFFSET                      14
-#define MXC_CCM_CCGR0_CAN1_MASK                                (3<<MXC_CCM_CCGR0_CAN1_OFFSET)
+#define MXC_CCM_CCGR0_CAN1_MASK                                (3 << MXC_CCM_CCGR0_CAN1_OFFSET)
 #define MXC_CCM_CCGR0_CAN1_SERIAL_OFFSET               16
-#define MXC_CCM_CCGR0_CAN1_SERIAL_MASK                 (3<<MXC_CCM_CCGR0_CAN1_SERIAL_OFFSET)
+#define MXC_CCM_CCGR0_CAN1_SERIAL_MASK                 (3 << MXC_CCM_CCGR0_CAN1_SERIAL_OFFSET)
 #define MXC_CCM_CCGR0_CAN2_OFFSET                      18
-#define MXC_CCM_CCGR0_CAN2_MASK                                (3<<MXC_CCM_CCGR0_CAN2_OFFSET)
+#define MXC_CCM_CCGR0_CAN2_MASK                                (3 << MXC_CCM_CCGR0_CAN2_OFFSET)
 #define MXC_CCM_CCGR0_CAN2_SERIAL_OFFSET               20
-#define MXC_CCM_CCGR0_CAN2_SERIAL_MASK                 (3<<MXC_CCM_CCGR0_CAN2_SERIAL_OFFSET)
+#define MXC_CCM_CCGR0_CAN2_SERIAL_MASK                 (3 << MXC_CCM_CCGR0_CAN2_SERIAL_OFFSET)
 #define MXC_CCM_CCGR0_CHEETAH_DBG_CLK_OFFSET           22
-#define MXC_CCM_CCGR0_CHEETAH_DBG_CLK_MASK             (3<<MXC_CCM_CCGR0_CHEETAH_DBG_CLK_OFFSET)
+#define MXC_CCM_CCGR0_CHEETAH_DBG_CLK_MASK             (3 << MXC_CCM_CCGR0_CHEETAH_DBG_CLK_OFFSET)
 #define MXC_CCM_CCGR0_DCIC1_OFFSET                     24
-#define MXC_CCM_CCGR0_DCIC1_MASK                       (3<<MXC_CCM_CCGR0_DCIC1_OFFSET)
+#define MXC_CCM_CCGR0_DCIC1_MASK                       (3 << MXC_CCM_CCGR0_DCIC1_OFFSET)
 #define MXC_CCM_CCGR0_DCIC2_OFFSET                     26
-#define MXC_CCM_CCGR0_DCIC2_MASK                       (3<<MXC_CCM_CCGR0_DCIC2_OFFSET)
+#define MXC_CCM_CCGR0_DCIC2_MASK                       (3 << MXC_CCM_CCGR0_DCIC2_OFFSET)
 #define MXC_CCM_CCGR0_DTCP_OFFSET                      28
-#define MXC_CCM_CCGR0_DTCP_MASK                                (3<<MXC_CCM_CCGR0_DTCP_OFFSET)
+#define MXC_CCM_CCGR0_DTCP_MASK                                (3 << MXC_CCM_CCGR0_DTCP_OFFSET)
 
 #define MXC_CCM_CCGR1_ECSPI1S_OFFSET                   0
-#define MXC_CCM_CCGR1_ECSPI1S_MASK                     (3<<MXC_CCM_CCGR1_ECSPI1S_OFFSET)
+#define MXC_CCM_CCGR1_ECSPI1S_MASK                     (3 << MXC_CCM_CCGR1_ECSPI1S_OFFSET)
 #define MXC_CCM_CCGR1_ECSPI2S_OFFSET                   2
-#define MXC_CCM_CCGR1_ECSPI2S_MASK                     (3<<MXC_CCM_CCGR1_ECSPI2S_OFFSET)
+#define MXC_CCM_CCGR1_ECSPI2S_MASK                     (3 << MXC_CCM_CCGR1_ECSPI2S_OFFSET)
 #define MXC_CCM_CCGR1_ECSPI3S_OFFSET                   4
-#define MXC_CCM_CCGR1_ECSPI3S_MASK                     (3<<MXC_CCM_CCGR1_ECSPI3S_OFFSET)
+#define MXC_CCM_CCGR1_ECSPI3S_MASK                     (3 << MXC_CCM_CCGR1_ECSPI3S_OFFSET)
 #define MXC_CCM_CCGR1_ECSPI4S_OFFSET                   6
-#define MXC_CCM_CCGR1_ECSPI4S_MASK                     (3<<MXC_CCM_CCGR1_ECSPI4S_OFFSET)
+#define MXC_CCM_CCGR1_ECSPI4S_MASK                     (3 << MXC_CCM_CCGR1_ECSPI4S_OFFSET)
 #define MXC_CCM_CCGR1_ECSPI5S_OFFSET                   8
-#define MXC_CCM_CCGR1_ECSPI5S_MASK                     (3<<MXC_CCM_CCGR1_ECSPI5S_OFFSET)
+#define MXC_CCM_CCGR1_ECSPI5S_MASK                     (3 << MXC_CCM_CCGR1_ECSPI5S_OFFSET)
 #define MXC_CCM_CCGR1_ENET_CLK_ENABLE_OFFSET           10
-#define MXC_CCM_CCGR1_ENET_CLK_ENABLE_MASK             (3<<MXC_CCM_CCGR1_ENET_CLK_ENABLE_OFFSET)
+#define MXC_CCM_CCGR1_ENET_CLK_ENABLE_MASK             (3 << MXC_CCM_CCGR1_ENET_CLK_ENABLE_OFFSET)
 #define MXC_CCM_CCGR1_EPIT1S_OFFSET                    12
-#define MXC_CCM_CCGR1_EPIT1S_MASK                      (3<<MXC_CCM_CCGR1_EPIT1S_OFFSET)
+#define MXC_CCM_CCGR1_EPIT1S_MASK                      (3 << MXC_CCM_CCGR1_EPIT1S_OFFSET)
 #define MXC_CCM_CCGR1_EPIT2S_OFFSET                    14
-#define MXC_CCM_CCGR1_EPIT2S_MASK                      (3<<MXC_CCM_CCGR1_EPIT2S_OFFSET)
+#define MXC_CCM_CCGR1_EPIT2S_MASK                      (3 << MXC_CCM_CCGR1_EPIT2S_OFFSET)
 #define MXC_CCM_CCGR1_ESAIS_OFFSET                     16
-#define MXC_CCM_CCGR1_ESAIS_MASK                       (3<<MXC_CCM_CCGR1_ESAIS_OFFSET)
+#define MXC_CCM_CCGR1_ESAIS_MASK                       (3 << MXC_CCM_CCGR1_ESAIS_OFFSET)
 #define MXC_CCM_CCGR1_GPT_BUS_OFFSET                   20
-#define MXC_CCM_CCGR1_GPT_BUS_MASK                     (3<<MXC_CCM_CCGR1_GPT_BUS_OFFSET)
+#define MXC_CCM_CCGR1_GPT_BUS_MASK                     (3 << MXC_CCM_CCGR1_GPT_BUS_OFFSET)
 #define MXC_CCM_CCGR1_GPT_SERIAL_OFFSET                        22
-#define MXC_CCM_CCGR1_GPT_SERIAL_MASK                  (3<<MXC_CCM_CCGR1_GPT_SERIAL_OFFSET)
+#define MXC_CCM_CCGR1_GPT_SERIAL_MASK                  (3 << MXC_CCM_CCGR1_GPT_SERIAL_OFFSET)
 #define MXC_CCM_CCGR1_GPU2D_OFFSET                     24
-#define MXC_CCM_CCGR1_GPU2D_MASK                       (3<<MXC_CCM_CCGR1_GPU2D_OFFSET)
+#define MXC_CCM_CCGR1_GPU2D_MASK                       (3 << MXC_CCM_CCGR1_GPU2D_OFFSET)
 #define MXC_CCM_CCGR1_GPU3D_OFFSET                     26
-#define MXC_CCM_CCGR1_GPU3D_MASK                       (3<<MXC_CCM_CCGR1_GPU3D_OFFSET)
+#define MXC_CCM_CCGR1_GPU3D_MASK                       (3 << MXC_CCM_CCGR1_GPU3D_OFFSET)
 
 #define MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_OFFSET           0
-#define MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK             (3<<MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_OFFSET)
+#define MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK             (3 << MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_OFFSET)
 #define MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_OFFSET           4
-#define MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK             (3<<MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_OFFSET)
+#define MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK             (3 << MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_OFFSET)
 #define MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET               6
-#define MXC_CCM_CCGR2_I2C1_SERIAL_MASK                 (3<<MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET)
+#define MXC_CCM_CCGR2_I2C1_SERIAL_MASK                 (3 << MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET)
 #define MXC_CCM_CCGR2_I2C2_SERIAL_OFFSET               8
-#define MXC_CCM_CCGR2_I2C2_SERIAL_MASK                 (3<<MXC_CCM_CCGR2_I2C2_SERIAL_OFFSET)
+#define MXC_CCM_CCGR2_I2C2_SERIAL_MASK                 (3 << MXC_CCM_CCGR2_I2C2_SERIAL_OFFSET)
 #define MXC_CCM_CCGR2_I2C3_SERIAL_OFFSET               10
-#define MXC_CCM_CCGR2_I2C3_SERIAL_MASK                 (3<<MXC_CCM_CCGR2_I2C3_SERIAL_OFFSET)
+#define MXC_CCM_CCGR2_I2C3_SERIAL_MASK                 (3 << MXC_CCM_CCGR2_I2C3_SERIAL_OFFSET)
 #define MXC_CCM_CCGR2_OCOTP_CTRL_OFFSET                        12
-#define MXC_CCM_CCGR2_OCOTP_CTRL_MASK                  (3<<MXC_CCM_CCGR2_OCOTP_CTRL_OFFSET)
+#define MXC_CCM_CCGR2_OCOTP_CTRL_MASK                  (3 << MXC_CCM_CCGR2_OCOTP_CTRL_OFFSET)
 #define MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_OFFSET          14
-#define MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK            (3<<MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_OFFSET)
+#define MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK            (3 << MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_OFFSET)
 #define MXC_CCM_CCGR2_IPMUX1_OFFSET                    16
-#define MXC_CCM_CCGR2_IPMUX1_MASK                      (3<<MXC_CCM_CCGR2_IPMUX1_OFFSET)
+#define MXC_CCM_CCGR2_IPMUX1_MASK                      (3 << MXC_CCM_CCGR2_IPMUX1_OFFSET)
 #define MXC_CCM_CCGR2_IPMUX2_OFFSET                    18
-#define MXC_CCM_CCGR2_IPMUX2_MASK                      (3<<MXC_CCM_CCGR2_IPMUX2_OFFSET)
+#define MXC_CCM_CCGR2_IPMUX2_MASK                      (3 << MXC_CCM_CCGR2_IPMUX2_OFFSET)
 #define MXC_CCM_CCGR2_IPMUX3_OFFSET                    20
-#define MXC_CCM_CCGR2_IPMUX3_MASK                      (3<<MXC_CCM_CCGR2_IPMUX3_OFFSET)
+#define MXC_CCM_CCGR2_IPMUX3_MASK                      (3 << MXC_CCM_CCGR2_IPMUX3_OFFSET)
 #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_OFFSET 22
-#define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_MASK   (3<<MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_OFFSET)
+#define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_MASK   (3 << MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_OFFSET)
 #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_OFFSET  24
-#define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_MASK    (3<<MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_OFFSET)
+#define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_MASK    (3 << MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_OFFSET)
 #define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_OFFSET        26
-#define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_MASK  (3<<MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_OFFSET)
+#define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_MASK  (3 << MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_OFFSET)
 
 #define MXC_CCM_CCGR3_IPU1_IPU_OFFSET                          0
-#define MXC_CCM_CCGR3_IPU1_IPU_MASK                            (3<<MXC_CCM_CCGR3_IPU1_IPU_OFFSET)
+#define MXC_CCM_CCGR3_IPU1_IPU_MASK                            (3 << MXC_CCM_CCGR3_IPU1_IPU_OFFSET)
 #define MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET                      2
-#define MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK                                (3<<MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET)
+#define MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK                                (3 << MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET)
 #define MXC_CCM_CCGR3_IPU1_IPU_DI1_OFFSET                      4
-#define MXC_CCM_CCGR3_IPU1_IPU_DI1_MASK                                (3<<MXC_CCM_CCGR3_IPU1_IPU_DI1_OFFSET)
+#define MXC_CCM_CCGR3_IPU1_IPU_DI1_MASK                                (3 << MXC_CCM_CCGR3_IPU1_IPU_DI1_OFFSET)
 #define MXC_CCM_CCGR3_IPU2_IPU_OFFSET                          6
-#define MXC_CCM_CCGR3_IPU2_IPU_MASK                            (3<<MXC_CCM_CCGR3_IPU2_IPU_OFFSET)
+#define MXC_CCM_CCGR3_IPU2_IPU_MASK                            (3 << MXC_CCM_CCGR3_IPU2_IPU_OFFSET)
 #define MXC_CCM_CCGR3_IPU2_IPU_DI0_OFFSET                      8
-#define MXC_CCM_CCGR3_IPU2_IPU_DI0_MASK                                (3<<MXC_CCM_CCGR3_IPU2_IPU_DI0_OFFSET)
+#define MXC_CCM_CCGR3_IPU2_IPU_DI0_MASK                                (3 << MXC_CCM_CCGR3_IPU2_IPU_DI0_OFFSET)
 #define MXC_CCM_CCGR3_IPU2_IPU_DI1_OFFSET                      10
-#define MXC_CCM_CCGR3_IPU2_IPU_DI1_MASK                                (3<<MXC_CCM_CCGR3_IPU2_IPU_DI1_OFFSET)
+#define MXC_CCM_CCGR3_IPU2_IPU_DI1_MASK                                (3 << MXC_CCM_CCGR3_IPU2_IPU_DI1_OFFSET)
 #define MXC_CCM_CCGR3_LDB_DI0_OFFSET                           12
-#define MXC_CCM_CCGR3_LDB_DI0_MASK                             (3<<MXC_CCM_CCGR3_LDB_DI0_OFFSET)
+#define MXC_CCM_CCGR3_LDB_DI0_MASK                             (3 << MXC_CCM_CCGR3_LDB_DI0_OFFSET)
 #define MXC_CCM_CCGR3_LDB_DI1_OFFSET                           14
-#define MXC_CCM_CCGR3_LDB_DI1_MASK                             (3<<MXC_CCM_CCGR3_LDB_DI1_OFFSET)
+#define MXC_CCM_CCGR3_LDB_DI1_MASK                             (3 << MXC_CCM_CCGR3_LDB_DI1_OFFSET)
 #define MXC_CCM_CCGR3_MIPI_CORE_CFG_OFFSET                     16
-#define MXC_CCM_CCGR3_MIPI_CORE_CFG_MASK                       (3<<MXC_CCM_CCGR3_MIPI_CORE_CFG_OFFSET)
+#define MXC_CCM_CCGR3_MIPI_CORE_CFG_MASK                       (3 << MXC_CCM_CCGR3_MIPI_CORE_CFG_OFFSET)
 #define MXC_CCM_CCGR3_MLB_OFFSET                               18
-#define MXC_CCM_CCGR3_MLB_MASK                                 (3<<MXC_CCM_CCGR3_MLB_OFFSET)
+#define MXC_CCM_CCGR3_MLB_MASK                                 (3 << MXC_CCM_CCGR3_MLB_OFFSET)
 #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_OFFSET       20
-#define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_MASK         (3<<MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_OFFSET)
+#define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_MASK         (3 << MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_OFFSET)
 #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_OFFSET       22
-#define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_MASK         (3<<MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_OFFSET)
+#define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_MASK         (3 << MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_OFFSET)
 #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_OFFSET              24
-#define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_MASK                        (3<<MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_OFFSET)
+#define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_MASK                        (3 << MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_OFFSET)
 #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_OFFSET              26
-#define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_MASK                        (3<<MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_OFFSET)
+#define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_MASK                        (3 << MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_OFFSET)
 #define MXC_CCM_CCGR3_OCRAM_OFFSET                             28
-#define MXC_CCM_CCGR3_OCRAM_MASK                               (3<<MXC_CCM_CCGR3_OCRAM_OFFSET)
+#define MXC_CCM_CCGR3_OCRAM_MASK                               (3 << MXC_CCM_CCGR3_OCRAM_OFFSET)
 #define MXC_CCM_CCGR3_OPENVGAXICLK_OFFSET                      30
-#define MXC_CCM_CCGR3_OPENVGAXICLK_MASK                                (3<<MXC_CCM_CCGR3_OPENVGAXICLK_OFFSET)
+#define MXC_CCM_CCGR3_OPENVGAXICLK_MASK                                (3 << MXC_CCM_CCGR3_OPENVGAXICLK_OFFSET)
 
 #define MXC_CCM_CCGR4_PCIE_OFFSET                              0
-#define MXC_CCM_CCGR4_PCIE_MASK                                        (3<<MXC_CCM_CCGR4_PCIE_OFFSET)
+#define MXC_CCM_CCGR4_PCIE_MASK                                        (3 << MXC_CCM_CCGR4_PCIE_OFFSET)
 #define MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_OFFSET              8
-#define MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_MASK                        (3<<MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_OFFSET)
+#define MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_MASK                        (3 << MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_OFFSET)
 #define MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET                        12
-#define MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK                  (3<<MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET)
+#define MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK                  (3 << MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET)
 #define MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_OFFSET     14
-#define MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_MASK       (3<<MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_OFFSET)
+#define MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_MASK       (3 << MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_OFFSET)
 #define MXC_CCM_CCGR4_PWM1_OFFSET                              16
-#define MXC_CCM_CCGR4_PWM1_MASK                                        (3<<MXC_CCM_CCGR4_PWM1_OFFSET)
+#define MXC_CCM_CCGR4_PWM1_MASK                                        (3 << MXC_CCM_CCGR4_PWM1_OFFSET)
 #define MXC_CCM_CCGR4_PWM2_OFFSET                              18
-#define MXC_CCM_CCGR4_PWM2_MASK                                        (3<<MXC_CCM_CCGR4_PWM2_OFFSET)
+#define MXC_CCM_CCGR4_PWM2_MASK                                        (3 << MXC_CCM_CCGR4_PWM2_OFFSET)
 #define MXC_CCM_CCGR4_PWM3_OFFSET                              20
-#define MXC_CCM_CCGR4_PWM3_MASK                                        (3<<MXC_CCM_CCGR4_PWM3_OFFSET)
+#define MXC_CCM_CCGR4_PWM3_MASK                                        (3 << MXC_CCM_CCGR4_PWM3_OFFSET)
 #define MXC_CCM_CCGR4_PWM4_OFFSET                              22
-#define MXC_CCM_CCGR4_PWM4_MASK                                        (3<<MXC_CCM_CCGR4_PWM4_OFFSET)
+#define MXC_CCM_CCGR4_PWM4_MASK                                        (3 << MXC_CCM_CCGR4_PWM4_OFFSET)
 #define MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_OFFSET           24
-#define MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK             (3<<MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_OFFSET)
+#define MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK             (3 << MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_OFFSET)
 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_OFFSET      26
-#define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK                (3<<MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_OFFSET)
+#define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK                (3 << MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_OFFSET)
 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_OFFSET  28
-#define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK    (3<<MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_OFFSET)
+#define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK    (3 << MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_OFFSET)
 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_OFFSET          30
-#define MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK            (3<<MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_OFFSET)
+#define MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK            (3 << MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_OFFSET)
 
 #define MXC_CCM_CCGR5_ROM_OFFSET                       0
-#define MXC_CCM_CCGR5_ROM_MASK                         (3<<MXC_CCM_CCGR5_ROM_OFFSET)
+#define MXC_CCM_CCGR5_ROM_MASK                         (3 << MXC_CCM_CCGR5_ROM_OFFSET)
 #define MXC_CCM_CCGR5_SATA_OFFSET                      4
-#define MXC_CCM_CCGR5_SATA_MASK                                (3<<MXC_CCM_CCGR5_SATA_OFFSET)
+#define MXC_CCM_CCGR5_SATA_MASK                                (3 << MXC_CCM_CCGR5_SATA_OFFSET)
 #define MXC_CCM_CCGR5_SDMA_OFFSET                      6
-#define MXC_CCM_CCGR5_SDMA_MASK                                (3<<MXC_CCM_CCGR5_SDMA_OFFSET)
+#define MXC_CCM_CCGR5_SDMA_MASK                                (3 << MXC_CCM_CCGR5_SDMA_OFFSET)
 #define MXC_CCM_CCGR5_SPBA_OFFSET                      12
-#define MXC_CCM_CCGR5_SPBA_MASK                                (3<<MXC_CCM_CCGR5_SPBA_OFFSET)
+#define MXC_CCM_CCGR5_SPBA_MASK                                (3 << MXC_CCM_CCGR5_SPBA_OFFSET)
 #define MXC_CCM_CCGR5_SPDIF_OFFSET                     14
-#define MXC_CCM_CCGR5_SPDIF_MASK                       (3<<MXC_CCM_CCGR5_SPDIF_OFFSET)
+#define MXC_CCM_CCGR5_SPDIF_MASK                       (3 << MXC_CCM_CCGR5_SPDIF_OFFSET)
 #define MXC_CCM_CCGR5_SSI1_OFFSET                      18
-#define MXC_CCM_CCGR5_SSI1_MASK                                (3<<MXC_CCM_CCGR5_SSI1_OFFSET)
+#define MXC_CCM_CCGR5_SSI1_MASK                                (3 << MXC_CCM_CCGR5_SSI1_OFFSET)
 #define MXC_CCM_CCGR5_SSI2_OFFSET                      20
-#define MXC_CCM_CCGR5_SSI2_MASK                                (3<<MXC_CCM_CCGR5_SSI2_OFFSET)
+#define MXC_CCM_CCGR5_SSI2_MASK                                (3 << MXC_CCM_CCGR5_SSI2_OFFSET)
 #define MXC_CCM_CCGR5_SSI3_OFFSET                      22
-#define MXC_CCM_CCGR5_SSI3_MASK                                (3<<MXC_CCM_CCGR5_SSI3_OFFSET)
+#define MXC_CCM_CCGR5_SSI3_MASK                                (3 << MXC_CCM_CCGR5_SSI3_OFFSET)
 #define MXC_CCM_CCGR5_UART_OFFSET                      24
-#define MXC_CCM_CCGR5_UART_MASK                                (3<<MXC_CCM_CCGR5_UART_OFFSET)
+#define MXC_CCM_CCGR5_UART_MASK                                (3 << MXC_CCM_CCGR5_UART_OFFSET)
 #define MXC_CCM_CCGR5_UART_SERIAL_OFFSET               26
-#define MXC_CCM_CCGR5_UART_SERIAL_MASK                 (3<<MXC_CCM_CCGR5_UART_SERIAL_OFFSET)
+#define MXC_CCM_CCGR5_UART_SERIAL_MASK                 (3 << MXC_CCM_CCGR5_UART_SERIAL_OFFSET)
 
 #define MXC_CCM_CCGR6_USBOH3_OFFSET            0
-#define MXC_CCM_CCGR6_USBOH3_MASK              (3<<MXC_CCM_CCGR6_USBOH3_OFFSET)
+#define MXC_CCM_CCGR6_USBOH3_MASK              (3 << MXC_CCM_CCGR6_USBOH3_OFFSET)
 #define MXC_CCM_CCGR6_USDHC1_OFFSET            2
-#define MXC_CCM_CCGR6_USDHC1_MASK              (3<<MXC_CCM_CCGR6_USDHC1_OFFSET)
+#define MXC_CCM_CCGR6_USDHC1_MASK              (3 << MXC_CCM_CCGR6_USDHC1_OFFSET)
 #define MXC_CCM_CCGR6_USDHC2_OFFSET            4
-#define MXC_CCM_CCGR6_USDHC2_MASK              (3<<MXC_CCM_CCGR6_USDHC2_OFFSET)
+#define MXC_CCM_CCGR6_USDHC2_MASK              (3 << MXC_CCM_CCGR6_USDHC2_OFFSET)
 #define MXC_CCM_CCGR6_USDHC3_OFFSET            6
-#define MXC_CCM_CCGR6_USDHC3_MASK              (3<<MXC_CCM_CCGR6_USDHC3_OFFSET)
+#define MXC_CCM_CCGR6_USDHC3_MASK              (3 << MXC_CCM_CCGR6_USDHC3_OFFSET)
 #define MXC_CCM_CCGR6_USDHC4_OFFSET            8
-#define MXC_CCM_CCGR6_USDHC4_MASK              (3<<MXC_CCM_CCGR6_USDHC4_OFFSET)
+#define MXC_CCM_CCGR6_USDHC4_MASK              (3 << MXC_CCM_CCGR6_USDHC4_OFFSET)
 #define MXC_CCM_CCGR6_EMI_SLOW_OFFSET          10
-#define MXC_CCM_CCGR6_EMI_SLOW_MASK            (3<<MXC_CCM_CCGR6_EMI_SLOW_OFFSET)
+#define MXC_CCM_CCGR6_EMI_SLOW_MASK            (3 << MXC_CCM_CCGR6_EMI_SLOW_OFFSET)
 #define MXC_CCM_CCGR6_VDOAXICLK_OFFSET         12
-#define MXC_CCM_CCGR6_VDOAXICLK_MASK           (3<<MXC_CCM_CCGR6_VDOAXICLK_OFFSET)
+#define MXC_CCM_CCGR6_VDOAXICLK_MASK           (3 << MXC_CCM_CCGR6_VDOAXICLK_OFFSET)
 
 #define BM_ANADIG_PLL_SYS_LOCK 0x80000000
 #define BP_ANADIG_PLL_SYS_RSVD0      20