drm/msm/dpu: use dpu core's major version to enable data compress

Instead of using a feature bit to decide whether to enable data
compress or not for DSC use-cases, use dpu core's major version
instead by assigning the enable_compression op based on the
dpu core's major version.

To make this possible pass the struct dpu_mdss_version to
dpu_hw_intf_init().

This will avoid defining feature bits for every bit level details of
registers.

changes in v5:
	- none

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/546803/
Link: https://lore.kernel.org/r/20230712012003.2212-3-quic_abhinavk@quicinc.com
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
index 5b0f662..d766791 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
@@ -523,7 +523,7 @@ static void dpu_hw_intf_enable_compression(struct dpu_hw_intf *ctx)
 }
 
 static void _setup_intf_ops(struct dpu_hw_intf_ops *ops,
-               unsigned long cap)
+               unsigned long cap, const struct dpu_mdss_version *mdss_rev)
 {
        ops->setup_timing_gen = dpu_hw_intf_setup_timing_engine;
        ops->setup_prg_fetch  = dpu_hw_intf_setup_prg_fetch;
@@ -543,12 +543,12 @@ static void _setup_intf_ops(struct dpu_hw_intf_ops *ops,
                ops->disable_autorefresh = dpu_hw_intf_disable_autorefresh;
        }
 
-       if (cap & BIT(DPU_INTF_DATA_COMPRESS))
+       if (mdss_rev->core_major_ver >= 7)
                ops->enable_compression = dpu_hw_intf_enable_compression;
 }
 
 struct dpu_hw_intf *dpu_hw_intf_init(const struct dpu_intf_cfg *cfg,
-               void __iomem *addr)
+               void __iomem *addr, const struct dpu_mdss_version *mdss_rev)
 {
        struct dpu_hw_intf *c;
 
@@ -569,7 +569,7 @@ struct dpu_hw_intf *dpu_hw_intf_init(const struct dpu_intf_cfg *cfg,
         */
        c->idx = cfg->id;
        c->cap = cfg;
-       _setup_intf_ops(&c->ops, c->cap->features);
+       _setup_intf_ops(&c->ops, c->cap->features, mdss_rev);
 
        return c;
 }

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h
index 99e21c4..3b5f18d 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h
@@ -127,9 +127,10 @@ struct dpu_hw_intf {
  * interface catalog entry.
  * @cfg:  interface catalog entry for which driver object is required
  * @addr: mapped register io address of MDP
+ * @mdss_rev: dpu core's major and minor versions
  */
 struct dpu_hw_intf *dpu_hw_intf_init(const struct dpu_intf_cfg *cfg,
-               void __iomem *addr);
+               void __iomem *addr, const struct dpu_mdss_version *mdss_rev);
 
 /**
  * dpu_hw_intf_destroy(): Destroys INTF driver context

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
index e333f4e..4a53e2c 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
@@ -161,7 +161,7 @@ int dpu_rm_init(struct dpu_rm *rm,
                struct dpu_hw_intf *hw;
                const struct dpu_intf_cfg *intf = &cat->intf[i];
 
-               hw = dpu_hw_intf_init(intf, mmio);
+               hw = dpu_hw_intf_init(intf, mmio, cat->mdss_ver);
                if (IS_ERR(hw)) {
                        rc = PTR_ERR(hw);
                        DPU_ERROR("failed intf object creation: err %d\n", rc);