spi: dw: Add support for master mode selection for DWC SSI controller

Add support to select the controller mode as master mode by setting Bit 31
of CTRLR0 register. This feature is supported for controller versions above
v1.02.

Signed-off-by: Nandhini Srikandan <nandhini.srikandan@intel.com>
Acked-by: Serge Semin <fancer.lancer@gmail.com>
Link: https://lore.kernel.org/r/20220713042223.1458-4-nandhini.srikandan@intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>

diff --git a/drivers/spi/spi-dw-core.c b/drivers/spi/spi-dw-core.c
index 911ea9b..f87d97c 100644 (file)
--- a/drivers/spi/spi-dw-core.c
+++ b/drivers/spi/spi-dw-core.c
@@ -307,8 +307,9 @@ static u32 dw_spi_prepare_cr0(struct dw_spi *dws, struct spi_device *spi)
                if (spi->mode & SPI_LOOP)
                        cr0 |= DW_HSSI_CTRLR0_SRL;
 
-               if (dws->caps & DW_SPI_CAP_KEEMBAY_MST)
-                       cr0 |= DW_HSSI_CTRLR0_KEEMBAY_MST;
+               /* CTRLR0[31] MST */
+               if (dw_spi_ver_is_ge(dws, HSSI, 102A))
+                       cr0 |= DW_HSSI_CTRLR0_MST;
        }
 
        return cr0;

diff --git a/drivers/spi/spi-dw.h b/drivers/spi/spi-dw.h
index 79d853f..8b8f924 100644 (file)
--- a/drivers/spi/spi-dw.h
+++ b/drivers/spi/spi-dw.h
@@ -94,13 +94,7 @@
 #define DW_HSSI_CTRLR0_SCPOL                   BIT(9)
 #define DW_HSSI_CTRLR0_TMOD_MASK               GENMASK(11, 10)
 #define DW_HSSI_CTRLR0_SRL                     BIT(13)
-
-/*
- * For Keem Bay, CTRLR0[31] is used to select controller mode.
- * 0: SSI is slave
- * 1: SSI is master
- */
-#define DW_HSSI_CTRLR0_KEEMBAY_MST             BIT(31)
+#define DW_HSSI_CTRLR0_MST                     BIT(31)
 
 /* Bit fields in CTRLR1 */
 #define DW_SPI_NDF_MASK                                GENMASK(15, 0)