ASoC: fsl_micfil: Add new registers and new bit definition

MICFIL IP is upgraded on i.MX93 platform. These new registers and new
bit definition are added to complete the register list.

Signed-off-by: Chancel Liu <chancel.liu@nxp.com>
Acked-by: Shengjiu Wang <shengjiu.wang@gmail.com>
Link: https://lore.kernel.org/r/20230802052117.1293029-2-chancel.liu@nxp.com
Signed-off-by: Mark Brown <broonie@kernel.org>

diff --git a/sound/soc/fsl/fsl_micfil.c b/sound/soc/fsl/fsl_micfil.c
index fe28b27..7841881 100644 (file)
--- a/sound/soc/fsl/fsl_micfil.c
+++ b/sound/soc/fsl/fsl_micfil.c
@@ -825,6 +825,9 @@ static bool fsl_micfil_readable_reg(struct device *dev, unsigned int reg)
        case REG_MICFIL_DC_CTRL:
        case REG_MICFIL_OUT_CTRL:
        case REG_MICFIL_OUT_STAT:
+       case REG_MICFIL_FSYNC_CTRL:
+       case REG_MICFIL_VERID:
+       case REG_MICFIL_PARAM:
        case REG_MICFIL_VAD0_CTRL1:
        case REG_MICFIL_VAD0_CTRL2:
        case REG_MICFIL_VAD0_STAT:
@@ -849,6 +852,7 @@ static bool fsl_micfil_writeable_reg(struct device *dev, unsigned int reg)
        case REG_MICFIL_DC_CTRL:
        case REG_MICFIL_OUT_CTRL:
        case REG_MICFIL_OUT_STAT:       /* Write 1 to Clear */
+       case REG_MICFIL_FSYNC_CTRL:
        case REG_MICFIL_VAD0_CTRL1:
        case REG_MICFIL_VAD0_CTRL2:
        case REG_MICFIL_VAD0_STAT:      /* Write 1 to Clear */
@@ -873,6 +877,8 @@ static bool fsl_micfil_volatile_reg(struct device *dev, unsigned int reg)
        case REG_MICFIL_DATACH5:
        case REG_MICFIL_DATACH6:
        case REG_MICFIL_DATACH7:
+       case REG_MICFIL_VERID:
+       case REG_MICFIL_PARAM:
        case REG_MICFIL_VAD0_STAT:
        case REG_MICFIL_VAD0_NDATA:
                return true;

diff --git a/sound/soc/fsl/fsl_micfil.h b/sound/soc/fsl/fsl_micfil.h
index 9237a1c..b3c392e 100644 (file)
--- a/sound/soc/fsl/fsl_micfil.h
+++ b/sound/soc/fsl/fsl_micfil.h
@@ -24,6 +24,9 @@
 #define REG_MICFIL_DC_CTRL             0x64
 #define REG_MICFIL_OUT_CTRL            0x74
 #define REG_MICFIL_OUT_STAT            0x7C
+#define REG_MICFIL_FSYNC_CTRL          0x80
+#define REG_MICFIL_VERID               0x84
+#define REG_MICFIL_PARAM               0x88
 #define REG_MICFIL_VAD0_CTRL1          0x90
 #define REG_MICFIL_VAD0_CTRL2          0x94
 #define REG_MICFIL_VAD0_STAT           0x98
@@ -39,6 +42,8 @@
 #define MICFIL_CTRL1_DBG               BIT(28)
 #define MICFIL_CTRL1_SRES              BIT(27)
 #define MICFIL_CTRL1_DBGE              BIT(26)
+#define MICFIL_CTRL1_DECFILS           BIT(20)
+#define MICFIL_CTRL1_FSYNCEN           BIT(16)
 
 #define MICFIL_CTRL1_DISEL_DISABLE     0
 #define MICFIL_CTRL1_DISEL_DMA         1
@@ -82,6 +87,29 @@
 #define MICFIL_DC_CUTOFF_152Hz         2
 #define MICFIL_DC_BYPASS               3
 
+/* MICFIL VERID Register -- REG_MICFIL_VERID */
+#define MICFIL_VERID_MAJOR_SHIFT        24
+#define MICFIL_VERID_MAJOR_MASK         GENMASK(31, 24)
+#define MICFIL_VERID_MINOR_SHIFT        16
+#define MICFIL_VERID_MINOR_MASK         GENMASK(23, 16)
+#define MICFIL_VERID_FEATURE_SHIFT      0
+#define MICFIL_VERID_FEATURE_MASK       GENMASK(15, 0)
+
+/* MICFIL PARAM Register -- REG_MICFIL_PARAM */
+#define MICFIL_PARAM_NUM_HWVAD_SHIFT    24
+#define MICFIL_PARAM_NUM_HWVAD_MASK     GENMASK(27, 24)
+#define MICFIL_PARAM_HWVAD_ZCD          BIT(19)
+#define MICFIL_PARAM_HWVAD_ENERGY_MODE  BIT(17)
+#define MICFIL_PARAM_HWVAD              BIT(16)
+#define MICFIL_PARAM_DC_OUT_BYPASS      BIT(11)
+#define MICFIL_PARAM_DC_IN_BYPASS       BIT(10)
+#define MICFIL_PARAM_LOW_POWER          BIT(9)
+#define MICFIL_PARAM_FIL_OUT_WIDTH      BIT(8)
+#define MICFIL_PARAM_FIFO_PTRWID_SHIFT  4
+#define MICFIL_PARAM_FIFO_PTRWID_MASK   GENMASK(7, 4)
+#define MICFIL_PARAM_NPAIR_SHIFT        0
+#define MICFIL_PARAM_NPAIR_MASK         GENMASK(3, 0)
+
 /* MICFIL HWVAD0 Control 1 Register -- REG_MICFIL_VAD0_CTRL1*/
 #define MICFIL_VAD0_CTRL1_CHSEL                GENMASK(26, 24)
 #define MICFIL_VAD0_CTRL1_CICOSR       GENMASK(19, 16)