net/mlx5: Use helpers to allocate and free rl table entries

User helper routines to allocate and free rate limit table entries.
Subsequent patch extends use of these helpers to do allocation
during rate entry allocation callback.

Signed-off-by: Parav Pandit <parav@nvidia.com>
Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>

diff --git a/drivers/net/ethernet/mellanox/mlx5/core/rl.c b/drivers/net/ethernet/mellanox/mlx5/core/rl.c
index 2accc0f324f31053dac31d2c0f075bc390fb5960..208fd3cad9707a725f0441c324b2642fed85a55e 100644 (file)
--- a/drivers/net/ethernet/mellanox/mlx5/core/rl.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/rl.c
@@ -172,6 +172,35 @@ bool mlx5_rl_are_equal(struct mlx5_rate_limit *rl_0,
 }
 EXPORT_SYMBOL(mlx5_rl_are_equal);
 
+static int mlx5_rl_table_alloc(struct mlx5_rl_table *table)
+{
+       int i;
+
+       table->rl_entry = kcalloc(table->max_size, sizeof(struct mlx5_rl_entry),
+                                 GFP_KERNEL);
+       if (!table->rl_entry)
+               return -ENOMEM;
+
+       /* The index represents the index in HW rate limit table
+        * Index 0 is reserved for unlimited rate
+        */
+       for (i = 0; i < table->max_size; i++)
+               table->rl_entry[i].index = i + 1;
+
+       return 0;
+}
+
+static void mlx5_rl_table_free(struct mlx5_core_dev *dev, struct mlx5_rl_table *table)
+{
+       int i;
+
+       /* Clear all configured rates */
+       for (i = 0; i < table->max_size; i++)
+               if (table->rl_entry[i].refcount)
+                       mlx5_set_pp_rate_limit_cmd(dev, &table->rl_entry[i], false);
+       kfree(table->rl_entry);
+}
+
 int mlx5_rl_add_rate_raw(struct mlx5_core_dev *dev, void *rl_in, u16 uid,
                         bool dedicated_entry, u16 *index)
 {
@@ -302,7 +331,7 @@ EXPORT_SYMBOL(mlx5_rl_remove_rate);
 int mlx5_init_rl_table(struct mlx5_core_dev *dev)
 {
        struct mlx5_rl_table *table = &dev->priv.rl_table;
-       int i;
+       int err;
 
        mutex_init(&table->rl_lock);
        if (!MLX5_CAP_GEN(dev, qos) || !MLX5_CAP_QOS(dev, packet_pacing)) {
@@ -315,18 +344,10 @@ int mlx5_init_rl_table(struct mlx5_core_dev *dev)
        table->max_rate = MLX5_CAP_QOS(dev, packet_pacing_max_rate);
        table->min_rate = MLX5_CAP_QOS(dev, packet_pacing_min_rate);
 
-       table->rl_entry = kcalloc(table->max_size, sizeof(struct mlx5_rl_entry),
-                                 GFP_KERNEL);
-       if (!table->rl_entry)
-               return -ENOMEM;
-
-       /* The index represents the index in HW rate limit table
-        * Index 0 is reserved for unlimited rate
-        */
-       for (i = 0; i < table->max_size; i++)
-               table->rl_entry[i].index = i + 1;
+       err = mlx5_rl_table_alloc(table);
+       if (err)
+               return err;
 
-       /* Index 0 is reserved */
        mlx5_core_info(dev, "Rate limit: %u rates are supported, range: %uMbps to %uMbps\n",
                       table->max_size,
                       table->min_rate >> 10,
@@ -338,13 +359,9 @@ int mlx5_init_rl_table(struct mlx5_core_dev *dev)
 void mlx5_cleanup_rl_table(struct mlx5_core_dev *dev)
 {
        struct mlx5_rl_table *table = &dev->priv.rl_table;
-       int i;
 
-       /* Clear all configured rates */
-       for (i = 0; i < table->max_size; i++)
-               if (table->rl_entry[i].refcount)
-                       mlx5_set_pp_rate_limit_cmd(dev, &table->rl_entry[i],
-                                                  false);
+       if (!MLX5_CAP_GEN(dev, qos) || !MLX5_CAP_QOS(dev, packet_pacing))
+               return;
 
-       kfree(dev->priv.rl_table.rl_entry);
+       mlx5_rl_table_free(dev, table);
 }