}
}
+static u32 vc4_hvs6_get_alpha_mask_mode(struct drm_plane_state *state)
+{
+ struct drm_device *dev = state->state->dev;
+ struct vc4_dev *vc4 = to_vc4_dev(dev);
+
+ WARN_ON_ONCE(vc4->gen != VC4_GEN_6);
+
+ if (vc4->step_d0 && (!state->fb->format->has_alpha ||
+ state->pixel_blend_mode == DRM_MODE_BLEND_PIXEL_NONE))
+ return VC4_SET_FIELD(SCALER6_CTL0_ALPHA_MASK_FIXED,
+ SCALER6_CTL0_ALPHA_MASK);
+
+ return VC4_SET_FIELD(SCALER6_CTL0_ALPHA_MASK_NONE, SCALER6_CTL0_ALPHA_MASK);
+}
+
/* Writes out a full display list for an active plane to the plane's
* private dlist state.
*/
vc4_dlist_write(vc4_state,
SCALER6_CTL0_VALID |
VC4_SET_FIELD(tiling, SCALER6_CTL0_ADDR_MODE) |
- VC4_SET_FIELD(0, SCALER6_CTL0_ALPHA_MASK) |
+ vc4_hvs6_get_alpha_mask_mode(state) |
(vc4_state->is_unity ? SCALER6_CTL0_UNITY : 0) |
VC4_SET_FIELD(format->pixel_order_hvs5, SCALER6_CTL0_ORDERRGBA) |
VC4_SET_FIELD(scl1, SCALER6_CTL0_SCL1_MODE) |
#define SCALER6_CTL0_ADDR_MODE_UIF 4
#define SCALER6_CTL0_ALPHA_MASK_MASK VC4_MASK(19, 18)
+#define SCALER6_CTL0_ALPHA_MASK_NONE 0
+#define SCALER6_CTL0_ALPHA_MASK_FIXED 3
+
#define SCALER6_CTL0_UNITY BIT(15)
#define SCALER6_CTL0_ORDERRGBA_MASK VC4_MASK(14, 13)
#define SCALER6_CTL0_SCL1_MODE_MASK VC4_MASK(10, 8)