[Patch AArch64] Restrict 16-bit sqrdml{sa}h instructions to FP_LO_REGS

gcc/

	* config/aarch64/aarch64.md
	(arch64_sqrdml<SQRDMLH_AS:rdma_as>h_lane<mode>): Fix register
	constraints for	operand 3.
	(aarch64_sqrdml<SQRDMLH_AS:rdma_as>h_laneq<mode>): Likewise.

From-SVN: r233460

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 0fcc1ee..90d91a7 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,10 @@
+2016-02-16  James Greenhalgh  <james.greenhalgh@arm.com>
+
+       * config/aarch64/aarch64.md
+       (arch64_sqrdml<SQRDMLH_AS:rdma_as>h_lane<mode>): Fix register
+       constraints for operand 3.
+       (aarch64_sqrdml<SQRDMLH_AS:rdma_as>h_laneq<mode>): Likewise.
+
 2016-02-16  Jakub Jelinek  <jakub@redhat.com>
            Richard Biener  <rguenther@suse.de>
 

diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
index 3047841..d8497ab 100644 (file)
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -3240,7 +3240,7 @@
          [(match_operand:VDQHS 1 "register_operand" "0")
           (match_operand:VDQHS 2 "register_operand" "w")
           (vec_select:<VEL>
-            (match_operand:<VCOND> 3 "register_operand" "w")
+            (match_operand:<VCOND> 3 "register_operand" "<vwx>")
             (parallel [(match_operand:SI 4 "immediate_operand" "i")]))]
          SQRDMLH_AS))]
    "TARGET_SIMD_RDMA"
@@ -3258,7 +3258,7 @@
          [(match_operand:SD_HSI 1 "register_operand" "0")
           (match_operand:SD_HSI 2 "register_operand" "w")
           (vec_select:<VEL>
-            (match_operand:<VCOND> 3 "register_operand" "w")
+            (match_operand:<VCOND> 3 "register_operand" "<vwx>")
             (parallel [(match_operand:SI 4 "immediate_operand" "i")]))]
          SQRDMLH_AS))]
    "TARGET_SIMD_RDMA"
@@ -3278,7 +3278,7 @@
          [(match_operand:VDQHS 1 "register_operand" "0")
           (match_operand:VDQHS 2 "register_operand" "w")
           (vec_select:<VEL>
-            (match_operand:<VCONQ> 3 "register_operand" "w")
+            (match_operand:<VCONQ> 3 "register_operand" "<vwx>")
             (parallel [(match_operand:SI 4 "immediate_operand" "i")]))]
          SQRDMLH_AS))]
    "TARGET_SIMD_RDMA"
@@ -3296,7 +3296,7 @@
          [(match_operand:SD_HSI 1 "register_operand" "0")
           (match_operand:SD_HSI 2 "register_operand" "w")
           (vec_select:<VEL>
-            (match_operand:<VCONQ> 3 "register_operand" "w")
+            (match_operand:<VCONQ> 3 "register_operand" "<vwx>")
             (parallel [(match_operand:SI 4 "immediate_operand" "i")]))]
          SQRDMLH_AS))]
    "TARGET_SIMD_RDMA"