chip_rev = device_handle->info.chip_rev;
chip_id = device_handle->info.chip_external_rev;
+ if (family_id >= AMDGPU_FAMILY_RV) {
+ printf("\n\nThe ASIC NOT support UVD, all sub-tests will pass\n");
+ return CUE_SUCCESS;
+ }
+
r = amdgpu_cs_ctx_create(device_handle, &context_handle);
if (r)
return CUE_SINIT_FAILED;
{
int r;
+ if (family_id >= AMDGPU_FAMILY_RV)
+ return CUE_SUCCESS;
+
r = amdgpu_bo_unmap_and_free(ib_handle, ib_va_handle,
ib_mc_address, IB_SIZE);
if (r)
void *msg;
int i, r;
+ if (family_id >= AMDGPU_FAMILY_RV)
+ return;
+
req.alloc_size = 4*1024;
req.preferred_heap = AMDGPU_GEM_DOMAIN_GTT;
uint8_t *ptr;
int i, r;
+ if (family_id >= AMDGPU_FAMILY_RV)
+ return;
+
req.alloc_size = 4*1024; /* msg */
req.alloc_size += 4*1024; /* fb */
if (family_id >= AMDGPU_FAMILY_VI)
void *msg;
int i, r;
+ if (family_id >= AMDGPU_FAMILY_RV)
+ return;
+
req.alloc_size = 4*1024;
req.preferred_heap = AMDGPU_GEM_DOMAIN_GTT;