/*
* All cluster mode values are not applicable on all SoCs. The following
* are the modes supported on various SoCs:
- * Split mode : AM65x, J721E, J7200 and AM64x SoCs
- * LockStep mode : AM65x, J721E and J7200 SoCs
- * Single-CPU mode : AM64x SoCs only
+ * Split mode : AM65x, J721E, J7200 and AM64x SoCs
+ * LockStep mode : AM65x, J721E and J7200 SoCs
+ * Single-CPU mode : AM64x SoCs only
+ * Single-Core mode : AM62x, AM62A SoCs
*/
enum cluster_mode {
CLUSTER_MODE_SPLIT = 0,
CLUSTER_MODE_LOCKSTEP,
CLUSTER_MODE_SINGLECPU,
+ CLUSTER_MODE_SINGLECORE
};
/**
* @tcm_is_double: flag to denote the larger unified TCMs in certain modes
* @tcm_ecc_autoinit: flag to denote the auto-initialization of TCMs for ECC
* @single_cpu_mode: flag to denote if SoC/IP supports Single-CPU mode
+ * @is_single_core: flag to denote if SoC/IP has only single core R5
*/
struct k3_r5_soc_data {
bool tcm_is_double;
bool tcm_ecc_autoinit;
bool single_cpu_mode;
+ bool is_single_core;
};
/**
core0 = list_first_entry(&cluster->cores, struct k3_r5_core, elem);
if (cluster->mode == CLUSTER_MODE_LOCKSTEP ||
- cluster->mode == CLUSTER_MODE_SINGLECPU) {
+ cluster->mode == CLUSTER_MODE_SINGLECPU ||
+ cluster->mode == CLUSTER_MODE_SINGLECORE) {
core = core0;
} else {
core = kproc->core;
* with the bit configured, so program it only on
* permitted cores
*/
- if (cluster->mode == CLUSTER_MODE_SINGLECPU) {
+ if (cluster->mode == CLUSTER_MODE_SINGLECPU ||
+ cluster->mode == CLUSTER_MODE_SINGLECORE) {
set_cfg = PROC_BOOT_CFG_FLAG_R5_SINGLE_CORE;
} else {
/*
if (cluster->mode == CLUSTER_MODE_LOCKSTEP ||
cluster->mode == CLUSTER_MODE_SINGLECPU ||
+ cluster->mode == CLUSTER_MODE_SINGLECORE ||
!cluster->soc_data->tcm_is_double)
return;
single_cpu = cfg & PROC_BOOT_CFG_FLAG_R5_SINGLE_CORE ? 1 : 0;
lockstep_en = cfg & PROC_BOOT_CFG_FLAG_R5_LOCKSTEP ? 1 : 0;
- if (single_cpu)
+ if (single_cpu && mode != CLUSTER_MODE_SINGLECORE)
mode = CLUSTER_MODE_SINGLECPU;
if (lockstep_en)
mode = CLUSTER_MODE_LOCKSTEP;
goto err_add;
}
- /* create only one rproc in lockstep mode or single-cpu mode */
+ /* create only one rproc in lockstep, single-cpu or
+ * single core mode
+ */
if (cluster->mode == CLUSTER_MODE_LOCKSTEP ||
- cluster->mode == CLUSTER_MODE_SINGLECPU)
+ cluster->mode == CLUSTER_MODE_SINGLECPU ||
+ cluster->mode == CLUSTER_MODE_SINGLECORE)
break;
}
/*
* default to most common efuse configurations - Split-mode on AM64x
* and LockStep-mode on all others
+ * default to most common efuse configurations -
+ * Split-mode on AM64x
+ * Single core on AM62x
+ * LockStep-mode on all others
*/
- cluster->mode = data->single_cpu_mode ?
+ if (!data->is_single_core)
+ cluster->mode = data->single_cpu_mode ?
CLUSTER_MODE_SPLIT : CLUSTER_MODE_LOCKSTEP;
+ else
+ cluster->mode = CLUSTER_MODE_SINGLECORE;
}
- if (cluster->mode == CLUSTER_MODE_SINGLECPU && !data->single_cpu_mode) {
+ if ((cluster->mode == CLUSTER_MODE_SINGLECPU && !data->single_cpu_mode) ||
+ (cluster->mode == CLUSTER_MODE_SINGLECORE && !data->is_single_core)) {
dev_err(dev, "Cluster mode = %d is not supported on this SoC\n", cluster->mode);
return -EINVAL;
}
num_cores = of_get_available_child_count(np);
- if (num_cores != 2) {
- dev_err(dev, "MCU cluster requires both R5F cores to be enabled, num_cores = %d\n",
+ if (num_cores != 2 && !data->is_single_core) {
+ dev_err(dev, "MCU cluster requires both R5F cores to be enabled but num_cores is set to = %d\n",
+ num_cores);
+ return -ENODEV;
+ }
+
+ if (num_cores != 1 && data->is_single_core) {
+ dev_err(dev, "SoC supports only single core R5 but num_cores is set to %d\n",
num_cores);
return -ENODEV;
}
.tcm_is_double = false,
.tcm_ecc_autoinit = false,
.single_cpu_mode = false,
+ .is_single_core = false,
};
static const struct k3_r5_soc_data j7200_j721s2_soc_data = {
.tcm_is_double = true,
.tcm_ecc_autoinit = true,
.single_cpu_mode = false,
+ .is_single_core = false,
};
static const struct k3_r5_soc_data am64_soc_data = {
.tcm_is_double = true,
.tcm_ecc_autoinit = true,
.single_cpu_mode = true,
+ .is_single_core = false,
+};
+
+static const struct k3_r5_soc_data am62_soc_data = {
+ .tcm_is_double = false,
+ .tcm_ecc_autoinit = true,
+ .single_cpu_mode = false,
+ .is_single_core = true,
};
static const struct of_device_id k3_r5_of_match[] = {
{ .compatible = "ti,j721e-r5fss", .data = &am65_j721e_soc_data, },
{ .compatible = "ti,j7200-r5fss", .data = &j7200_j721s2_soc_data, },
{ .compatible = "ti,am64-r5fss", .data = &am64_soc_data, },
+ { .compatible = "ti,am62-r5fss", .data = &am62_soc_data, },
{ .compatible = "ti,j721s2-r5fss", .data = &j7200_j721s2_soc_data, },
{ /* sentinel */ },
};