wifi: rtlwifi: Convert LNKCTL change to PCIe cap RMW accessors

commit 5894d0089cbc146063dcc0239a78ede0a8142efb upstream.

The rtlwifi driver comes with custom code to write into PCIe Link
Control register. RMW access for the Link Control register requires
locking that is already provided by the standard PCIe capability
accessors.

Convert the custom RMW code writing into LNKCTL register to standard
RMW capability accessors. The accesses are changed to cover the full
LNKCTL register instead of touching just a single byte of the register.

Fixes: 0c8173385e54 ("rtl8192ce: Add new driver")
Cc: stable@vger.kernel.org
Signed-off-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
Signed-off-by: Kalle Valo <kvalo@kernel.org>
Link: https://lore.kernel.org/r/20231124084725.12738-3-ilpo.jarvinen@linux.intel.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/drivers/net/wireless/realtek/rtlwifi/pci.c b/drivers/net/wireless/realtek/rtlwifi/pci.c
index 206eca3..b118df0 100644 (file)
--- a/drivers/net/wireless/realtek/rtlwifi/pci.c
+++ b/drivers/net/wireless/realtek/rtlwifi/pci.c
@@ -164,21 +164,29 @@ static bool _rtl_pci_platform_switch_device_pci_aspm(
        struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
        struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 
+       value &= PCI_EXP_LNKCTL_ASPMC;
+
        if (rtlhal->hw_type != HARDWARE_TYPE_RTL8192SE)
-               value |= 0x40;
+               value |= PCI_EXP_LNKCTL_CCC;
 
-       pci_write_config_byte(rtlpci->pdev, 0x80, value);
+       pcie_capability_clear_and_set_word(rtlpci->pdev, PCI_EXP_LNKCTL,
+                                          PCI_EXP_LNKCTL_ASPMC | value,
+                                          value);
 
        return false;
 }
 
-/*When we set 0x01 to enable clk request. Set 0x0 to disable clk req.*/
-static void _rtl_pci_switch_clk_req(struct ieee80211_hw *hw, u8 value)
+/* @value is PCI_EXP_LNKCTL_CLKREQ_EN or 0 to enable/disable clk request. */
+static void _rtl_pci_switch_clk_req(struct ieee80211_hw *hw, u16 value)
 {
        struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
        struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 
-       pci_write_config_byte(rtlpci->pdev, 0x81, value);
+       value &= PCI_EXP_LNKCTL_CLKREQ_EN;
+
+       pcie_capability_clear_and_set_word(rtlpci->pdev, PCI_EXP_LNKCTL,
+                                          PCI_EXP_LNKCTL_CLKREQ_EN,
+                                          value);
 
        if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE)
                udelay(100);
@@ -259,7 +267,8 @@ static void rtl_pci_enable_aspm(struct ieee80211_hw *hw)
 
        if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) {
                _rtl_pci_switch_clk_req(hw, (ppsc->reg_rfps_level &
-                                            RT_RF_OFF_LEVL_CLK_REQ) ? 1 : 0);
+                                            RT_RF_OFF_LEVL_CLK_REQ) ?
+                                            PCI_EXP_LNKCTL_CLKREQ_EN : 0);
                RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_CLK_REQ);
        }
        udelay(100);