rockchip: timer: add OF_PLATDATA support for dw-apb-timer

The Rockchip rk3066 SoC has 3 dw-apb-timer nodes.
U-boot is compiled with OF_PLATDATA TPL/SPL options,
so add OF_PLATDATA support for the dw-apb-timer.
Also change driver name to be able to compile with
U-boot scripts. No reset OF_PLATDATA support was added,
because the rk3066 nodes don't need/have them.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

diff --git a/drivers/timer/dw-apb-timer.c b/drivers/timer/dw-apb-timer.c
index 9aed5dd..f722697 100644 (file)
--- a/drivers/timer/dw-apb-timer.c
+++ b/drivers/timer/dw-apb-timer.c
@@ -8,10 +8,12 @@
 #include <common.h>
 #include <dm.h>
 #include <clk.h>
+#include <dt-structs.h>
 #include <malloc.h>
 #include <reset.h>
 #include <timer.h>
 #include <dm/device_compat.h>
+#include <linux/kconfig.h>
 
 #include <asm/io.h>
 #include <asm/arch/timer.h>
@@ -25,6 +27,12 @@ struct dw_apb_timer_priv {
        struct reset_ctl_bulk resets;
 };
 
+struct dw_apb_timer_plat {
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+       struct dtd_snps_dw_apb_timer dtplat;
+#endif
+};
+
 static u64 dw_apb_timer_get_count(struct udevice *dev)
 {
        struct dw_apb_timer_priv *priv = dev_get_priv(dev);
@@ -43,20 +51,33 @@ static int dw_apb_timer_probe(struct udevice *dev)
        struct dw_apb_timer_priv *priv = dev_get_priv(dev);
        struct clk clk;
        int ret;
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+       struct dw_apb_timer_plat *plat = dev_get_plat(dev);
+       struct dtd_snps_dw_apb_timer *dtplat = &plat->dtplat;
 
-       ret = reset_get_bulk(dev, &priv->resets);
-       if (ret)
-               dev_warn(dev, "Can't get reset: %d\n", ret);
-       else
-               reset_deassert_bulk(&priv->resets);
+       priv->regs = dtplat->reg[0];
 
-       ret = clk_get_by_index(dev, 0, &clk);
-       if (ret)
+       ret = clk_get_by_phandle(dev, &dtplat->clocks[0], &clk);
+       if (ret < 0)
                return ret;
 
-       uc_priv->clock_rate = clk_get_rate(&clk);
+       uc_priv->clock_rate = dtplat->clock_frequency;
+#endif
+       if (CONFIG_IS_ENABLED(OF_REAL)) {
+               ret = reset_get_bulk(dev, &priv->resets);
+               if (ret)
+                       dev_warn(dev, "Can't get reset: %d\n", ret);
+               else
+                       reset_deassert_bulk(&priv->resets);
+
+               ret = clk_get_by_index(dev, 0, &clk);
+               if (ret)
+                       return ret;
 
-       clk_free(&clk);
+               uc_priv->clock_rate = clk_get_rate(&clk);
+
+               clk_free(&clk);
+       }
 
        /* init timer */
        writel(0xffffffff, priv->regs + DW_APB_LOAD_VAL);
@@ -68,9 +89,11 @@ static int dw_apb_timer_probe(struct udevice *dev)
 
 static int dw_apb_timer_of_to_plat(struct udevice *dev)
 {
-       struct dw_apb_timer_priv *priv = dev_get_priv(dev);
+       if (CONFIG_IS_ENABLED(OF_REAL)) {
+               struct dw_apb_timer_priv *priv = dev_get_priv(dev);
 
-       priv->regs = dev_read_addr(dev);
+               priv->regs = dev_read_addr(dev);
+       }
 
        return 0;
 }
@@ -91,8 +114,8 @@ static const struct udevice_id dw_apb_timer_ids[] = {
        {}
 };
 
-U_BOOT_DRIVER(dw_apb_timer) = {
-       .name           = "dw_apb_timer",
+U_BOOT_DRIVER(snps_dw_apb_timer) = {
+       .name           = "snps_dw_apb_timer",
        .id             = UCLASS_TIMER,
        .ops            = &dw_apb_timer_ops,
        .probe          = dw_apb_timer_probe,
@@ -100,4 +123,5 @@ U_BOOT_DRIVER(dw_apb_timer) = {
        .of_to_plat = dw_apb_timer_of_to_plat,
        .remove         = dw_apb_timer_remove,
        .priv_auto      = sizeof(struct dw_apb_timer_priv),
+       .plat_auto      = sizeof(struct dw_apb_timer_plat),
 };