Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
/* masks of "get_unique_index" bits */
uint64_t outputs_written;
uint32_t patch_outputs_written;
- uint32_t ps_colors_written;
};
/* Valid shader configurations:
*/
if (blend && blend->dual_src_blend &&
sctx->ps_shader.cso &&
- (sctx->ps_shader.cso->ps_colors_written & 0x3) != 0x3)
+ (sctx->ps_shader.cso->info.colors_written & 0x3) != 0x3)
mask = 0;
radeon_set_context_reg(cs, R_028238_CB_TARGET_MASK, mask);
}
sel->esgs_itemsize = util_last_bit64(sel->outputs_written) * 16;
break;
- case PIPE_SHADER_FRAGMENT:
- for (i = 0; i < sel->info.num_outputs; i++) {
- unsigned name = sel->info.output_semantic_name[i];
- unsigned index = sel->info.output_semantic_index[i];
-
- if (name == TGSI_SEMANTIC_COLOR)
- sel->ps_colors_written |= 1 << index;
- }
- break;
}
if (sscreen->b.debug_flags & DBG_PRECOMPILE) {