global: Migrate CONFIG_SYS_MPC8* symbols to the CFG_SYS namespace

Migrate all of COFIG_SYS_MPC* to the CFG_SYS namespace.

Signed-off-by: Tom Rini <trini@konsulko.com>

diff --git a/arch/powerpc/cpu/mpc85xx/bsc9132_serdes.c b/arch/powerpc/cpu/mpc85xx/bsc9132_serdes.c
index b972cf3..7921334 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/bsc9132_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/bsc9132_serdes.c
@@ -76,7 +76,7 @@ int is_serdes_configured(enum srds_prtcl prtcl)
 
 void fsl_serdes_init(void)
 {
-       ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+       ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
        u32 pordevsr = in_be32(&gur->pordevsr);
        u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
                                MPC85xx_PORDEVSR_IO_SEL_SHIFT;

diff --git a/arch/powerpc/cpu/mpc85xx/c29x_serdes.c b/arch/powerpc/cpu/mpc85xx/c29x_serdes.c
index 34b58bb..e53dd43 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/c29x_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/c29x_serdes.c
@@ -40,7 +40,7 @@ int is_serdes_configured(enum srds_prtcl device)
 
 void fsl_serdes_init(void)
 {
-       ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+       ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR;
        u32 pordevsr = in_be32(&gur->pordevsr);
        u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
                                MPC85xx_PORDEVSR_IO_SEL_SHIFT;

diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c
index 14d5c56..432d4b1 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/cpu.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu.c
@@ -59,7 +59,7 @@ int checkcpu (void)
 #if defined(CONFIG_DYNAMIC_DDR_CLK_FREQ) || \
        defined(CONFIG_STATIC_DDR_CLK_FREQ) || defined(CONFIG_FSL_CORENET)
        ccsr_gur_t __iomem *gur =
-               (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+               (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR);
 #endif
 
        /*
@@ -124,7 +124,7 @@ int checkcpu (void)
                puts("Unicore software on multiprocessor system!!\n"
                     "To enable mutlticore build define CONFIG_MP\n");
 #endif
-               volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
+               volatile ccsr_pic_t *pic = (void *)(CFG_SYS_MPC8xxx_PIC_ADDR);
                printf("CPU%d:  ", pic->whoami);
        } else {
                puts("CPU:   ");
@@ -319,7 +319,7 @@ int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
        val |= 0x70000000;
        mtspr(DBCR0,val);
 #else
-       volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+       volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
 
        /* Call board-specific preparation for reset */
        board_reset_prepare();
@@ -436,7 +436,7 @@ int dram_init(void)
 
 #if defined(CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN)
        {
-               ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+               ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
                unsigned int x = 10;
                unsigned int i;
 

diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 90f024d..9fb7802 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -302,7 +302,7 @@ static void corenet_tb_init(void)
        volatile ccsr_rcpm_t *rcpm =
                (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
        volatile ccsr_pic_t *pic =
-               (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
+               (void *)(CFG_SYS_MPC8xxx_PIC_ADDR);
        u32 whoami = in_be32(&pic->whoami);
 
        /* Enable the timebase register for this core */
@@ -313,7 +313,7 @@ static void corenet_tb_init(void)
 #ifdef CONFIG_SYS_FSL_ERRATUM_A007212
 void fsl_erratum_a007212_workaround(void)
 {
-       ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+       ccsr_gur_t __iomem *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
        u32 ddr_pll_ratio;
        u32 __iomem *plldgdcr1 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c20);
        u32 __iomem *plldadcr1 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c28);
@@ -379,13 +379,13 @@ ulong cpu_init_f(void)
 {
        extern void m8560_cpm_reset (void);
 #ifdef CONFIG_SYS_DCSRBAR_PHYS
-       ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+       ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
 #endif
 #if defined(CONFIG_NXP_ESBC) && !defined(CONFIG_SYS_RAMBOOT)
        struct law_entry law;
 #endif
 #ifdef CONFIG_ARCH_MPC8548
-       ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
+       ccsr_local_ecm_t *ecm = (void *)(CFG_SYS_MPC85xx_ECM_ADDR);
        uint svr = get_svr();
 
        /*
@@ -455,7 +455,7 @@ int enable_cluster_l2(void)
 {
        int i = 0;
        u32 cluster, svr = get_svr();
-       ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+       ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR);
        struct ccsr_cluster_l2 __iomem *l2cache;
 
        /* only the L2 of first cluster should be enabled as expected on T4080,
@@ -516,7 +516,7 @@ int l2cache_init(void)
 {
        __maybe_unused u32 svr = get_svr();
 #ifdef CONFIG_L2_CACHE
-       ccsr_l2cache_t *l2cache = (void __iomem *)CONFIG_SYS_MPC85xx_L2_ADDR;
+       ccsr_l2cache_t *l2cache = (void __iomem *)CFG_SYS_MPC85xx_L2_ADDR;
 #elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
        struct ccsr_cluster_l2 * l2cache = (void __iomem *)CONFIG_SYS_FSL_CLUSTER_1_L2;
 #endif
@@ -821,7 +821,7 @@ int cpu_init_r(void)
 #ifdef CONFIG_SYS_FSL_USB1_PHY_ENABLE
        {
                struct ccsr_usb_phy __iomem *usb_phy1 =
-                       (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR;
+                       (void *)CFG_SYS_MPC85xx_USB1_PHY_ADDR;
 #ifdef CONFIG_SYS_FSL_ERRATUM_A006261
                if (has_erratum_a006261())
                        fsl_erratum_a006261_workaround(usb_phy1);
@@ -833,7 +833,7 @@ int cpu_init_r(void)
 #ifdef CONFIG_SYS_FSL_USB2_PHY_ENABLE
        {
                struct ccsr_usb_phy __iomem *usb_phy2 =
-                       (void *)CONFIG_SYS_MPC85xx_USB2_PHY_ADDR;
+                       (void *)CFG_SYS_MPC85xx_USB2_PHY_ADDR;
 #ifdef CONFIG_SYS_FSL_ERRATUM_A006261
                if (has_erratum_a006261())
                        fsl_erratum_a006261_workaround(usb_phy2);
@@ -859,7 +859,7 @@ int cpu_init_r(void)
 
 #if defined(CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE)
                struct ccsr_usb_phy __iomem *usb_phy =
-                       (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR;
+                       (void *)CFG_SYS_MPC85xx_USB1_PHY_ADDR;
                setbits_be32(&usb_phy->pllprg[1],
                             CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN |
                             CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN |
@@ -928,11 +928,11 @@ int cpu_init_r(void)
                fsl_sata_reg_t *reg;
 
                /* first SATA controller */
-               reg = (void *)CONFIG_SYS_MPC85xx_SATA1_ADDR;
+               reg = (void *)CFG_SYS_MPC85xx_SATA1_ADDR;
                clrbits_le32(&reg->hcontrol, HCONTROL_ENTERPRISE_EN);
 
                /* second SATA controller */
-               reg = (void *)CONFIG_SYS_MPC85xx_SATA2_ADDR;
+               reg = (void *)CFG_SYS_MPC85xx_SATA2_ADDR;
                clrbits_le32(&reg->hcontrol, HCONTROL_ENTERPRISE_EN);
        }
 #endif

diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c
index e6d3058..18bfa2a 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c
@@ -85,10 +85,10 @@ void cpu_init_early_f(void *fdt)
 {
        u32 mas0, mas1, mas2, mas3, mas7;
 #ifdef CONFIG_SYS_FSL_ERRATUM_P1010_A003549
-       ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+       ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
 #endif
 #ifdef CONFIG_A003399_NOR_WORKAROUND
-       ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
+       ccsr_l2cache_t *l2cache = (void *)CFG_SYS_MPC85xx_L2_ADDR;
        u32  *dst, *src;
        void (*setup_ifc_sram)(void);
        int i;

diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c
index 61d8aa7..811e6d6 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/fdt.c
+++ b/arch/powerpc/cpu/mpc85xx/fdt.c
@@ -222,7 +222,7 @@ static inline void ft_fixup_l2cache_compatible(void *blob, int off)
 /* return size in kilobytes */
 static inline u32 l2cache_size(void)
 {
-       volatile ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
+       volatile ccsr_l2cache_t *l2cache = (void *)CFG_SYS_MPC85xx_L2_ADDR;
        volatile u32 l2siz_field = (l2cache->l2ctl >> 28) & 0x3;
        u32 ver = SVR_SOC_VER(get_svr());
 
@@ -509,7 +509,7 @@ static void ft_fixup_qe_snum(void *blob)
 #if defined(CONFIG_ARCH_P4080)
 static void fdt_fixup_usb(void *fdt)
 {
-       ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+       ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
        u32 rcwsr11 = in_be32(&gur->rcwsr[11]);
        int off;
 
@@ -532,7 +532,7 @@ void fdt_fixup_dma3(void *blob)
 {
        /* the 3rd DMA is not functional if SRIO2 is chosen */
        int nodeoff;
-       ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+       ccsr_gur_t __iomem *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
 
 #define CONFIG_SYS_ELO3_DMA3 (0xffe000000 + 0x102300)
 #if defined(CONFIG_ARCH_T2080)

diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c
index da8e0b6..1a30395 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c
@@ -122,7 +122,7 @@ int is_serdes_configured(enum srds_prtcl device)
 
 int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
 {
-       const ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+       const ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR);
        u32 cfg = in_be32(&gur->rcwsr[4]);
        int i;
 
@@ -193,7 +193,7 @@ int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
 void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift,
                u8 serdes_prtcl_map[SERDES_PRCTL_COUNT])
 {
-       ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+       ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR);
        u32 cfg;
        int lane;
 

diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
index 2b4912b..1d35733 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
@@ -108,7 +108,7 @@ int serdes_get_bank_by_lane(int lane)
 
 int serdes_lane_enabled(int lane)
 {
-       ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+       ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
        serdes_corenet_t *regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
 
        int bank = lanes[lane].bank;
@@ -133,7 +133,7 @@ int serdes_lane_enabled(int lane)
 
 int is_serdes_configured(enum srds_prtcl device)
 {
-       ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+       ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
 
        /* Is serdes enabled at all? */
        if (!(in_be32(&gur->rcwsr[5]) & FSL_CORENET_RCWSR5_SRDS_EN))
@@ -169,7 +169,7 @@ int serdes_get_first_lane(enum srds_prtcl device)
        u32 prtcl;
        const ccsr_gur_t *gur;
 
-       gur = (typeof(gur))CONFIG_SYS_MPC85xx_GUTS_ADDR;
+       gur = (typeof(gur))CFG_SYS_MPC85xx_GUTS_ADDR;
 
        /* Is serdes enabled at all? */
        if (unlikely((in_be32(&gur->rcwsr[5]) & 0x2000) == 0))
@@ -251,7 +251,7 @@ void serdes_reset_rx(enum srds_prtcl device)
        if (unlikely(device == NONE))
                return;
 
-       gur = (typeof(gur))CONFIG_SYS_MPC85xx_GUTS_ADDR;
+       gur = (typeof(gur))CFG_SYS_MPC85xx_GUTS_ADDR;
 
        /* Is serdes enabled at all? */
        if (unlikely((in_be32(&gur->rcwsr[5]) & 0x2000) == 0))
@@ -491,7 +491,7 @@ void soc_serdes_init(void) __attribute__((weak, alias("__soc_serdes_init")));
 
 void fsl_serdes_init(void)
 {
-       ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+       ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
        int cfg;
        serdes_corenet_t *srds_regs;
 #ifdef CONFIG_ARCH_P5040

diff --git a/arch/powerpc/cpu/mpc85xx/interrupts.c b/arch/powerpc/cpu/mpc85xx/interrupts.c
index 4ad7626..bcbdfac 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/interrupts.c
+++ b/arch/powerpc/cpu/mpc85xx/interrupts.c
@@ -25,7 +25,7 @@
 
 void interrupt_init_cpu(unsigned *decrementer_count)
 {
-       ccsr_pic_t __iomem *pic = (void *)CONFIG_SYS_MPC8xxx_PIC_ADDR;
+       ccsr_pic_t __iomem *pic = (void *)CFG_SYS_MPC8xxx_PIC_ADDR;
 
 #ifdef CONFIG_POST
        /*

diff --git a/arch/powerpc/cpu/mpc85xx/mp.c b/arch/powerpc/cpu/mpc85xx/mp.c
index 84eb8b4..e1469eb 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/mp.c
+++ b/arch/powerpc/cpu/mpc85xx/mp.c
@@ -50,7 +50,7 @@ int hold_cores_in_reset(int verbose)
 
 int cpu_reset(u32 nr)
 {
-       volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
+       volatile ccsr_pic_t *pic = (void *)(CFG_SYS_MPC8xxx_PIC_ADDR);
        out_be32(&pic->pir, 1 << nr);
        /* the dummy read works around an errata on early 85xx MP PICs */
        (void)in_be32(&pic->pir);
@@ -87,7 +87,7 @@ int cpu_status(u32 nr)
 #ifdef CONFIG_FSL_CORENET
 int cpu_disable(u32 nr)
 {
-       volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+       volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
 
        setbits_be32(&gur->coredisrl, 1 << nr);
 
@@ -95,7 +95,7 @@ int cpu_disable(u32 nr)
 }
 
 int is_core_disabled(int nr) {
-       ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+       ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
        u32 coredisrl = in_be32(&gur->coredisrl);
 
        return (coredisrl & (1 << nr));
@@ -103,7 +103,7 @@ int is_core_disabled(int nr) {
 #else
 int cpu_disable(u32 nr)
 {
-       volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+       volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
 
        switch (nr) {
        case 0:
@@ -121,7 +121,7 @@ int cpu_disable(u32 nr)
 }
 
 int is_core_disabled(int nr) {
-       ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+       ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
        u32 devdisr = in_be32(&gur->devdisr);
 
        switch (nr) {
@@ -264,10 +264,10 @@ static void plat_mp_up(unsigned long bootpg, unsigned int pagesize)
        u32 mask = cpu_mask();
        struct law_entry e;
 
-       gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+       gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
        ccm = (void *)(CONFIG_SYS_FSL_CORENET_CCM_ADDR);
        rcpm = (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
-       pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
+       pic = (void *)(CFG_SYS_MPC8xxx_PIC_ADDR);
 
        whoami = in_be32(&pic->whoami);
        cpu_up_mask = 1 << whoami;
@@ -336,9 +336,9 @@ static void plat_mp_up(unsigned long bootpg, unsigned int pagesize)
        u32 up, cpu_up_mask, whoami;
        u32 *table = (u32 *)&__spin_table;
        volatile u32 bpcr;
-       volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
-       volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-       volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
+       volatile ccsr_local_ecm_t *ecm = (void *)(CFG_SYS_MPC85xx_ECM_ADDR);
+       volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
+       volatile ccsr_pic_t *pic = (void *)(CFG_SYS_MPC8xxx_PIC_ADDR);
        u32 devdisr;
        int timeout = 10;
 

diff --git a/arch/powerpc/cpu/mpc85xx/mpc8536_serdes.c b/arch/powerpc/cpu/mpc85xx/mpc8536_serdes.c
index 111692f..cbcb57f 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/mpc8536_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/mpc8536_serdes.c
@@ -89,8 +89,8 @@ int is_serdes_configured(enum srds_prtcl device)
 
 void fsl_serdes_init(void)
 {
-       void *guts = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-       void *sd = (void *)CONFIG_SYS_MPC85xx_SERDES2_ADDR;
+       void *guts = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
+       void *sd = (void *)CFG_SYS_MPC85xx_SERDES2_ADDR;
        u32 pordevsr = in_be32(guts + GUTS_PORDEVSR_OFFS);
        u32 srds1_io_sel, srds2_io_sel;
        u32 tmp;

diff --git a/arch/powerpc/cpu/mpc85xx/mpc8544_serdes.c b/arch/powerpc/cpu/mpc85xx/mpc8544_serdes.c
index f3b5450..a48f3c1 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/mpc8544_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/mpc8544_serdes.c
@@ -52,7 +52,7 @@ int is_serdes_configured(enum srds_prtcl device)
 
 void fsl_serdes_init(void)
 {
-       ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+       ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR;
        u32 pordevsr = in_be32(&gur->pordevsr);
        u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
                                MPC85xx_PORDEVSR_IO_SEL_SHIFT;

diff --git a/arch/powerpc/cpu/mpc85xx/mpc8548_serdes.c b/arch/powerpc/cpu/mpc85xx/mpc8548_serdes.c
index 38f30af..479ee08 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/mpc8548_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/mpc8548_serdes.c
@@ -32,7 +32,7 @@ int is_serdes_configured(enum srds_prtcl prtcl)
 
 void fsl_serdes_init(void)
 {
-       ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+       ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
        u32 pordevsr = in_be32(&gur->pordevsr);
        u32 srds1_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
                                MPC85xx_PORDEVSR_IO_SEL_SHIFT;

diff --git a/arch/powerpc/cpu/mpc85xx/p1010_serdes.c b/arch/powerpc/cpu/mpc85xx/p1010_serdes.c
index 8cba422..56e5ef6 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/p1010_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/p1010_serdes.c
@@ -51,7 +51,7 @@ int is_serdes_configured(enum srds_prtcl device)
 
 void fsl_serdes_init(void)
 {
-       ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+       ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR;
        u32 pordevsr = in_be32(&gur->pordevsr);
        u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
                                MPC85xx_PORDEVSR_IO_SEL_SHIFT;

diff --git a/arch/powerpc/cpu/mpc85xx/p1021_serdes.c b/arch/powerpc/cpu/mpc85xx/p1021_serdes.c
index 6b8e447..47f13e3 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/p1021_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/p1021_serdes.c
@@ -50,8 +50,8 @@ int is_serdes_configured(enum srds_prtcl prtcl)
 
 void fsl_serdes_init(void)
 {
-       ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-       serdes_85xx_t *serdes = (void *)CONFIG_SYS_MPC85xx_SERDES1_ADDR;
+       ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
+       serdes_85xx_t *serdes = (void *)CFG_SYS_MPC85xx_SERDES1_ADDR;
 
        u32 pordevsr = in_be32(&gur->pordevsr);
        u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>

diff --git a/arch/powerpc/cpu/mpc85xx/p1023_serdes.c b/arch/powerpc/cpu/mpc85xx/p1023_serdes.c
index bf5cac6..7a8f653 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/p1023_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/p1023_serdes.c
@@ -35,7 +35,7 @@ int is_serdes_configured(enum srds_prtcl device)
 
 void fsl_serdes_init(void)
 {
-       ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+       ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR;
        u32 pordevsr = in_be32(&gur->pordevsr);
        u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
                                MPC85xx_PORDEVSR_IO_SEL_SHIFT;

diff --git a/arch/powerpc/cpu/mpc85xx/p2020_serdes.c b/arch/powerpc/cpu/mpc85xx/p2020_serdes.c
index f36b1b6..8c5d82a 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/p2020_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/p2020_serdes.c
@@ -40,7 +40,7 @@ int is_serdes_configured(enum srds_prtcl prtcl)
 
 void fsl_serdes_init(void)
 {
-       ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+       ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
        u32 pordevsr = in_be32(&gur->pordevsr);
        u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
                                MPC85xx_PORDEVSR_IO_SEL_SHIFT;

diff --git a/arch/powerpc/cpu/mpc85xx/qe_io.c b/arch/powerpc/cpu/mpc85xx/qe_io.c
index c5b1443..3cf41ca 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/qe_io.c
+++ b/arch/powerpc/cpu/mpc85xx/qe_io.c
@@ -20,7 +20,7 @@ void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign)
        u32                     pin_2bit_assign;
        u32                     pin_1bit_mask;
        u32                     tmp_val;
-       volatile ccsr_gur_t     *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+       volatile ccsr_gur_t     *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
        volatile par_io_t       *par_io = (volatile par_io_t *)
                                                &(gur->qe_par_io);
 

diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c
index 6686b7c..a7004a6 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/speed.c
+++ b/arch/powerpc/cpu/mpc85xx/speed.c
@@ -24,7 +24,7 @@ DECLARE_GLOBAL_DATA_PTR;
 
 void get_sys_info(sys_info_t *sys_info)
 {
-       volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+       volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
 #ifdef CONFIG_FSL_CORENET
        volatile ccsr_clk_t *clk = (void *)(CONFIG_SYS_FSL_CORENET_CLK_ADDR);
        unsigned int cpu;
@@ -575,7 +575,7 @@ int get_clocks(void)
 {
        sys_info_t sys_info;
 #ifdef CONFIG_ARCH_MPC8544
-       volatile ccsr_gur_t *gur = (void *) CONFIG_SYS_MPC85xx_GUTS_ADDR;
+       volatile ccsr_gur_t *gur = (void *) CFG_SYS_MPC85xx_GUTS_ADDR;
 #endif
        get_sys_info (&sys_info);
        gd->cpu_clk = sys_info.freq_processor[0];

diff --git a/arch/powerpc/cpu/mpc85xx/spl_minimal.c b/arch/powerpc/cpu/mpc85xx/spl_minimal.c
index bdd7338..47df3c2 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/spl_minimal.c
+++ b/arch/powerpc/cpu/mpc85xx/spl_minimal.c
@@ -15,7 +15,7 @@ DECLARE_GLOBAL_DATA_PTR;
 ulong cpu_init_f(void)
 {
 #ifdef CONFIG_SYS_INIT_L2_ADDR
-       ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
+       ccsr_l2cache_t *l2cache = (void *)CFG_SYS_MPC85xx_L2_ADDR;
 
        out_be32(&l2cache->l2srbar0, CONFIG_SYS_INIT_L2_ADDR);
 

diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S
index 9d44fa4..024414e 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/start.S
+++ b/arch/powerpc/cpu/mpc85xx/start.S
@@ -80,7 +80,7 @@
 
 /* Definitions from C header file asm/immap_85xx.h */
 
-#define CONFIG_SYS_MPC85xx_L2_OFFSET           0x20000
+#define CFG_SYS_MPC85xx_L2_OFFSET              0x20000
 
 #define MPC85xx_L2CTL                          0x000
 #define MPC85xx_L2CTL_L2E                      0x80000000
@@ -127,13 +127,13 @@ bootsect:
        .org 0x80 /* Start of configuration */
        .Lconf_pair_start:
 
-       .long CONFIG_SYS_CCSRBAR_DEFAULT + CONFIG_SYS_MPC85xx_L2_OFFSET + MPC85xx_L2SRBAR0 /* Address: L2 memory-mapped SRAM base addr 0 */
+       .long CONFIG_SYS_CCSRBAR_DEFAULT + CFG_SYS_MPC85xx_L2_OFFSET + MPC85xx_L2SRBAR0 /* Address: L2 memory-mapped SRAM base addr 0 */
        .long CONFIG_SYS_INIT_L2_ADDR
 
-       .long CONFIG_SYS_CCSRBAR_DEFAULT + CONFIG_SYS_MPC85xx_L2_OFFSET + MPC85xx_L2ERRDIS /* Address: L2 cache error disable */
+       .long CONFIG_SYS_CCSRBAR_DEFAULT + CFG_SYS_MPC85xx_L2_OFFSET + MPC85xx_L2ERRDIS /* Address: L2 cache error disable */
        .long MPC85xx_L2ERRDIS_MBECC | MPC85xx_L2ERRDIS_SBECC
 
-       .long CONFIG_SYS_CCSRBAR_DEFAULT + CONFIG_SYS_MPC85xx_L2_OFFSET + MPC85xx_L2CTL /* Address: L2 configuration 0 */
+       .long CONFIG_SYS_CCSRBAR_DEFAULT + CFG_SYS_MPC85xx_L2_OFFSET + MPC85xx_L2CTL /* Address: L2 configuration 0 */
        .long MPC85xx_L2CTL_L2E | MPC85xx_L2CTL_L2SRAM_ENTIRE
 
        .long CONFIG_SYS_CCSRBAR_DEFAULT + ESDHCCTL /* Address: eSDHC DMA control */

diff --git a/arch/powerpc/cpu/mpc85xx/traps.c b/arch/powerpc/cpu/mpc85xx/traps.c
index 97ed24a..8f451b4 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/traps.c
+++ b/arch/powerpc/cpu/mpc85xx/traps.c
@@ -260,7 +260,7 @@ void UnknownException(struct pt_regs *regs)
 
 void ExtIntException(struct pt_regs *regs)
 {
-       volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
+       volatile ccsr_pic_t *pic = (void *)(CFG_SYS_MPC8xxx_PIC_ADDR);
 
        uint vect;
 

diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c b/arch/powerpc/cpu/mpc8xxx/cpu.c
index 0985fb2..7f20190 100644 (file)
--- a/arch/powerpc/cpu/mpc8xxx/cpu.c
+++ b/arch/powerpc/cpu/mpc8xxx/cpu.c
@@ -104,7 +104,7 @@ static struct cpu_type cpu_type_list[] = {
 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
 static inline u32 init_type(u32 cluster, int init_id)
 {
-       ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+       ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR);
        u32 idx = (cluster >> (init_id * 8)) & TP_CLUSTER_INIT_MASK;
        u32 type = in_be32(&gur->tp_ityp[idx]);
 
@@ -116,7 +116,7 @@ static inline u32 init_type(u32 cluster, int init_id)
 
 u32 compute_ppc_cpumask(void)
 {
-       ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+       ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR);
        int i = 0, count = 0;
        u32 cluster, type, mask = 0;
 
@@ -140,7 +140,7 @@ u32 compute_ppc_cpumask(void)
 #ifdef CONFIG_HETROGENOUS_CLUSTERS
 u32 compute_dsp_cpumask(void)
 {
-       ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+       ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR);
        int i = CONFIG_DSP_CLUSTER_START, count = 0;
        u32 cluster, type, dsp_mask = 0;
 
@@ -163,7 +163,7 @@ u32 compute_dsp_cpumask(void)
 
 int fsl_qoriq_dsp_core_to_cluster(unsigned int core)
 {
-       ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+       ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR);
        int count = 0, i = CONFIG_DSP_CLUSTER_START;
        u32 cluster;
 
@@ -186,7 +186,7 @@ int fsl_qoriq_dsp_core_to_cluster(unsigned int core)
 
 int fsl_qoriq_core_to_cluster(unsigned int core)
 {
-       ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+       ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR);
        int i = 0, count = 0;
        u32 cluster;
 
@@ -235,7 +235,7 @@ struct cpu_type *identify_cpu(u32 ver)
  */
 __weak u32 cpu_mask(void)
 {
-       ccsr_pic_t __iomem *pic = (void *)CONFIG_SYS_MPC8xxx_PIC_ADDR;
+       ccsr_pic_t __iomem *pic = (void *)CFG_SYS_MPC8xxx_PIC_ADDR;
        struct cpu_type *cpu = gd->arch.cpu;
 
        /* better to query feature reporting register than just assume 1 */
@@ -252,7 +252,7 @@ __weak u32 cpu_mask(void)
 #ifdef CONFIG_HETROGENOUS_CLUSTERS
 __weak u32 cpu_dsp_mask(void)
 {
-       ccsr_pic_t __iomem *pic = (void *)CONFIG_SYS_MPC8xxx_PIC_ADDR;
+       ccsr_pic_t __iomem *pic = (void *)CFG_SYS_MPC8xxx_PIC_ADDR;
        struct cpu_type *cpu = gd->arch.cpu;
 
        /* better to query feature reporting register than just assume 1 */

diff --git a/arch/powerpc/cpu/mpc8xxx/law.c b/arch/powerpc/cpu/mpc8xxx/law.c
index 24bbe3b..4e3f900 100644 (file)
--- a/arch/powerpc/cpu/mpc8xxx/law.c
+++ b/arch/powerpc/cpu/mpc8xxx/law.c
@@ -301,7 +301,7 @@ void init_laws(void)
 
 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
        /* check RCW to get which port is used for boot */
-       ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+       ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR;
        u32 bootloc = in_be32(&gur->rcwsr[6]);
        /*
         * in SRIO or PCIE boot we need to set specail LAWs for

diff --git a/arch/powerpc/cpu/mpc8xxx/srio.c b/arch/powerpc/cpu/mpc8xxx/srio.c
index c73cf93..62524a2 100644 (file)
--- a/arch/powerpc/cpu/mpc8xxx/srio.c
+++ b/arch/powerpc/cpu/mpc8xxx/srio.c
@@ -33,12 +33,12 @@
        #define _DEVDISR_SRIO2 FSL_CORENET_DEVDISR_SRIO2
 #endif
        #define _DEVDISR_RMU   FSL_CORENET_DEVDISR_RMU
-       #define CONFIG_SYS_MPC8xxx_GUTS_ADDR CONFIG_SYS_MPC85xx_GUTS_ADDR
+       #define CONFIG_SYS_MPC8xxx_GUTS_ADDR CFG_SYS_MPC85xx_GUTS_ADDR
 #elif defined(CONFIG_MPC85xx)
        #define _DEVDISR_SRIO1 MPC85xx_DEVDISR_SRIO
        #define _DEVDISR_SRIO2 MPC85xx_DEVDISR_SRIO
        #define _DEVDISR_RMU   MPC85xx_DEVDISR_RMSG
-       #define CONFIG_SYS_MPC8xxx_GUTS_ADDR CONFIG_SYS_MPC85xx_GUTS_ADDR
+       #define CONFIG_SYS_MPC8xxx_GUTS_ADDR CFG_SYS_MPC85xx_GUTS_ADDR
 #elif defined(CONFIG_MPC86xx)
        #define _DEVDISR_SRIO1 MPC86xx_DEVDISR_SRIO
        #define _DEVDISR_SRIO2 MPC86xx_DEVDISR_SRIO

diff --git a/arch/powerpc/include/asm/fsl_liodn.h b/arch/powerpc/include/asm/fsl_liodn.h
index 7ced50c..be55f99 100644 (file)
--- a/arch/powerpc/include/asm/fsl_liodn.h
+++ b/arch/powerpc/include/asm/fsl_liodn.h
@@ -18,15 +18,15 @@ struct srio_liodn_id_table {
 #define SET_SRIO_LIODN_1(port, idA) \
        { .id = { idA }, .num_ids = 1, .portid = port, \
          .reg_offset[0] = offsetof(ccsr_gur_t, rio##port##liodnr) \
-               + CONFIG_SYS_MPC85xx_GUTS_OFFSET + CONFIG_SYS_CCSRBAR, \
+               + CFG_SYS_MPC85xx_GUTS_OFFSET + CONFIG_SYS_CCSRBAR, \
        }
 
 #define SET_SRIO_LIODN_2(port, idA, idB) \
        { .id = { idA, idB }, .num_ids = 2, .portid = port, \
          .reg_offset[0] = offsetof(ccsr_gur_t, rio##port##liodnr) \
-               + CONFIG_SYS_MPC85xx_GUTS_OFFSET + CONFIG_SYS_CCSRBAR, \
+               + CFG_SYS_MPC85xx_GUTS_OFFSET + CONFIG_SYS_CCSRBAR, \
          .reg_offset[1] = offsetof(ccsr_gur_t, rio##port##maintliodnr) \
-               + CONFIG_SYS_MPC85xx_GUTS_OFFSET + CONFIG_SYS_CCSRBAR, \
+               + CFG_SYS_MPC85xx_GUTS_OFFSET + CONFIG_SYS_CCSRBAR, \
        }
 
 #define SET_SRIO_LIODN_BASE(port, id_a) \
@@ -90,42 +90,42 @@ extern void fdt_fixup_liodn(void *blob);
 
 #define SET_GUTS_LIODN(compat, liodn, name, compatoff) \
        SET_LIODN_ENTRY_1(compat, liodn, \
-               offsetof(ccsr_gur_t, name) + CONFIG_SYS_MPC85xx_GUTS_OFFSET, \
+               offsetof(ccsr_gur_t, name) + CFG_SYS_MPC85xx_GUTS_OFFSET, \
                compatoff)
 
 #define SET_USB_LIODN(usbNum, compat, liodn) \
        SET_GUTS_LIODN(compat, liodn, usb##usbNum##liodnr,\
-               CONFIG_SYS_MPC85xx_USB##usbNum##_OFFSET)
+               CFG_SYS_MPC85xx_USB##usbNum##_OFFSET)
 
 #define SET_SATA_LIODN(sataNum, liodn) \
        SET_GUTS_LIODN("fsl,pq-sata-v2", liodn, sata##sataNum##liodnr,\
-               CONFIG_SYS_MPC85xx_SATA##sataNum##_OFFSET)
+               CFG_SYS_MPC85xx_SATA##sataNum##_OFFSET)
 
 #define SET_PCI_LIODN(compat, pciNum, liodn) \
        SET_GUTS_LIODN(compat, liodn, pex##pciNum##liodnr,\
-               CONFIG_SYS_MPC85xx_PCIE##pciNum##_OFFSET)
+               CFG_SYS_MPC85xx_PCIE##pciNum##_OFFSET)
 
 #define SET_PCI_LIODN_BASE(compat, pciNum, liodn) \
        SET_LIODN_ENTRY_1(compat, liodn,\
-               offsetof(ccsr_pcix_t, liodn_base) + CONFIG_SYS_MPC85xx_PCIE##pciNum##_OFFSET,\
-               CONFIG_SYS_MPC85xx_PCIE##pciNum##_OFFSET)
+               offsetof(ccsr_pcix_t, liodn_base) + CFG_SYS_MPC85xx_PCIE##pciNum##_OFFSET,\
+               CFG_SYS_MPC85xx_PCIE##pciNum##_OFFSET)
 
 /* reg nodes for DMA start @ 0x300 */
 #define SET_DMA_LIODN(dmaNum, compat, liodn) \
        SET_GUTS_LIODN(compat, liodn, dma##dmaNum##liodnr,\
-               CONFIG_SYS_MPC85xx_DMA##dmaNum##_OFFSET + 0x300)
+               CFG_SYS_MPC85xx_DMA##dmaNum##_OFFSET + 0x300)
 
 #define SET_SDHC_LIODN(sdhcNum, liodn) \
        SET_GUTS_LIODN("fsl,esdhc", liodn, sdmmc##sdhcNum##liodnr,\
-               CONFIG_SYS_MPC85xx_ESDHC_OFFSET)
+               CFG_SYS_MPC85xx_ESDHC_OFFSET)
 
 #define SET_QE_LIODN(liodn) \
        SET_GUTS_LIODN("fsl,qe", liodn, qeliodnr,\
-               CONFIG_SYS_MPC85xx_QE_OFFSET)
+               CFG_SYS_MPC85xx_QE_OFFSET)
 
 #define SET_TDM_LIODN(liodn) \
        SET_GUTS_LIODN("fsl,tdm1.0", liodn, tdmliodnr,\
-               CONFIG_SYS_MPC85xx_TDM_OFFSET)
+               CFG_SYS_MPC85xx_TDM_OFFSET)
 
 #define SET_QMAN_LIODN(liodn) \
        SET_LIODN_ENTRY_1("fsl,qman", liodn, \

diff --git a/arch/powerpc/include/asm/immap_83xx.h b/arch/powerpc/include/asm/immap_83xx.h
index c731347..0bf5b9c 100644 (file)
--- a/arch/powerpc/include/asm/immap_83xx.h
+++ b/arch/powerpc/include/asm/immap_83xx.h
@@ -861,15 +861,15 @@ struct ccsr_gpio {
        };
 };
 
-#define CONFIG_SYS_MPC8xxx_DDR_OFFSET  (0x2000)
+#define CFG_SYS_MPC8xxx_DDR_OFFSET     (0x2000)
 #define CONFIG_SYS_FSL_DDR_ADDR \
-                       (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR_OFFSET)
-#define CONFIG_SYS_MPC83xx_DMA_OFFSET  (0x8000)
-#define CONFIG_SYS_MPC83xx_DMA_ADDR \
-                       (CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_DMA_OFFSET)
-#define CONFIG_SYS_MPC83xx_ESDHC_OFFSET        (0x2e000)
-#define CONFIG_SYS_MPC83xx_ESDHC_ADDR \
-                       (CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_ESDHC_OFFSET)
+                       (CONFIG_SYS_IMMR + CFG_SYS_MPC8xxx_DDR_OFFSET)
+#define CFG_SYS_MPC83xx_DMA_OFFSET     (0x8000)
+#define CFG_SYS_MPC83xx_DMA_ADDR \
+                       (CONFIG_SYS_IMMR + CFG_SYS_MPC83xx_DMA_OFFSET)
+#define CFG_SYS_MPC83xx_ESDHC_OFFSET   (0x2e000)
+#define CFG_SYS_MPC83xx_ESDHC_ADDR \
+                       (CONFIG_SYS_IMMR + CFG_SYS_MPC83xx_ESDHC_OFFSET)
 
 #define CONFIG_SYS_LBC_ADDR (&((immap_t *)CONFIG_SYS_IMMR)->im_lbc)
 

diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index 7e88779..7a7a7f2 100644 (file)
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -2437,9 +2437,9 @@ struct ccsr_pman {
 #define CONFIG_SYS_FSL_CORENET_PMAN2_OFFSET    0x5000
 #define CONFIG_SYS_FSL_CORENET_PMAN3_OFFSET    0x6000
 #endif
-#define CONFIG_SYS_MPC8xxx_DDR_OFFSET          0x8000
-#define CONFIG_SYS_MPC8xxx_DDR2_OFFSET         0x9000
-#define CONFIG_SYS_MPC8xxx_DDR3_OFFSET         0xA000
+#define CFG_SYS_MPC8xxx_DDR_OFFSET             0x8000
+#define CFG_SYS_MPC8xxx_DDR2_OFFSET            0x9000
+#define CFG_SYS_MPC8xxx_DDR3_OFFSET            0xA000
 #define CONFIG_SYS_FSL_CORENET_CLK_OFFSET      0xE1000
 #define CONFIG_SYS_FSL_CORENET_RCPM_OFFSET     0xE2000
 #ifdef CONFIG_SYS_FSL_SFP_VER_3_0
@@ -2457,36 +2457,36 @@ struct ccsr_pman {
 #define CONFIG_SYS_FSL_CPC_OFFSET              0x10000
 #define CONFIG_SYS_FSL_SCFG_OFFSET             0xFC000
 #define CONFIG_SYS_FSL_PAMU_OFFSET             0x20000
-#define CONFIG_SYS_MPC85xx_DMA1_OFFSET         0x100000
-#define CONFIG_SYS_MPC85xx_DMA2_OFFSET         0x101000
-#define CONFIG_SYS_MPC85xx_DMA3_OFFSET         0x102000
-#define CONFIG_SYS_MPC85xx_DMA_OFFSET          CONFIG_SYS_MPC85xx_DMA1_OFFSET
-#define CONFIG_SYS_MPC85xx_ESPI_OFFSET         0x110000
-#define CONFIG_SYS_MPC85xx_ESDHC_OFFSET                0x114000
-#define CONFIG_SYS_MPC85xx_LBC_OFFSET          0x124000
-#define CONFIG_SYS_MPC85xx_IFC_OFFSET          0x124000
-#define CONFIG_SYS_MPC85xx_GPIO_OFFSET         0x130000
-#define CONFIG_SYS_MPC85xx_TDM_OFFSET          0x185000
-#define CONFIG_SYS_MPC85xx_QE_OFFSET           0x140000
+#define CFG_SYS_MPC85xx_DMA1_OFFSET            0x100000
+#define CFG_SYS_MPC85xx_DMA2_OFFSET            0x101000
+#define CFG_SYS_MPC85xx_DMA3_OFFSET            0x102000
+#define CFG_SYS_MPC85xx_DMA_OFFSET             CFG_SYS_MPC85xx_DMA1_OFFSET
+#define CFG_SYS_MPC85xx_ESPI_OFFSET            0x110000
+#define CFG_SYS_MPC85xx_ESDHC_OFFSET           0x114000
+#define CFG_SYS_MPC85xx_LBC_OFFSET             0x124000
+#define CFG_SYS_MPC85xx_IFC_OFFSET             0x124000
+#define CFG_SYS_MPC85xx_GPIO_OFFSET            0x130000
+#define CFG_SYS_MPC85xx_TDM_OFFSET             0x185000
+#define CFG_SYS_MPC85xx_QE_OFFSET              0x140000
 #define CONFIG_SYS_FSL_CORENET_RMAN_OFFSET     0x1e0000
 #if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && !defined(CONFIG_ARCH_B4860) && \
        !defined(CONFIG_ARCH_B4420)
-#define CONFIG_SYS_MPC85xx_PCIE1_OFFSET                0x240000
-#define CONFIG_SYS_MPC85xx_PCIE2_OFFSET                0x250000
-#define CONFIG_SYS_MPC85xx_PCIE3_OFFSET                0x260000
-#define CONFIG_SYS_MPC85xx_PCIE4_OFFSET                0x270000
+#define CFG_SYS_MPC85xx_PCIE1_OFFSET           0x240000
+#define CFG_SYS_MPC85xx_PCIE2_OFFSET           0x250000
+#define CFG_SYS_MPC85xx_PCIE3_OFFSET           0x260000
+#define CFG_SYS_MPC85xx_PCIE4_OFFSET           0x270000
 #else
-#define CONFIG_SYS_MPC85xx_PCIE1_OFFSET                0x200000
-#define CONFIG_SYS_MPC85xx_PCIE2_OFFSET                0x201000
-#define CONFIG_SYS_MPC85xx_PCIE3_OFFSET                0x202000
-#define CONFIG_SYS_MPC85xx_PCIE4_OFFSET                0x203000
+#define CFG_SYS_MPC85xx_PCIE1_OFFSET           0x200000
+#define CFG_SYS_MPC85xx_PCIE2_OFFSET           0x201000
+#define CFG_SYS_MPC85xx_PCIE3_OFFSET           0x202000
+#define CFG_SYS_MPC85xx_PCIE4_OFFSET           0x203000
 #endif
-#define CONFIG_SYS_MPC85xx_USB1_OFFSET         0x210000
-#define CONFIG_SYS_MPC85xx_USB2_OFFSET         0x211000
-#define CONFIG_SYS_MPC85xx_USB1_PHY_OFFSET 0x214000
-#define CONFIG_SYS_MPC85xx_USB2_PHY_OFFSET 0x214100
-#define CONFIG_SYS_MPC85xx_SATA1_OFFSET                0x220000
-#define CONFIG_SYS_MPC85xx_SATA2_OFFSET                0x221000
+#define CFG_SYS_MPC85xx_USB1_OFFSET            0x210000
+#define CFG_SYS_MPC85xx_USB2_OFFSET            0x211000
+#define CFG_SYS_MPC85xx_USB1_PHY_OFFSET 0x214000
+#define CFG_SYS_MPC85xx_USB2_PHY_OFFSET 0x214100
+#define CFG_SYS_MPC85xx_SATA1_OFFSET           0x220000
+#define CFG_SYS_MPC85xx_SATA2_OFFSET           0x221000
 #define CONFIG_SYS_FSL_SEC_OFFSET              0x300000
 #define CONFIG_SYS_FSL_JR0_OFFSET              0x301000
 #define CONFIG_SYS_SEC_MON_OFFSET              0x314000
@@ -2515,32 +2515,32 @@ struct ccsr_pman {
 #define CONFIG_SYS_FSL_FM2_RX1_10G_OFFSET      0x591000
 #define CONFIG_SYS_FSL_CLUSTER_1_L2_OFFSET     0xC20000
 #else
-#define CONFIG_SYS_MPC85xx_ECM_OFFSET          0x0000
-#define CONFIG_SYS_MPC8xxx_DDR_OFFSET          0x2000
-#define CONFIG_SYS_MPC85xx_LBC_OFFSET          0x5000
-#define CONFIG_SYS_MPC8xxx_DDR2_OFFSET         0x6000
-#define CONFIG_SYS_MPC85xx_ESPI_OFFSET         0x7000
-#define CONFIG_SYS_MPC85xx_PCI1_OFFSET         0x8000
-#define CONFIG_SYS_MPC85xx_PCIX_OFFSET         0x8000
-#define CONFIG_SYS_MPC85xx_PCI2_OFFSET         0x9000
-#define CONFIG_SYS_MPC85xx_PCIX2_OFFSET                0x9000
-#define CONFIG_SYS_MPC85xx_PCIE1_OFFSET         0xa000
-#define CONFIG_SYS_MPC85xx_PCIE2_OFFSET         0x9000
+#define CFG_SYS_MPC85xx_ECM_OFFSET             0x0000
+#define CFG_SYS_MPC8xxx_DDR_OFFSET             0x2000
+#define CFG_SYS_MPC85xx_LBC_OFFSET             0x5000
+#define CFG_SYS_MPC8xxx_DDR2_OFFSET            0x6000
+#define CFG_SYS_MPC85xx_ESPI_OFFSET            0x7000
+#define CFG_SYS_MPC85xx_PCI1_OFFSET            0x8000
+#define CFG_SYS_MPC85xx_PCIX_OFFSET            0x8000
+#define CFG_SYS_MPC85xx_PCI2_OFFSET            0x9000
+#define CFG_SYS_MPC85xx_PCIX2_OFFSET           0x9000
+#define CFG_SYS_MPC85xx_PCIE1_OFFSET         0xa000
+#define CFG_SYS_MPC85xx_PCIE2_OFFSET         0x9000
 #if defined(CONFIG_ARCH_P2020)
-#define CONFIG_SYS_MPC85xx_PCIE3_OFFSET         0x8000
+#define CFG_SYS_MPC85xx_PCIE3_OFFSET         0x8000
 #else
-#define CONFIG_SYS_MPC85xx_PCIE3_OFFSET         0xb000
+#define CFG_SYS_MPC85xx_PCIE3_OFFSET         0xb000
 #endif
-#define CONFIG_SYS_MPC85xx_GPIO_OFFSET         0xF000
-#define CONFIG_SYS_MPC85xx_SATA1_OFFSET                0x18000
-#define CONFIG_SYS_MPC85xx_SATA2_OFFSET                0x19000
-#define CONFIG_SYS_MPC85xx_IFC_OFFSET          0x1e000
-#define CONFIG_SYS_MPC85xx_L2_OFFSET           0x20000
-#define CONFIG_SYS_MPC85xx_DMA_OFFSET          0x21000
-#define CONFIG_SYS_MPC85xx_USB1_OFFSET         0x22000
-#define CONFIG_SYS_MPC85xx_USB2_OFFSET         0x23000
-#define CONFIG_SYS_MPC85xx_USB1_PHY_OFFSET     0xE5000
-#define CONFIG_SYS_MPC85xx_USB2_PHY_OFFSET     0xE5100
+#define CFG_SYS_MPC85xx_GPIO_OFFSET            0xF000
+#define CFG_SYS_MPC85xx_SATA1_OFFSET           0x18000
+#define CFG_SYS_MPC85xx_SATA2_OFFSET           0x19000
+#define CFG_SYS_MPC85xx_IFC_OFFSET             0x1e000
+#define CFG_SYS_MPC85xx_L2_OFFSET              0x20000
+#define CFG_SYS_MPC85xx_DMA_OFFSET             0x21000
+#define CFG_SYS_MPC85xx_USB1_OFFSET            0x22000
+#define CFG_SYS_MPC85xx_USB2_OFFSET            0x23000
+#define CFG_SYS_MPC85xx_USB1_PHY_OFFSET        0xE5000
+#define CFG_SYS_MPC85xx_USB2_PHY_OFFSET        0xE5100
 #ifdef CONFIG_TSECV2
 #define CONFIG_SYS_TSEC1_OFFSET                        0xB0000
 #elif defined(CONFIG_TSECV2_1)
@@ -2549,7 +2549,7 @@ struct ccsr_pman {
 #define CONFIG_SYS_TSEC1_OFFSET                        0x24000
 #endif
 #define CONFIG_SYS_MDIO1_OFFSET                        0x24000
-#define CONFIG_SYS_MPC85xx_ESDHC_OFFSET                0x2e000
+#define CFG_SYS_MPC85xx_ESDHC_OFFSET           0x2e000
 #if defined(CONFIG_ARCH_C29X)
 #define CONFIG_SYS_FSL_SEC_OFFSET              0x80000
 #define CONFIG_SYS_FSL_JR0_OFFSET               0x81000
@@ -2557,8 +2557,8 @@ struct ccsr_pman {
 #define CONFIG_SYS_FSL_SEC_OFFSET              0x30000
 #define CONFIG_SYS_FSL_JR0_OFFSET               0x31000
 #endif
-#define CONFIG_SYS_MPC85xx_SERDES2_OFFSET      0xE3100
-#define CONFIG_SYS_MPC85xx_SERDES1_OFFSET      0xE3000
+#define CFG_SYS_MPC85xx_SERDES2_OFFSET 0xE3100
+#define CFG_SYS_MPC85xx_SERDES1_OFFSET 0xE3000
 #define CONFIG_SYS_SEC_MON_OFFSET              0xE6000
 #define CONFIG_SYS_SFP_OFFSET                  0xE7000
 #define CONFIG_SYS_FSL_QMAN_OFFSET             0x88000
@@ -2569,8 +2569,8 @@ struct ccsr_pman {
 #define CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET       0x1e0000
 #endif
 
-#define CONFIG_SYS_MPC85xx_PIC_OFFSET          0x40000
-#define CONFIG_SYS_MPC85xx_GUTS_OFFSET         0xE0000
+#define CFG_SYS_MPC85xx_PIC_OFFSET             0x40000
+#define CFG_SYS_MPC85xx_GUTS_OFFSET            0xE0000
 #define CONFIG_SYS_FSL_SRIO_OFFSET             0xC0000
 
 #define CONFIG_SYS_FSL_CPC_ADDR        \
@@ -2587,50 +2587,50 @@ struct ccsr_pman {
        (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_RAID_ENGINE_OFFSET)
 #define CONFIG_SYS_FSL_CORENET_RMAN_ADDR \
        (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_RMAN_OFFSET)
-#define CONFIG_SYS_MPC85xx_GUTS_ADDR \
-       (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GUTS_OFFSET)
+#define CFG_SYS_MPC85xx_GUTS_ADDR \
+       (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_GUTS_OFFSET)
 #define CONFIG_SYS_FSL_CORENET_CCM_ADDR \
        (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_CCM_OFFSET)
 #define CONFIG_SYS_FSL_CORENET_CLK_ADDR \
        (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_CLK_OFFSET)
 #define CONFIG_SYS_FSL_CORENET_RCPM_ADDR \
        (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_RCPM_OFFSET)
-#define CONFIG_SYS_MPC85xx_ECM_ADDR \
-       (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ECM_OFFSET)
+#define CFG_SYS_MPC85xx_ECM_ADDR \
+       (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_ECM_OFFSET)
 #define CONFIG_SYS_FSL_DDR_ADDR \
-       (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR_OFFSET)
+       (CONFIG_SYS_IMMR + CFG_SYS_MPC8xxx_DDR_OFFSET)
 #define CONFIG_SYS_FSL_DDR2_ADDR \
-       (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR2_OFFSET)
+       (CONFIG_SYS_IMMR + CFG_SYS_MPC8xxx_DDR2_OFFSET)
 #define CONFIG_SYS_FSL_DDR3_ADDR \
-       (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR3_OFFSET)
+       (CONFIG_SYS_IMMR + CFG_SYS_MPC8xxx_DDR3_OFFSET)
 #define CONFIG_SYS_LBC_ADDR \
-       (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_LBC_OFFSET)
+       (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_LBC_OFFSET)
 #define CONFIG_SYS_IFC_ADDR \
-       (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_IFC_OFFSET)
-#define CONFIG_SYS_MPC85xx_ESPI_ADDR \
-       (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ESPI_OFFSET)
-#define CONFIG_SYS_MPC85xx_PCIX_ADDR \
-       (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIX_OFFSET)
-#define CONFIG_SYS_MPC85xx_PCIX2_ADDR \
-       (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIX2_OFFSET)
-#define CONFIG_SYS_MPC85xx_GPIO_ADDR \
-       (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GPIO_OFFSET)
-#define CONFIG_SYS_MPC85xx_SATA1_ADDR \
-       (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SATA1_OFFSET)
-#define CONFIG_SYS_MPC85xx_SATA2_ADDR \
-       (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SATA2_OFFSET)
-#define CONFIG_SYS_MPC85xx_L2_ADDR \
-       (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_L2_OFFSET)
-#define CONFIG_SYS_MPC85xx_DMA_ADDR \
-       (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DMA_OFFSET)
-#define CONFIG_SYS_MPC85xx_ESDHC_ADDR \
-       (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ESDHC_OFFSET)
-#define CONFIG_SYS_MPC8xxx_PIC_ADDR \
-       (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PIC_OFFSET)
-#define CONFIG_SYS_MPC85xx_SERDES1_ADDR \
-       (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES1_OFFSET)
-#define CONFIG_SYS_MPC85xx_SERDES2_ADDR \
-       (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES2_OFFSET)
+       (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_IFC_OFFSET)
+#define CFG_SYS_MPC85xx_ESPI_ADDR \
+       (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_ESPI_OFFSET)
+#define CFG_SYS_MPC85xx_PCIX_ADDR \
+       (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_PCIX_OFFSET)
+#define CFG_SYS_MPC85xx_PCIX2_ADDR \
+       (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_PCIX2_OFFSET)
+#define CFG_SYS_MPC85xx_GPIO_ADDR \
+       (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_GPIO_OFFSET)
+#define CFG_SYS_MPC85xx_SATA1_ADDR \
+       (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_SATA1_OFFSET)
+#define CFG_SYS_MPC85xx_SATA2_ADDR \
+       (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_SATA2_OFFSET)
+#define CFG_SYS_MPC85xx_L2_ADDR \
+       (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_L2_OFFSET)
+#define CFG_SYS_MPC85xx_DMA_ADDR \
+       (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_DMA_OFFSET)
+#define CFG_SYS_MPC85xx_ESDHC_ADDR \
+       (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_ESDHC_OFFSET)
+#define CFG_SYS_MPC8xxx_PIC_ADDR \
+       (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_PIC_OFFSET)
+#define CFG_SYS_MPC85xx_SERDES1_ADDR \
+       (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_SERDES1_OFFSET)
+#define CFG_SYS_MPC85xx_SERDES2_ADDR \
+       (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_SERDES2_OFFSET)
 #define CONFIG_SYS_FSL_CORENET_SERDES_ADDR \
        (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES_OFFSET)
 #define CONFIG_SYS_FSL_CORENET_SERDES2_ADDR \
@@ -2639,14 +2639,14 @@ struct ccsr_pman {
        (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES3_OFFSET)
 #define CONFIG_SYS_FSL_CORENET_SERDES4_ADDR \
        (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES4_OFFSET)
-#define CONFIG_SYS_MPC85xx_USB1_ADDR \
-       (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB1_OFFSET)
-#define CONFIG_SYS_MPC85xx_USB2_ADDR \
-       (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB2_OFFSET)
-#define CONFIG_SYS_MPC85xx_USB1_PHY_ADDR \
-       (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB1_PHY_OFFSET)
-#define CONFIG_SYS_MPC85xx_USB2_PHY_ADDR \
-       (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB2_PHY_OFFSET)
+#define CFG_SYS_MPC85xx_USB1_ADDR \
+       (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_USB1_OFFSET)
+#define CFG_SYS_MPC85xx_USB2_ADDR \
+       (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_USB2_OFFSET)
+#define CFG_SYS_MPC85xx_USB1_PHY_ADDR \
+       (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_USB1_PHY_OFFSET)
+#define CFG_SYS_MPC85xx_USB2_PHY_ADDR \
+       (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_USB2_PHY_OFFSET)
 #define CONFIG_SYS_FSL_SEC_ADDR \
        (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET)
 #define CONFIG_SYS_FSL_JR0_ADDR \
@@ -2663,17 +2663,17 @@ struct ccsr_pman {
        (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_PAMU_OFFSET)
 
 #define CONFIG_SYS_PCI1_ADDR \
-       (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCI1_OFFSET)
+       (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_PCI1_OFFSET)
 #define CONFIG_SYS_PCI2_ADDR \
-       (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCI2_OFFSET)
+       (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_PCI2_OFFSET)
 #define CONFIG_SYS_PCIE1_ADDR \
-       (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE1_OFFSET)
+       (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_PCIE1_OFFSET)
 #define CONFIG_SYS_PCIE2_ADDR \
-       (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE2_OFFSET)
+       (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_PCIE2_OFFSET)
 #define CONFIG_SYS_PCIE3_ADDR \
-       (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE3_OFFSET)
+       (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_PCIE3_OFFSET)
 #define CONFIG_SYS_PCIE4_ADDR \
-       (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE4_OFFSET)
+       (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_PCIE4_OFFSET)
 
 #define CONFIG_SYS_SFP_ADDR  \
        (CONFIG_SYS_IMMR + CONFIG_SYS_SFP_OFFSET)
@@ -2752,9 +2752,9 @@ struct dcsr_dcfg_regs {
        u8  res_524[0x1000 - 0x524]; /* 0x524 - 0x1000 */
 };
 
-#define CONFIG_SYS_MPC85xx_SCFG \
-       (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SCFG_OFFSET)
-#define CONFIG_SYS_MPC85xx_SCFG_OFFSET 0xfc000
+#define CFG_SYS_MPC85xx_SCFG \
+       (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_SCFG_OFFSET)
+#define CFG_SYS_MPC85xx_SCFG_OFFSET    0xfc000
 /* The supplement configuration unit register */
 struct ccsr_scfg {
        u32 dpslpcr;    /* 0x000 Deep Sleep Control register */

diff --git a/arch/powerpc/include/asm/mpc85xx_gpio.h b/arch/powerpc/include/asm/mpc85xx_gpio.h
index feebe15..0ed6bec 100644 (file)
--- a/arch/powerpc/include/asm/mpc85xx_gpio.h
+++ b/arch/powerpc/include/asm/mpc85xx_gpio.h
@@ -20,7 +20,7 @@
 static inline void mpc85xx_gpio_set(unsigned int mask,
                unsigned int dir, unsigned int val)
 {
-       ccsr_gpio_t *gpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
+       ccsr_gpio_t *gpio = (void *)(CFG_SYS_MPC85xx_GPIO_ADDR);
 
        /* First mask off the unwanted parts of "dir" and "val" */
        dir &= mask;
@@ -56,7 +56,7 @@ static inline void mpc85xx_gpio_set_high(unsigned int gpios)
 
 static inline unsigned int mpc85xx_gpio_get(unsigned int mask)
 {
-       ccsr_gpio_t *gpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
+       ccsr_gpio_t *gpio = (void *)(CFG_SYS_MPC85xx_GPIO_ADDR);
 
        /* Read the requested values */
        return in_be32(&gpio->gpdat) & mask;

diff --git a/board/freescale/common/fsl_chain_of_trust.c b/board/freescale/common/fsl_chain_of_trust.c
index ad72353..3bd570a 100644 (file)
--- a/board/freescale/common/fsl_chain_of_trust.c
+++ b/board/freescale/common/fsl_chain_of_trust.c
@@ -28,7 +28,7 @@
 #endif
 
 #if defined(CONFIG_MPC85xx)
-#define CONFIG_DCFG_ADDR       CONFIG_SYS_MPC85xx_GUTS_ADDR
+#define CONFIG_DCFG_ADDR       CFG_SYS_MPC85xx_GUTS_ADDR
 #else
 #define CONFIG_DCFG_ADDR       CONFIG_SYS_FSL_GUTS_ADDR
 #endif

diff --git a/board/freescale/common/fsl_validate.c b/board/freescale/common/fsl_validate.c
index 7a23d8f..bc1b855 100644 (file)
--- a/board/freescale/common/fsl_validate.c
+++ b/board/freescale/common/fsl_validate.c
@@ -83,7 +83,7 @@ static u32 check_ie(struct fsl_secboot_img_priv *img)
 
 int get_csf_base_addr(u32 *csf_addr, u32 *flash_base_addr)
 {
-       struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+       struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
        u32 csf_hdr_addr = in_be32(&gur->scratchrw[0]);
        u32 csf_flash_offset = csf_hdr_addr & ~(CONFIG_SYS_PBI_FLASH_BASE);
        u32 flash_addr, addr;

diff --git a/board/freescale/common/mpc85xx_sleep.c b/board/freescale/common/mpc85xx_sleep.c
index d2bb173..71922aa 100644 (file)
--- a/board/freescale/common/mpc85xx_sleep.c
+++ b/board/freescale/common/mpc85xx_sleep.c
@@ -24,7 +24,7 @@ void __weak board_sleep_prepare(void)
 
 bool is_warm_boot(void)
 {
-       struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+       struct ccsr_gur __iomem *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR;
 
        if (in_be32(&gur->scrtsr[0]) & DCFG_CCSR_CRSTSR_WDRFR)
                return 1;
@@ -46,7 +46,7 @@ static void dp_ddr_restore(void)
 {
        u64 *src, *dst;
        int i;
-       struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_MPC85xx_SCFG;
+       struct ccsr_scfg __iomem *scfg = (void *)CFG_SYS_MPC85xx_SCFG;
 
        /* get the address of ddr date from SPARECR3 */
        src = (u64 *)(in_be32(&scfg->sparecr[2]) + DDR_BUFF_LEN - 8);
@@ -80,7 +80,7 @@ int fsl_dp_resume(void)
 {
        u32 start_addr;
        void (*kernel_resume)(void);
-       struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_MPC85xx_SCFG;
+       struct ccsr_scfg __iomem *scfg = (void *)CFG_SYS_MPC85xx_SCFG;
 
        if (!is_warm_boot())
                return 0;

diff --git a/board/freescale/common/vid.c b/board/freescale/common/vid.c
index d2c9bbb..3f5f33e 100644 (file)
--- a/board/freescale/common/vid.c
+++ b/board/freescale/common/vid.c
@@ -542,7 +542,7 @@ int adjust_vdd(ulong vdd_override)
        struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 #else
        ccsr_gur_t __iomem *gur =
-               (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+               (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR);
 #endif
        u8 vid;
        u32 fusesr;

diff --git a/board/freescale/mpc8548cds/mpc8548cds.c b/board/freescale/mpc8548cds/mpc8548cds.c
index 8886d8b..e4c951f 100644 (file)
--- a/board/freescale/mpc8548cds/mpc8548cds.c
+++ b/board/freescale/mpc8548cds/mpc8548cds.c
@@ -33,8 +33,8 @@ void local_bus_init(void);
 
 int checkboard (void)
 {
-       volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-       volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
+       volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
+       volatile ccsr_local_ecm_t *ecm = (void *)(CFG_SYS_MPC85xx_ECM_ADDR);
 
        /* PCI slot in USER bits CSR[6:7] by convention. */
        uint pci_slot = get_pci_slot ();
@@ -68,7 +68,7 @@ int checkboard (void)
 void
 local_bus_init(void)
 {
-       volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+       volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
        volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
 
        uint clkdiv;

diff --git a/board/freescale/p1010rdb/p1010rdb.c b/board/freescale/p1010rdb/p1010rdb.c
index c796330..c39df46 100644 (file)
--- a/board/freescale/p1010rdb/p1010rdb.c
+++ b/board/freescale/p1010rdb/p1010rdb.c
@@ -82,7 +82,7 @@ struct cpld_data {
 
 int board_early_init_f(void)
 {
-       ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
+       ccsr_gpio_t *pgpio = (void *)(CFG_SYS_MPC85xx_GPIO_ADDR);
        struct fsl_ifc ifc = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
        /* Clock configuration to access CPLD using IFC(GPCM) */
        setbits_be32(&ifc.gregs->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT);
@@ -131,7 +131,7 @@ int board_early_init_r(void)
 
 int config_board_mux(int ctrl_type)
 {
-       ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+       ccsr_gur_t __iomem *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
        u8 tmp;
 
 #if CONFIG_IS_ENABLED(DM_I2C)
@@ -668,7 +668,7 @@ void board_reset(void)
 
 int misc_init_r(void)
 {
-       ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+       ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
 
        if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "can")) {
                clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_CAN1_TDM |

diff --git a/board/freescale/p1010rdb/spl.c b/board/freescale/p1010rdb/spl.c
index 8869500..0db11f4 100644 (file)
--- a/board/freescale/p1010rdb/spl.c
+++ b/board/freescale/p1010rdb/spl.c
@@ -28,7 +28,7 @@ phys_size_t get_effective_memsize(void)
 void board_init_f(ulong bootflag)
 {
        u32 plat_ratio;
-       ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+       ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR;
        struct fsl_ifc ifc = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
 
        console_init_f();

diff --git a/board/freescale/p1010rdb/spl_minimal.c b/board/freescale/p1010rdb/spl_minimal.c
index a956c5a..a262d5c 100644 (file)
--- a/board/freescale/p1010rdb/spl_minimal.c
+++ b/board/freescale/p1010rdb/spl_minimal.c
@@ -20,7 +20,7 @@ DECLARE_GLOBAL_DATA_PTR;
 void board_init_f(ulong bootflag)
 {
        u32 plat_ratio;
-       ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+       ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR;
 
 #if defined(CONFIG_SYS_NAND_BR_PRELIM) && defined(CONFIG_SYS_NAND_OR_PRELIM)
        set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM);

diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
index b301491..2999c85 100644 (file)
--- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
+++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
@@ -149,7 +149,7 @@ void board_cpld_init(void)
 void board_gpio_init(void)
 {
 #ifdef CONFIG_QE
-       ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+       ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
        par_io_t *par_io = (par_io_t *) &(gur->qe_par_io);
 
        /* Enable VSC7385 switch */
@@ -159,7 +159,7 @@ void board_gpio_init(void)
        setbits_be32(&par_io[GPIO_SLIC_PORT].cpdat, GPIO_SLIC_DATA);
 #else
 
-       ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
+       ccsr_gpio_t *pgpio = (void *)(CFG_SYS_MPC85xx_GPIO_ADDR);
 
        /*
         * GPIO10 DDR Reset, open drain
@@ -197,7 +197,7 @@ void board_gpio_init(void)
 
 int board_early_init_f(void)
 {
-       ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+       ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
 
        setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SDHC_CD);
 #ifndef SDHC_WP_IS_GPIO
@@ -227,7 +227,7 @@ int board_early_init_f(void)
 int checkboard(void)
 {
        struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
-       ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+       ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
        u8 in, out, invert, io_config, val;
        int bus_num = CONFIG_SYS_SPD_BUS_NUM;
 
@@ -370,7 +370,7 @@ int board_eth_init(struct bd_info *bis)
        struct fsl_pq_mdio_info mdio_info;
        struct tsec_info_struct tsec_info[4];
        ccsr_gur_t *gur __attribute__((unused)) =
-               (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+               (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
        int num = 0;
 
 #ifdef CONFIG_TSEC1
@@ -418,7 +418,7 @@ int board_eth_init(struct bd_info *bis)
 static void fix_max6370_watchdog(void *blob)
 {
        int off = fdt_node_offset_by_compatible(blob, -1, "maxim,max6370");
-       ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
+       ccsr_gpio_t *pgpio = (void *)(CFG_SYS_MPC85xx_GPIO_ADDR);
        u32 gpioval = in_be32(&pgpio->gpdat);
 
        /*

diff --git a/board/freescale/p1_p2_rdb_pc/spl.c b/board/freescale/p1_p2_rdb_pc/spl.c
index eda84bf..e7d4428 100644 (file)
--- a/board/freescale/p1_p2_rdb_pc/spl.c
+++ b/board/freescale/p1_p2_rdb_pc/spl.c
@@ -29,7 +29,7 @@ phys_size_t get_effective_memsize(void)
 void board_init_f(ulong bootflag)
 {
        u32 plat_ratio, bus_clk;
-       ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+       ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR;
 
        /*
         * Call board_early_init_f() as early as possible as it workarounds

diff --git a/board/freescale/p1_p2_rdb_pc/spl_minimal.c b/board/freescale/p1_p2_rdb_pc/spl_minimal.c
index 72beead..e467c7a 100644 (file)
--- a/board/freescale/p1_p2_rdb_pc/spl_minimal.c
+++ b/board/freescale/p1_p2_rdb_pc/spl_minimal.c
@@ -19,7 +19,7 @@ DECLARE_GLOBAL_DATA_PTR;
 void board_init_f(ulong bootflag)
 {
        u32 plat_ratio;
-       ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+       ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR;
 
 #if defined(CONFIG_SYS_NAND_BR_PRELIM) && defined(CONFIG_SYS_NAND_OR_PRELIM)
        set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM);

diff --git a/board/freescale/p2041rdb/p2041rdb.c b/board/freescale/p2041rdb/p2041rdb.c
index 2a84e9b..859ffc4 100644 (file)
--- a/board/freescale/p2041rdb/p2041rdb.c
+++ b/board/freescale/p2041rdb/p2041rdb.c
@@ -66,7 +66,7 @@ int checkboard(void)
 
 int board_early_init_f(void)
 {
-       ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+       ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
 
        /* board only uses the DDR_MCK0/1, so disable the DDR_MCK2/3 */
        setbits_be32(&gur->ddrclkdr, 0x000f000f);
@@ -81,7 +81,7 @@ int board_early_init_f(void)
 
 void board_config_lanes_mux(void)
 {
-       ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+       ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR;
        int srds_prtcl = (in_be32(&gur->rcwsr[4]) &
                                FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26;
 

diff --git a/board/freescale/t102xrdb/eth_t102xrdb.c b/board/freescale/t102xrdb/eth_t102xrdb.c
index 4f04d2e..be42efa 100644 (file)
--- a/board/freescale/t102xrdb/eth_t102xrdb.c
+++ b/board/freescale/t102xrdb/eth_t102xrdb.c
@@ -33,7 +33,7 @@ int board_eth_init(struct bd_info *bis)
        struct memac_mdio_info dtsec_mdio_info;
        struct memac_mdio_info tgec_mdio_info;
        struct mii_dev *dev;
-       ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+       ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
        u32 srds_s1;
 
        srds_s1 = in_be32(&gur->rcwsr[4]) &

diff --git a/board/freescale/t102xrdb/spl.c b/board/freescale/t102xrdb/spl.c
index af15da5..3ba94fe 100644 (file)
--- a/board/freescale/t102xrdb/spl.c
+++ b/board/freescale/t102xrdb/spl.c
@@ -29,7 +29,7 @@ phys_size_t get_effective_memsize(void)
 #define GPIO1_SD_SEL 0x00020000
 int board_mmc_getcd(struct mmc *mmc)
 {
-       ccsr_gpio_t __iomem *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
+       ccsr_gpio_t __iomem *pgpio = (void *)(CFG_SYS_MPC85xx_GPIO_ADDR);
        u32 val = in_be32(&pgpio->gpdat);
 
        /* GPIO1_14, 0: eMMC, 1: SD */
@@ -40,7 +40,7 @@ int board_mmc_getcd(struct mmc *mmc)
 
 int board_mmc_getwp(struct mmc *mmc)
 {
-       ccsr_gpio_t __iomem *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
+       ccsr_gpio_t __iomem *pgpio = (void *)(CFG_SYS_MPC85xx_GPIO_ADDR);
        u32 val = in_be32(&pgpio->gpdat);
 
        val &= GPIO1_SD_SEL;
@@ -52,7 +52,7 @@ int board_mmc_getwp(struct mmc *mmc)
 void board_init_f(ulong bootflag)
 {
        u32 plat_ratio, sys_clk, ccb_clk;
-       ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+       ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR;
 
        /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
        memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t));

diff --git a/board/freescale/t102xrdb/t102xrdb.c b/board/freescale/t102xrdb/t102xrdb.c
index 539a5c7..f777f5a 100644 (file)
--- a/board/freescale/t102xrdb/t102xrdb.c
+++ b/board/freescale/t102xrdb/t102xrdb.c
@@ -49,7 +49,7 @@ int checkboard(void)
 {
        struct cpu_type *cpu = gd->arch.cpu;
        static const char *freq[3] = {"100.00MHZ", "125.00MHz", "156.25MHZ"};
-       ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+       ccsr_gur_t __iomem *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
        u32 srds_s1;
 
        srds_s1 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
@@ -99,7 +99,7 @@ int checkboard(void)
 #ifdef CONFIG_TARGET_T1024RDB
 static void board_mux_lane(void)
 {
-       ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+       ccsr_gur_t __iomem *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
        u32 srds_prtcl_s1;
        u8 reg = CPLD_READ(misc_ctl_status);
 
@@ -222,7 +222,7 @@ static void fdt_enable_nor(void *blob)
 
 int board_mmc_getcd(struct mmc *mmc)
 {
-       ccsr_gpio_t __iomem *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
+       ccsr_gpio_t __iomem *pgpio = (void *)(CFG_SYS_MPC85xx_GPIO_ADDR);
        u32 val = in_be32(&pgpio->gpdat);
 
        /* GPIO1_14, 0: eMMC, 1: SD/MMC */
@@ -233,7 +233,7 @@ int board_mmc_getcd(struct mmc *mmc)
 
 int board_mmc_getwp(struct mmc *mmc)
 {
-       ccsr_gpio_t __iomem *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
+       ccsr_gpio_t __iomem *pgpio = (void *)(CFG_SYS_MPC85xx_GPIO_ADDR);
        u32 val = in_be32(&pgpio->gpdat);
 
        val &= GPIO1_SD_SEL;
@@ -243,8 +243,8 @@ int board_mmc_getwp(struct mmc *mmc)
 
 static u32 t1023rdb_ctrl(u32 ctrl_type)
 {
-       ccsr_gpio_t __iomem *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
-       ccsr_gur_t __iomem  *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+       ccsr_gpio_t __iomem *pgpio = (void *)(CFG_SYS_MPC85xx_GPIO_ADDR);
+       ccsr_gur_t __iomem  *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
        u32 val;
        u8 tmp;
        int bus_num = I2C_PCA6408_BUS_NUM;
@@ -274,7 +274,7 @@ static u32 t1023rdb_ctrl(u32 ctrl_type)
                setbits_be32(&pgpio->gpdir, GPIO1_SD_SEL);
                break;
        case GPIO3_GET_VERSION:
-               pgpio = (ccsr_gpio_t *)(CONFIG_SYS_MPC85xx_GPIO_ADDR
+               pgpio = (ccsr_gpio_t *)(CFG_SYS_MPC85xx_GPIO_ADDR
                         + GPIO3_OFFSET);
                val = in_be32(&pgpio->gpdat);
                val = ((val & GPIO3_BRD_VER_MASK) >> 26) & 0x3;
@@ -323,7 +323,7 @@ static u32 t1023rdb_ctrl(u32 ctrl_type)
                setbits_be32(&pgpio->gpdir, GPIO1_SD_SEL);
                break;
        case GPIO3_GET_VERSION:
-               pgpio = (ccsr_gpio_t *)(CONFIG_SYS_MPC85xx_GPIO_ADDR
+               pgpio = (ccsr_gpio_t *)(CFG_SYS_MPC85xx_GPIO_ADDR
                         + GPIO3_OFFSET);
                val = in_be32(&pgpio->gpdat);
                val = ((val & GPIO3_BRD_VER_MASK) >> 26) & 0x3;

diff --git a/board/freescale/t104xrdb/eth.c b/board/freescale/t104xrdb/eth.c
index 3ae5d72..bb6641b 100644 (file)
--- a/board/freescale/t104xrdb/eth.c
+++ b/board/freescale/t104xrdb/eth.c
@@ -142,7 +142,7 @@ int board_eth_init(struct bd_info *bis)
        if (serdes_get_first_lane(FSL_SRDS_1, SGMII_FM1_DTSEC2) < 0) {
                /* Enable L2 On MAC2 using SCFG */
                struct ccsr_scfg *scfg = (struct ccsr_scfg *)
-                               CONFIG_SYS_MPC85xx_SCFG;
+                               CFG_SYS_MPC85xx_SCFG;
 
                out_be32(&scfg->esgmiiselcr, in_be32(&scfg->esgmiiselcr) |
                         (0x80000000));

diff --git a/board/freescale/t104xrdb/spl.c b/board/freescale/t104xrdb/spl.c
index dfaff1a..c7fb427 100644 (file)
--- a/board/freescale/t104xrdb/spl.c
+++ b/board/freescale/t104xrdb/spl.c
@@ -33,7 +33,7 @@ void board_init_f(ulong bootflag)
        u32 porsr1, pinctl;
        u32 svr = get_svr();
 #endif
-       ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+       ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR;
 
 #if defined(CONFIG_SPL_NAND_BOOT) && defined(CONFIG_A008044_WORKAROUND)
        if (IS_SVR_REV(svr, 1, 0)) {

diff --git a/board/freescale/t104xrdb/t104xrdb.c b/board/freescale/t104xrdb/t104xrdb.c
index 7800434..7d3fd29 100644 (file)
--- a/board/freescale/t104xrdb/t104xrdb.c
+++ b/board/freescale/t104xrdb/t104xrdb.c
@@ -93,7 +93,7 @@ int board_early_init_r(void)
 
 int misc_init_r(void)
 {
-       ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+       ccsr_gur_t __iomem *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
        u32 srds_s1;
 
        srds_s1 = in_be32(&gur->rcwsr[4]) >> 24;

diff --git a/board/freescale/t208xqds/eth_t208xqds.c b/board/freescale/t208xqds/eth_t208xqds.c
index 2d7fc8b..dd1c35f 100644 (file)
--- a/board/freescale/t208xqds/eth_t208xqds.c
+++ b/board/freescale/t208xqds/eth_t208xqds.c
@@ -189,7 +189,7 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
        const char *phyconn;
        int off;
 
-       ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+       ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
 #ifdef CONFIG_TARGET_T2080QDS
        serdes_corenet_t *srds_regs =
                (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
@@ -413,7 +413,7 @@ void fdt_fixup_board_enet(void *fdt)
  */
 static void initialize_lane_to_slot(void)
 {
-       ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+       ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
        u32 srds_s1 = in_be32(&gur->rcwsr[4]) &
                                FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
 
@@ -459,7 +459,7 @@ int board_eth_init(struct bd_info *bis)
        int i, idx, lane, slot, interface;
        struct memac_mdio_info dtsec_mdio_info;
        struct memac_mdio_info tgec_mdio_info;
-       ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+       ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
        u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
        u32 srds_s1;
 

diff --git a/board/freescale/t208xqds/spl.c b/board/freescale/t208xqds/spl.c
index e934a3c..8b68329 100644 (file)
--- a/board/freescale/t208xqds/spl.c
+++ b/board/freescale/t208xqds/spl.c
@@ -67,7 +67,7 @@ unsigned long get_board_ddr_clk(void)
 void board_init_f(ulong bootflag)
 {
        u32 plat_ratio, sys_clk, ccb_clk;
-       ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+       ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR;
 
        /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
        memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t));

diff --git a/board/freescale/t208xqds/t208xqds.c b/board/freescale/t208xqds/t208xqds.c
index 1da3a71..82710cf 100644 (file)
--- a/board/freescale/t208xqds/t208xqds.c
+++ b/board/freescale/t208xqds/t208xqds.c
@@ -88,7 +88,7 @@ int i2c_multiplexer_select_vid_channel(u8 channel)
 
 int brd_mux_lane_to_slot(void)
 {
-       ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+       ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
        u32 srds_prtcl_s1;
 
        srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &

diff --git a/board/freescale/t208xrdb/spl.c b/board/freescale/t208xrdb/spl.c
index 60fe084..3f9b1fa 100644 (file)
--- a/board/freescale/t208xrdb/spl.c
+++ b/board/freescale/t208xrdb/spl.c
@@ -27,7 +27,7 @@ phys_size_t get_effective_memsize(void)
 void board_init_f(ulong bootflag)
 {
        u32 plat_ratio, sys_clk, ccb_clk;
-       ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+       ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR;
 
        /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
        memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t));

diff --git a/board/freescale/t4rdb/eth.c b/board/freescale/t4rdb/eth.c
index 34ffaa6..4041b3d 100644 (file)
--- a/board/freescale/t4rdb/eth.c
+++ b/board/freescale/t4rdb/eth.c
@@ -43,7 +43,7 @@ int board_eth_init(struct bd_info *bis)
        struct memac_mdio_info dtsec_mdio_info;
        struct memac_mdio_info tgec_mdio_info;
        struct mii_dev *dev;
-       ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+       ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
        u32 srds_prtcl_s1, srds_prtcl_s2;
 
        srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &

diff --git a/board/freescale/t4rdb/spl.c b/board/freescale/t4rdb/spl.c
index c7d5de3..72d3b80 100644 (file)
--- a/board/freescale/t4rdb/spl.c
+++ b/board/freescale/t4rdb/spl.c
@@ -33,7 +33,7 @@ phys_size_t get_effective_memsize(void)
 void board_init_f(ulong bootflag)
 {
        u32 plat_ratio, sys_clk, ccb_clk;
-       ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+       ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR;
 
        /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
        memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t));

diff --git a/board/keymile/kmcent2/kmcent2.c b/board/keymile/kmcent2/kmcent2.c
index 4486538..758bd5b 100644 (file)
--- a/board/keymile/kmcent2/kmcent2.c
+++ b/board/keymile/kmcent2/kmcent2.c
@@ -45,7 +45,7 @@ int checkboard(void)
 int board_early_init_f(void)
 {
        struct fsl_ifc ifc = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
-       ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+       ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
        bool cpuwd_flag = false;
 
        /* board specific IFC configuration: increased bus turnaround time */
@@ -221,8 +221,8 @@ EVENT_SPY(EVT_MISC_INIT_F, kmcent2_misc_init_f);
 int misc_init_r(void)
 {
        serdes_corenet_t *regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
-       struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_MPC85xx_SCFG;
-       ccsr_gur_t __iomem *gur = (ccsr_gur_t __iomem *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+       struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_MPC85xx_SCFG;
+       ccsr_gur_t __iomem *gur = (ccsr_gur_t __iomem *)CFG_SYS_MPC85xx_GUTS_ADDR;
 
        /* check SERDES bank 0 reference clock */
        u32 actual = in_be32(&regs->bank[USED_SRDS_BANK].pllcr0);

diff --git a/board/socrates/socrates.c b/board/socrates/socrates.c
index 33b7261..eaba875 100644 (file)
--- a/board/socrates/socrates.c
+++ b/board/socrates/socrates.c
@@ -35,7 +35,7 @@ ulong flash_get_size (ulong base, int banknum);
 
 int checkboard (void)
 {
-       volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+       volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
        char buf[64];
        int f;
        int i = env_get_f("serial#", buf, sizeof(buf));
@@ -139,7 +139,7 @@ int misc_init_r (void)
 void local_bus_init (void)
 {
        volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
-       volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
+       volatile ccsr_local_ecm_t *ecm = (void *)(CFG_SYS_MPC85xx_ECM_ADDR);
        sys_info_t sysinfo;
        uint clkdiv;
        uint lbc_mhz;
@@ -175,7 +175,7 @@ void local_bus_init (void)
 #ifdef CONFIG_BOARD_EARLY_INIT_R
 int board_early_init_r (void)
 {
-       volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+       volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
 
        /* set and reset the GPIO pin 2 which will reset the W83782G chip */
        out_8((unsigned char*)&gur->gpoutdr, 0x3F );

diff --git a/board/xes/common/fsl_8xxx_clk.c b/board/xes/common/fsl_8xxx_clk.c
index 20e88d4..c36b2af 100644 (file)
--- a/board/xes/common/fsl_8xxx_clk.c
+++ b/board/xes/common/fsl_8xxx_clk.c
@@ -13,7 +13,7 @@
 unsigned long get_board_sys_clk(void)
 {
 #if defined(CONFIG_MPC85xx)
-       volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+       volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
 #elif defined(CONFIG_MPC86xx)
        immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
        volatile ccsr_gur_t *gur = &immap->im_gur;
@@ -36,7 +36,7 @@ unsigned long get_board_sys_clk(void)
  */
 unsigned long get_board_ddr_clk(void)
 {
-       volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+       volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
        u32 ddr_ratio = (in_be32(&gur->porpllsr) & 0x00003e00) >> 9;
 
        if (ddr_ratio == 0x7)

diff --git a/board/xes/common/fsl_8xxx_misc.c b/board/xes/common/fsl_8xxx_misc.c
index b268103..9d92103 100644 (file)
--- a/board/xes/common/fsl_8xxx_misc.c
+++ b/board/xes/common/fsl_8xxx_misc.c
@@ -28,7 +28,7 @@ int board_flash_wp_on(void)
 uint get_board_derivative(void)
 {
 #if defined(CONFIG_MPC85xx)
-       volatile ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+       volatile ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR;
 #elif defined(CONFIG_MPC86xx)
        volatile immap_t *immap = (immap_t *)CONFIG_SYS_CCSRBAR;
        volatile ccsr_gur_t *gur = &immap->im_gur;

diff --git a/drivers/ddr/fsl/mpc85xx_ddr_gen2.c b/drivers/ddr/fsl/mpc85xx_ddr_gen2.c
index d7b8064..9ed80d6 100644 (file)
--- a/drivers/ddr/fsl/mpc85xx_ddr_gen2.c
+++ b/drivers/ddr/fsl/mpc85xx_ddr_gen2.c
@@ -21,7 +21,7 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
                (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
 
 #if defined(CONFIG_SYS_FSL_ERRATUM_NMG_DDR120) && defined(CONFIG_MPC85xx)
-       ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+       ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
        uint svr;
 #endif
 

diff --git a/drivers/ddr/fsl/mpc85xx_ddr_gen3.c b/drivers/ddr/fsl/mpc85xx_ddr_gen3.c
index 1ed4d50..47339c5 100644 (file)
--- a/drivers/ddr/fsl/mpc85xx_ddr_gen3.c
+++ b/drivers/ddr/fsl/mpc85xx_ddr_gen3.c
@@ -33,7 +33,7 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
        int timeout;
 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
        int timeout_save;
-       volatile ccsr_local_ecm_t *ecm = (void *)CONFIG_SYS_MPC85xx_ECM_ADDR;
+       volatile ccsr_local_ecm_t *ecm = (void *)CFG_SYS_MPC85xx_ECM_ADDR;
        unsigned int csn_bnds_backup = 0, cs_sa, cs_ea, *csn_bnds_t;
        int csn = -1;
 #endif

diff --git a/drivers/dma/fsl_dma.c b/drivers/dma/fsl_dma.c
index 1864b5d..cd78e45 100644 (file)
--- a/drivers/dma/fsl_dma.c
+++ b/drivers/dma/fsl_dma.c
@@ -24,9 +24,9 @@
 
 
 #if defined(CONFIG_MPC83xx)
-dma83xx_t *dma_base = (void *)(CONFIG_SYS_MPC83xx_DMA_ADDR);
+dma83xx_t *dma_base = (void *)(CFG_SYS_MPC83xx_DMA_ADDR);
 #elif defined(CONFIG_MPC85xx)
-ccsr_dma_t *dma_base = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR);
+ccsr_dma_t *dma_base = (void *)(CFG_SYS_MPC85xx_DMA_ADDR);
 #elif defined(CONFIG_MPC86xx)
 ccsr_dma_t *dma_base = (void *)(CONFIG_SYS_MPC86xx_DMA_ADDR);
 #else

diff --git a/drivers/net/fm/b4860.c b/drivers/net/fm/b4860.c
index e622d86..1c5543e 100644 (file)
--- a/drivers/net/fm/b4860.c
+++ b/drivers/net/fm/b4860.c
@@ -25,7 +25,7 @@ u32 port_to_devdisr[] = {
 
 static int is_device_disabled(enum fm_port port)
 {
-       ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+       ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
        u32 devdisr2 = in_be32(&gur->devdisr2);
 
        return port_to_devdisr[port] & devdisr2;
@@ -33,14 +33,14 @@ static int is_device_disabled(enum fm_port port)
 
 void fman_disable_port(enum fm_port port)
 {
-       ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+       ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
 
        setbits_be32(&gur->devdisr2, port_to_devdisr[port]);
 }
 
 void fman_enable_port(enum fm_port port)
 {
-       ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+       ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
 
        clrbits_be32(&gur->devdisr2, port_to_devdisr[port]);
 }
@@ -51,7 +51,7 @@ phy_interface_t fman_port_enet_if(enum fm_port port)
        u32 serdes2_prtcl;
        char buffer[HWCONFIG_BUFFER_SIZE];
        char *buf = NULL;
-       ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+       ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
 #endif
 
        if (is_device_disabled(port))

diff --git a/drivers/net/fm/p1023.c b/drivers/net/fm/p1023.c
index c9b85fc..9013b27 100644 (file)
--- a/drivers/net/fm/p1023.c
+++ b/drivers/net/fm/p1023.c
@@ -16,7 +16,7 @@ static u32 port_to_devdisr[] = {
 
 static int is_device_disabled(enum fm_port port)
 {
-       ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+       ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
        u32 devdisr = in_be32(&gur->devdisr);
 
        return port_to_devdisr[port] & devdisr;
@@ -24,7 +24,7 @@ static int is_device_disabled(enum fm_port port)
 
 void fman_disable_port(enum fm_port port)
 {
-       ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+       ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
 
        /* don't allow disabling of DTSEC1 as its needed for MDIO */
        if (port == FM1_DTSEC1)
@@ -35,14 +35,14 @@ void fman_disable_port(enum fm_port port)
 
 void fman_enable_port(enum fm_port port)
 {
-       ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+       ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
 
        clrbits_be32(&gur->devdisr, port_to_devdisr[port]);
 }
 
 phy_interface_t fman_port_enet_if(enum fm_port port)
 {
-       ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+       ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
        u32 pordevsr = in_be32(&gur->pordevsr);
 
        if (is_device_disabled(port))

diff --git a/drivers/net/fm/p4080.c b/drivers/net/fm/p4080.c
index 577ee22..7ad9932 100644 (file)
--- a/drivers/net/fm/p4080.c
+++ b/drivers/net/fm/p4080.c
@@ -24,7 +24,7 @@ static u32 port_to_devdisr[] = {
 
 static int is_device_disabled(enum fm_port port)
 {
-       ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+       ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
        u32 devdisr2 = in_be32(&gur->devdisr2);
 
        return port_to_devdisr[port] & devdisr2;
@@ -32,7 +32,7 @@ static int is_device_disabled(enum fm_port port)
 
 void fman_disable_port(enum fm_port port)
 {
-       ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+       ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
 
        /* don't allow disabling of DTSEC1 as its needed for MDIO */
        if (port == FM1_DTSEC1)
@@ -43,14 +43,14 @@ void fman_disable_port(enum fm_port port)
 
 void fman_enable_port(enum fm_port port)
 {
-       ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+       ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
 
        clrbits_be32(&gur->devdisr2, port_to_devdisr[port]);
 }
 
 phy_interface_t fman_port_enet_if(enum fm_port port)
 {
-       ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+       ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
        u32 rcwsr11 = in_be32(&gur->rcwsr[11]);
 
        if (is_device_disabled(port))

diff --git a/drivers/net/fm/p5020.c b/drivers/net/fm/p5020.c
index 8ecc482..f931491 100644 (file)
--- a/drivers/net/fm/p5020.c
+++ b/drivers/net/fm/p5020.c
@@ -20,7 +20,7 @@ static u32 port_to_devdisr[] = {
 
 static int is_device_disabled(enum fm_port port)
 {
-       ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+       ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
        u32 devdisr2 = in_be32(&gur->devdisr2);
 
        return port_to_devdisr[port] & devdisr2;
@@ -28,7 +28,7 @@ static int is_device_disabled(enum fm_port port)
 
 void fman_disable_port(enum fm_port port)
 {
-       ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+       ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
 
        /* don't allow disabling of DTSEC1 as its needed for MDIO */
        if (port == FM1_DTSEC1)
@@ -39,14 +39,14 @@ void fman_disable_port(enum fm_port port)
 
 void fman_enable_port(enum fm_port port)
 {
-       ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+       ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
 
        clrbits_be32(&gur->devdisr2, port_to_devdisr[port]);
 }
 
 phy_interface_t fman_port_enet_if(enum fm_port port)
 {
-       ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+       ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
        u32 rcwsr11 = in_be32(&gur->rcwsr[11]);
 
        if (is_device_disabled(port))

diff --git a/drivers/net/fm/p5040.c b/drivers/net/fm/p5040.c
index 3a1494d..ef9f4bc 100644 (file)
--- a/drivers/net/fm/p5040.c
+++ b/drivers/net/fm/p5040.c
@@ -26,7 +26,7 @@ u32 port_to_devdisr[] = {
 
 static int is_device_disabled(enum fm_port port)
 {
-       ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+       ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
        u32 devdisr2 = in_be32(&gur->devdisr2);
 
        return port_to_devdisr[port] & devdisr2;
@@ -34,7 +34,7 @@ static int is_device_disabled(enum fm_port port)
 
 void fman_disable_port(enum fm_port port)
 {
-       ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+       ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
 
        /* don't allow disabling of DTSEC1 as its needed for MDIO */
        if (port == FM1_DTSEC1)
@@ -45,14 +45,14 @@ void fman_disable_port(enum fm_port port)
 
 void fman_enable_port(enum fm_port port)
 {
-       ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+       ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
 
        clrbits_be32(&gur->devdisr2, port_to_devdisr[port]);
 }
 
 phy_interface_t fman_port_enet_if(enum fm_port port)
 {
-       ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+       ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
        u32 rcwsr11 = in_be32(&gur->rcwsr[11]);
 
        if (is_device_disabled(port))

diff --git a/drivers/net/fm/t1024.c b/drivers/net/fm/t1024.c
index 7110fb4..70ab461 100644 (file)
--- a/drivers/net/fm/t1024.c
+++ b/drivers/net/fm/t1024.c
@@ -20,7 +20,7 @@ u32 port_to_devdisr[] = {
 
 static int is_device_disabled(enum fm_port port)
 {
-       ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+       ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR);
        u32 devdisr2 = in_be32(&gur->devdisr2);
 
        return port_to_devdisr[port] & devdisr2;
@@ -28,14 +28,14 @@ static int is_device_disabled(enum fm_port port)
 
 void fman_disable_port(enum fm_port port)
 {
-       ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+       ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR);
 
        setbits_be32(&gur->devdisr2, port_to_devdisr[port]);
 }
 
 phy_interface_t fman_port_enet_if(enum fm_port port)
 {
-       ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+       ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR);
        u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
 
        if (is_device_disabled(port))

diff --git a/drivers/net/fm/t1040.c b/drivers/net/fm/t1040.c
index 192f1c6..5c260be 100644 (file)
--- a/drivers/net/fm/t1040.c
+++ b/drivers/net/fm/t1040.c
@@ -11,7 +11,7 @@
 
 phy_interface_t fman_port_enet_if(enum fm_port port)
 {
-       ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+       ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
        u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
 
        /* handle RGMII first */

diff --git a/drivers/net/fm/t2080.c b/drivers/net/fm/t2080.c
index bfbd8de..6174934 100644 (file)
--- a/drivers/net/fm/t2080.c
+++ b/drivers/net/fm/t2080.c
@@ -28,7 +28,7 @@ u32 port_to_devdisr[] = {
 
 static int is_device_disabled(enum fm_port port)
 {
-       ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+       ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR);
        u32 devdisr2 = in_be32(&gur->devdisr2);
 
        return port_to_devdisr[port] & devdisr2;
@@ -36,14 +36,14 @@ static int is_device_disabled(enum fm_port port)
 
 void fman_disable_port(enum fm_port port)
 {
-       ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+       ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR);
 
        setbits_be32(&gur->devdisr2, port_to_devdisr[port]);
 }
 
 phy_interface_t fman_port_enet_if(enum fm_port port)
 {
-       ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+       ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR);
        u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
 
        if (is_device_disabled(port))

diff --git a/drivers/net/fm/t4240.c b/drivers/net/fm/t4240.c
index ba7b862..f0a02bf 100644 (file)
--- a/drivers/net/fm/t4240.c
+++ b/drivers/net/fm/t4240.c
@@ -35,7 +35,7 @@ u32 port_to_devdisr[] = {
 
 static int is_device_disabled(enum fm_port port)
 {
-       ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+       ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR);
        u32 devdisr2 = in_be32(&gur->devdisr2);
 
        return port_to_devdisr[port] & devdisr2;
@@ -43,21 +43,21 @@ static int is_device_disabled(enum fm_port port)
 
 void fman_disable_port(enum fm_port port)
 {
-       ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+       ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR);
 
        setbits_be32(&gur->devdisr2, port_to_devdisr[port]);
 }
 
 void fman_enable_port(enum fm_port port)
 {
-       ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+       ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR);
 
        clrbits_be32(&gur->devdisr2, port_to_devdisr[port]);
 }
 
 phy_interface_t fman_port_enet_if(enum fm_port port)
 {
-       ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+       ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR);
        u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
 
        if (is_device_disabled(port))

diff --git a/drivers/qe/qe.c b/drivers/qe/qe.c
index 8342c33..2799ef3 100644 (file)
--- a/drivers/qe/qe.c
+++ b/drivers/qe/qe.c
@@ -469,7 +469,7 @@ int qe_upload_firmware(const struct qe_firmware *firmware)
 #ifdef CONFIG_ARCH_LS1021A
        struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
 #else
-       ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+       ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
 #endif
 #endif
        if (!firmware) {
@@ -609,7 +609,7 @@ int u_qe_upload_firmware(const struct qe_firmware *firmware)
 #ifdef CONFIG_ARCH_LS1021A
        struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
 #else
-       ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+       ccsr_gur_t __iomem *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
 #endif
 #endif
        if (!firmware) {
@@ -718,7 +718,7 @@ int u_qe_firmware_resume(const struct qe_firmware *firmware, qe_map_t *qe_immrr)
        const u32 *code;
 #ifdef CONFIG_DEEP_SLEEP
 #ifdef CONFIG_PPC
-       ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+       ccsr_gur_t __iomem *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
 #else
        struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
 #endif

diff --git a/drivers/qe/uec.c b/drivers/qe/uec.c
index c4bd5c4..3108879 100644 (file)
--- a/drivers/qe/uec.c
+++ b/drivers/qe/uec.c
@@ -562,7 +562,7 @@ static void phy_change(struct eth_device *dev)
        struct uec_priv *uec = (struct uec_priv *)dev->priv;
 
 #if defined(CONFIG_ARCH_P1021) || defined(CONFIG_ARCH_P1025)
-       ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+       ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
 
        /* QE9 and QE12 need to be set for enabling QE MII management signals */
        setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE9);
@@ -1194,7 +1194,7 @@ static int uec_init(struct eth_device *dev, struct bd_info *bd)
        int                     err, i;
        struct phy_info         *curphy;
 #if defined(CONFIG_ARCH_P1021) || defined(CONFIG_ARCH_P1025)
-       ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+       ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
 #endif
 
        uec = (struct uec_priv *)dev->priv;

diff --git a/drivers/spi/fsl_espi.c b/drivers/spi/fsl_espi.c
index c7a6926..b1d964d 100644 (file)
--- a/drivers/spi/fsl_espi.c
+++ b/drivers/spi/fsl_espi.c
@@ -390,7 +390,7 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
        if (!fsl)
                return NULL;
 
-       fsl->espi = (void *)(CONFIG_SYS_MPC85xx_ESPI_ADDR);
+       fsl->espi = (void *)(CFG_SYS_MPC85xx_ESPI_ADDR);
        fsl->mode = mode;
        fsl->max_transfer_length = ESPI_MAX_DATA_TRANSFER_LEN;
        fsl->speed_hz = max_hz;

diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h
index f405334..9baab9d 100644 (file)
--- a/include/configs/MPC837XERDB.h
+++ b/include/configs/MPC837XERDB.h
@@ -216,7 +216,7 @@
 
 #ifdef CONFIG_MMC
 #define CONFIG_FSL_ESDHC_PIN_MUX
-#define CONFIG_SYS_FSL_ESDHC_ADDR      CONFIG_SYS_MPC83xx_ESDHC_ADDR
+#define CONFIG_SYS_FSL_ESDHC_ADDR      CFG_SYS_MPC83xx_ESDHC_ADDR
 #endif
 
 /*

diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h
index 2c49326..03b823d 100644 (file)
--- a/include/configs/P1010RDB.h
+++ b/include/configs/P1010RDB.h
@@ -392,7 +392,7 @@ extern unsigned long get_sdram_size(void);
 #endif /* CONFIG_TSEC_ENET */
 
 #ifdef CONFIG_MMC
-#define CONFIG_SYS_FSL_ESDHC_ADDR      CONFIG_SYS_MPC85xx_ESDHC_ADDR
+#define CONFIG_SYS_FSL_ESDHC_ADDR      CFG_SYS_MPC85xx_ESDHC_ADDR
 #endif
 
 /*

diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h
index 991c1a2..42a7b4f 100644 (file)
--- a/include/configs/P2041RDB.h
+++ b/include/configs/P2041RDB.h
@@ -308,7 +308,7 @@
 #endif
 
 #ifdef CONFIG_MMC
-#define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
+#define CONFIG_SYS_FSL_ESDHC_ADDR       CFG_SYS_MPC85xx_ESDHC_ADDR
 #endif
 
 /*

diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h
index ae1a3f1..afc38b4 100644 (file)
--- a/include/configs/T102xRDB.h
+++ b/include/configs/T102xRDB.h
@@ -365,7 +365,7 @@
  * SDHC
  */
 #ifdef CONFIG_MMC
-#define CONFIG_SYS_FSL_ESDHC_ADDR      CONFIG_SYS_MPC85xx_ESDHC_ADDR
+#define CONFIG_SYS_FSL_ESDHC_ADDR      CFG_SYS_MPC85xx_ESDHC_ADDR
 #endif
 
 /* Qman/Bman */

diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h
index 39f6171..d4ffaa4 100644 (file)
--- a/include/configs/T104xRDB.h
+++ b/include/configs/T104xRDB.h
@@ -346,7 +346,7 @@
 */
 
 #ifdef CONFIG_MMC
-#define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
+#define CONFIG_SYS_FSL_ESDHC_ADDR       CFG_SYS_MPC85xx_ESDHC_ADDR
 #endif
 
 /* Qman/Bman */

diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h
index 8b4ce00..6bab631 100644 (file)
--- a/include/configs/T208xQDS.h
+++ b/include/configs/T208xQDS.h
@@ -422,7 +422,7 @@
  * SDHC
  */
 #ifdef CONFIG_MMC
-#define CONFIG_SYS_FSL_ESDHC_ADDR      CONFIG_SYS_MPC85xx_ESDHC_ADDR
+#define CONFIG_SYS_FSL_ESDHC_ADDR      CFG_SYS_MPC85xx_ESDHC_ADDR
 #endif
 
 /*

diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h
index 3f6e687..6e1c6d1 100644 (file)
--- a/include/configs/T208xRDB.h
+++ b/include/configs/T208xRDB.h
@@ -379,7 +379,7 @@
  * SDHC
  */
 #ifdef CONFIG_MMC
-#define CONFIG_SYS_FSL_ESDHC_ADDR      CONFIG_SYS_MPC85xx_ESDHC_ADDR
+#define CONFIG_SYS_FSL_ESDHC_ADDR      CFG_SYS_MPC85xx_ESDHC_ADDR
 #endif
 
 /*

diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h
index b50e18a..35f3e79 100644 (file)
--- a/include/configs/T4240RDB.h
+++ b/include/configs/T4240RDB.h
@@ -382,7 +382,7 @@
 */
 
 #ifdef CONFIG_MMC
-#define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
+#define CONFIG_SYS_FSL_ESDHC_ADDR       CFG_SYS_MPC85xx_ESDHC_ADDR
 #endif
 
 

diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h
index 5366446..82823ca 100644 (file)
--- a/include/configs/p1_p2_rdb_pc.h
+++ b/include/configs/p1_p2_rdb_pc.h
@@ -417,7 +417,7 @@
  */
 
 #ifdef CONFIG_MMC
-#define CONFIG_SYS_FSL_ESDHC_ADDR      CONFIG_SYS_MPC85xx_ESDHC_ADDR
+#define CONFIG_SYS_FSL_ESDHC_ADDR      CFG_SYS_MPC85xx_ESDHC_ADDR
 #endif
 
 /*

diff --git a/include/post.h b/include/post.h
index a07a6bc..ec03556 100644 (file)
--- a/include/post.h
+++ b/include/post.h
@@ -27,7 +27,7 @@
 
 #elif defined (CONFIG_MPC85xx)
 #include <asm/immap_85xx.h>
-#define _POST_WORD_ADDR        (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PIC_OFFSET + \
+#define _POST_WORD_ADDR        (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_PIC_OFFSET + \
                                offsetof(ccsr_pic_t, tfrr))
 #endif