clk: meson: add mpll pre-divider
authorJerome Brunet <jbrunet@baylibre.com>
Mon, 19 Feb 2018 11:21:44 +0000 (12:21 +0100)
committerNeil Armstrong <narmstrong@baylibre.com>
Tue, 13 Mar 2018 09:09:56 +0000 (10:09 +0100)
mpll clocks parent can actually be divided by 1 or 2. So far, this
divider has always been set to 1, so the calculation was correct.
Now that we know it exists, model the tree correctly. If we ever get
a platform where the divider is different, we won't get into trouble

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
drivers/clk/meson/axg.c
drivers/clk/meson/axg.h
drivers/clk/meson/gxbb.c
drivers/clk/meson/gxbb.h
drivers/clk/meson/meson8b.c
drivers/clk/meson/meson8b.h

index ed4a645..2989087 100644 (file)
@@ -354,6 +354,20 @@ static struct clk_fixed_factor axg_fclk_div7 = {
        },
 };
 
+static struct clk_regmap axg_mpll_prediv = {
+       .data = &(struct clk_regmap_div_data){
+               .offset = HHI_MPLL_CNTL5,
+               .shift = 12,
+               .width = 1,
+       },
+       .hw.init = &(struct clk_init_data){
+               .name = "mpll_prediv",
+               .ops = &clk_regmap_divider_ro_ops,
+               .parent_names = (const char *[]){ "fixed_pll" },
+               .num_parents = 1,
+       },
+};
+
 static struct clk_regmap axg_mpll0_div = {
        .data = &(struct meson_clk_mpll_data){
                .sdm = {
@@ -386,7 +400,7 @@ static struct clk_regmap axg_mpll0_div = {
        .hw.init = &(struct clk_init_data){
                .name = "mpll0_div",
                .ops = &meson_clk_mpll_ops,
-               .parent_names = (const char *[]){ "fixed_pll" },
+               .parent_names = (const char *[]){ "mpll_prediv" },
                .num_parents = 1,
        },
 };
@@ -432,7 +446,7 @@ static struct clk_regmap axg_mpll1_div = {
        .hw.init = &(struct clk_init_data){
                .name = "mpll1_div",
                .ops = &meson_clk_mpll_ops,
-               .parent_names = (const char *[]){ "fixed_pll" },
+               .parent_names = (const char *[]){ "mpll_prediv" },
                .num_parents = 1,
        },
 };
@@ -478,7 +492,7 @@ static struct clk_regmap axg_mpll2_div = {
        .hw.init = &(struct clk_init_data){
                .name = "mpll2_div",
                .ops = &meson_clk_mpll_ops,
-               .parent_names = (const char *[]){ "fixed_pll" },
+               .parent_names = (const char *[]){ "mpll_prediv" },
                .num_parents = 1,
        },
 };
@@ -524,7 +538,7 @@ static struct clk_regmap axg_mpll3_div = {
        .hw.init = &(struct clk_init_data){
                .name = "mpll3_div",
                .ops = &meson_clk_mpll_ops,
-               .parent_names = (const char *[]){ "fixed_pll" },
+               .parent_names = (const char *[]){ "mpll_prediv" },
                .num_parents = 1,
        },
 };
@@ -821,6 +835,7 @@ static struct clk_hw_onecell_data axg_hw_onecell_data = {
                [CLKID_MPLL2_DIV]               = &axg_mpll2_div.hw,
                [CLKID_MPLL3_DIV]               = &axg_mpll3_div.hw,
                [CLKID_HIFI_PLL]                = &axg_hifi_pll.hw,
+               [CLKID_MPLL_PREDIV]             = &axg_mpll_prediv.hw,
                [NR_CLKS]                       = NULL,
        },
        .num = NR_CLKS,
@@ -893,6 +908,7 @@ static struct clk_regmap *const axg_clk_regmaps[] = {
        &axg_sys_pll,
        &axg_gp0_pll,
        &axg_hifi_pll,
+       &axg_mpll_prediv,
 };
 
 static const struct of_device_id clkc_match_table[] = {
index 4916c70..6e5dc65 100644 (file)
 #define CLKID_MPLL1_DIV                                66
 #define CLKID_MPLL2_DIV                                67
 #define CLKID_MPLL3_DIV                                68
+#define CLKID_MPLL_PREDIV                      70
 
-#define NR_CLKS                                        70
+#define NR_CLKS                                        71
 
 /* include the CLKIDs that have been made part of the DT binding */
 #include <dt-bindings/clock/axg-clkc.h>
index fdeb372..b62d181 100644 (file)
@@ -545,6 +545,20 @@ static struct clk_fixed_factor gxbb_fclk_div7 = {
        },
 };
 
+static struct clk_regmap gxbb_mpll_prediv = {
+       .data = &(struct clk_regmap_div_data){
+               .offset = HHI_MPLL_CNTL5,
+               .shift = 12,
+               .width = 1,
+       },
+       .hw.init = &(struct clk_init_data){
+               .name = "mpll_prediv",
+               .ops = &clk_regmap_divider_ro_ops,
+               .parent_names = (const char *[]){ "fixed_pll" },
+               .num_parents = 1,
+       },
+};
+
 static struct clk_regmap gxbb_mpll0_div = {
        .data = &(struct meson_clk_mpll_data){
                .sdm = {
@@ -572,7 +586,7 @@ static struct clk_regmap gxbb_mpll0_div = {
        .hw.init = &(struct clk_init_data){
                .name = "mpll0_div",
                .ops = &meson_clk_mpll_ops,
-               .parent_names = (const char *[]){ "fixed_pll" },
+               .parent_names = (const char *[]){ "mpll_prediv" },
                .num_parents = 1,
        },
 };
@@ -613,7 +627,7 @@ static struct clk_regmap gxbb_mpll1_div = {
        .hw.init = &(struct clk_init_data){
                .name = "mpll1_div",
                .ops = &meson_clk_mpll_ops,
-               .parent_names = (const char *[]){ "fixed_pll" },
+               .parent_names = (const char *[]){ "mpll_prediv" },
                .num_parents = 1,
        },
 };
@@ -654,7 +668,7 @@ static struct clk_regmap gxbb_mpll2_div = {
        .hw.init = &(struct clk_init_data){
                .name = "mpll2_div",
                .ops = &meson_clk_mpll_ops,
-               .parent_names = (const char *[]){ "fixed_pll" },
+               .parent_names = (const char *[]){ "mpll_prediv" },
                .num_parents = 1,
        },
 };
@@ -1703,6 +1717,7 @@ static struct clk_hw_onecell_data gxbb_hw_onecell_data = {
                [CLKID_MPLL0_DIV]           = &gxbb_mpll0_div.hw,
                [CLKID_MPLL1_DIV]           = &gxbb_mpll1_div.hw,
                [CLKID_MPLL2_DIV]           = &gxbb_mpll2_div.hw,
+               [CLKID_MPLL_PREDIV]         = &gxbb_mpll_prediv.hw,
                [NR_CLKS]                   = NULL,
        },
        .num = NR_CLKS,
@@ -1853,6 +1868,7 @@ static struct clk_hw_onecell_data gxl_hw_onecell_data = {
                [CLKID_MPLL0_DIV]           = &gxbb_mpll0_div.hw,
                [CLKID_MPLL1_DIV]           = &gxbb_mpll1_div.hw,
                [CLKID_MPLL2_DIV]           = &gxbb_mpll2_div.hw,
+               [CLKID_MPLL_PREDIV]         = &gxbb_mpll_prediv.hw,
                [NR_CLKS]                   = NULL,
        },
        .num = NR_CLKS,
@@ -2005,6 +2021,7 @@ static struct clk_regmap *const gx_clk_regmaps[] = {
        &gxbb_cts_amclk_div,
        &gxbb_fixed_pll,
        &gxbb_sys_pll,
+       &gxbb_mpll_prediv,
 };
 
 struct clkc_data {
index a8e7b88..afae007 100644 (file)
 #define CLKID_MPLL0_DIV                  142
 #define CLKID_MPLL1_DIV                  143
 #define CLKID_MPLL2_DIV                  144
+#define CLKID_MPLL_PREDIV        145
 
-#define NR_CLKS                          145
+#define NR_CLKS                          146
 
 /* include the CLKIDs that have been made part of the DT binding */
 #include <dt-bindings/clock/gxbb-clkc.h>
index 62c54a7..f8b2f23 100644 (file)
@@ -280,6 +280,20 @@ static struct clk_fixed_factor meson8b_fclk_div7 = {
        },
 };
 
+static struct clk_regmap meson8b_mpll_prediv = {
+       .data = &(struct clk_regmap_div_data){
+               .offset = HHI_MPLL_CNTL5,
+               .shift = 12,
+               .width = 1,
+       },
+       .hw.init = &(struct clk_init_data){
+               .name = "mpll_prediv",
+               .ops = &clk_regmap_divider_ro_ops,
+               .parent_names = (const char *[]){ "fixed_pll" },
+               .num_parents = 1,
+       },
+};
+
 static struct clk_regmap meson8b_mpll0_div = {
        .data = &(struct meson_clk_mpll_data){
                .sdm = {
@@ -307,7 +321,7 @@ static struct clk_regmap meson8b_mpll0_div = {
        .hw.init = &(struct clk_init_data){
                .name = "mpll0_div",
                .ops = &meson_clk_mpll_ops,
-               .parent_names = (const char *[]){ "fixed_pll" },
+               .parent_names = (const char *[]){ "mpll_prediv" },
                .num_parents = 1,
        },
 };
@@ -348,7 +362,7 @@ static struct clk_regmap meson8b_mpll1_div = {
        .hw.init = &(struct clk_init_data){
                .name = "mpll1_div",
                .ops = &meson_clk_mpll_ops,
-               .parent_names = (const char *[]){ "fixed_pll" },
+               .parent_names = (const char *[]){ "mpll_prediv" },
                .num_parents = 1,
        },
 };
@@ -389,7 +403,7 @@ static struct clk_regmap meson8b_mpll2_div = {
        .hw.init = &(struct clk_init_data){
                .name = "mpll2_div",
                .ops = &meson_clk_mpll_ops,
-               .parent_names = (const char *[]){ "fixed_pll" },
+               .parent_names = (const char *[]){ "mpll_prediv" },
                .num_parents = 1,
        },
 };
@@ -751,6 +765,7 @@ static struct clk_hw_onecell_data meson8b_hw_onecell_data = {
                [CLKID_CPU_DIV3]            = &meson8b_cpu_div3.hw,
                [CLKID_CPU_SCALE_DIV]       = &meson8b_cpu_scale_div.hw,
                [CLKID_CPU_SCALE_OUT_SEL]   = &meson8b_cpu_scale_out_sel.hw,
+               [CLKID_MPLL_PREDIV]         = &meson8b_mpll_prediv.hw,
                [CLK_NR_CLKS]               = NULL,
        },
        .num = CLK_NR_CLKS,
@@ -850,6 +865,7 @@ static struct clk_regmap *const meson8b_clk_regmaps[] = {
        &meson8b_cpu_scale_div,
        &meson8b_cpu_scale_out_sel,
        &meson8b_cpu_clk,
+       &meson8b_mpll_prediv,
 };
 
 static const struct meson8b_clk_reset_line {
index 73dae83..839ffc9 100644 (file)
@@ -77,8 +77,9 @@
 #define CLKID_CPU_DIV3         101
 #define CLKID_CPU_SCALE_DIV    102
 #define CLKID_CPU_SCALE_OUT_SEL        103
+#define CLKID_MPLL_PREDIV      104
 
-#define CLK_NR_CLKS            104
+#define CLK_NR_CLKS            105
 
 /*
  * include the CLKID and RESETID that have