assert(MO.getReg() > PPC::NoRegister &&
MO.getReg() < PPC::NUM_TARGET_REGS &&
"Invalid register for this target!");
+ // Ignore all implicit register operands.
+ if (MO.isImplicit())
+ return false;
OutMO = MCOperand::createReg(MO.getReg());
return true;
case MachineOperand::MO_Immediate:
renamable $cr5lt = CRNOR renamable $cr0lt, renamable $cr1gt, implicit killed $cr0
renamable $cr5gt = COPY renamable $cr1gt, implicit $cr1
; CHECK: crnor 4*cr5+lt, lt, 4*cr1+gt
- ; CHECK: cror 4*cr5+gt, 4*cr1+gt, 4*cr1+gt
+ ; CHECK: crmove 4*cr5+gt, 4*cr1+gt
SPILL_CRBIT killed renamable $cr5lt, 0, %stack.0 :: (store 4 into %stack.0)
renamable $cr1 = CMPW renamable $r4, renamable $r5, implicit killed $x5, implicit killed $x4
SPILL_CRBIT killed renamable $cr5gt, 0, %stack.1 :: (store 4 into %stack.1)
define void @test40(i8* %ptr, i8 %cmp, i8 %val) {
; PPC64LE-LABEL: test40:
; PPC64LE: # %bb.0:
-; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31
+; PPC64LE-NEXT: clrlwi 4, 4, 24
; PPC64LE-NEXT: .LBB40_1:
; PPC64LE-NEXT: lbarx 6, 0, 3
; PPC64LE-NEXT: cmpw 4, 6
define void @test41(i8* %ptr, i8 %cmp, i8 %val) {
; PPC64LE-LABEL: test41:
; PPC64LE: # %bb.0:
-; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31
+; PPC64LE-NEXT: clrlwi 4, 4, 24
; PPC64LE-NEXT: .LBB41_1:
; PPC64LE-NEXT: lbarx 6, 0, 3
; PPC64LE-NEXT: cmpw 4, 6
define void @test42(i8* %ptr, i8 %cmp, i8 %val) {
; PPC64LE-LABEL: test42:
; PPC64LE: # %bb.0:
-; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31
+; PPC64LE-NEXT: clrlwi 4, 4, 24
; PPC64LE-NEXT: .LBB42_1:
; PPC64LE-NEXT: lbarx 6, 0, 3
; PPC64LE-NEXT: cmpw 4, 6
define void @test43(i8* %ptr, i8 %cmp, i8 %val) {
; PPC64LE-LABEL: test43:
; PPC64LE: # %bb.0:
-; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31
+; PPC64LE-NEXT: clrlwi 4, 4, 24
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB43_1:
; PPC64LE-NEXT: lbarx 6, 0, 3
define void @test44(i8* %ptr, i8 %cmp, i8 %val) {
; PPC64LE-LABEL: test44:
; PPC64LE: # %bb.0:
-; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31
+; PPC64LE-NEXT: clrlwi 4, 4, 24
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB44_1:
; PPC64LE-NEXT: lbarx 6, 0, 3
define void @test45(i8* %ptr, i8 %cmp, i8 %val) {
; PPC64LE-LABEL: test45:
; PPC64LE: # %bb.0:
-; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31
+; PPC64LE-NEXT: clrlwi 4, 4, 24
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB45_1:
; PPC64LE-NEXT: lbarx 6, 0, 3
define void @test46(i8* %ptr, i8 %cmp, i8 %val) {
; PPC64LE-LABEL: test46:
; PPC64LE: # %bb.0:
-; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31
+; PPC64LE-NEXT: clrlwi 4, 4, 24
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB46_1:
; PPC64LE-NEXT: lbarx 6, 0, 3
define void @test47(i8* %ptr, i8 %cmp, i8 %val) {
; PPC64LE-LABEL: test47:
; PPC64LE: # %bb.0:
-; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31
+; PPC64LE-NEXT: clrlwi 4, 4, 24
; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB47_1:
; PPC64LE-NEXT: lbarx 6, 0, 3
define void @test48(i8* %ptr, i8 %cmp, i8 %val) {
; PPC64LE-LABEL: test48:
; PPC64LE: # %bb.0:
-; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31
+; PPC64LE-NEXT: clrlwi 4, 4, 24
; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB48_1:
; PPC64LE-NEXT: lbarx 6, 0, 3
define void @test49(i8* %ptr, i8 %cmp, i8 %val) {
; PPC64LE-LABEL: test49:
; PPC64LE: # %bb.0:
-; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31
+; PPC64LE-NEXT: clrlwi 4, 4, 24
; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB49_1:
; PPC64LE-NEXT: lbarx 6, 0, 3
define void @test50(i16* %ptr, i16 %cmp, i16 %val) {
; PPC64LE-LABEL: test50:
; PPC64LE: # %bb.0:
-; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31
+; PPC64LE-NEXT: clrlwi 4, 4, 16
; PPC64LE-NEXT: .LBB50_1:
; PPC64LE-NEXT: lharx 6, 0, 3
; PPC64LE-NEXT: cmpw 4, 6
define void @test51(i16* %ptr, i16 %cmp, i16 %val) {
; PPC64LE-LABEL: test51:
; PPC64LE: # %bb.0:
-; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31
+; PPC64LE-NEXT: clrlwi 4, 4, 16
; PPC64LE-NEXT: .LBB51_1:
; PPC64LE-NEXT: lharx 6, 0, 3
; PPC64LE-NEXT: cmpw 4, 6
define void @test52(i16* %ptr, i16 %cmp, i16 %val) {
; PPC64LE-LABEL: test52:
; PPC64LE: # %bb.0:
-; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31
+; PPC64LE-NEXT: clrlwi 4, 4, 16
; PPC64LE-NEXT: .LBB52_1:
; PPC64LE-NEXT: lharx 6, 0, 3
; PPC64LE-NEXT: cmpw 4, 6
define void @test53(i16* %ptr, i16 %cmp, i16 %val) {
; PPC64LE-LABEL: test53:
; PPC64LE: # %bb.0:
-; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31
+; PPC64LE-NEXT: clrlwi 4, 4, 16
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB53_1:
; PPC64LE-NEXT: lharx 6, 0, 3
define void @test54(i16* %ptr, i16 %cmp, i16 %val) {
; PPC64LE-LABEL: test54:
; PPC64LE: # %bb.0:
-; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31
+; PPC64LE-NEXT: clrlwi 4, 4, 16
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB54_1:
; PPC64LE-NEXT: lharx 6, 0, 3
define void @test55(i16* %ptr, i16 %cmp, i16 %val) {
; PPC64LE-LABEL: test55:
; PPC64LE: # %bb.0:
-; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31
+; PPC64LE-NEXT: clrlwi 4, 4, 16
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB55_1:
; PPC64LE-NEXT: lharx 6, 0, 3
define void @test56(i16* %ptr, i16 %cmp, i16 %val) {
; PPC64LE-LABEL: test56:
; PPC64LE: # %bb.0:
-; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31
+; PPC64LE-NEXT: clrlwi 4, 4, 16
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB56_1:
; PPC64LE-NEXT: lharx 6, 0, 3
define void @test57(i16* %ptr, i16 %cmp, i16 %val) {
; PPC64LE-LABEL: test57:
; PPC64LE: # %bb.0:
-; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31
+; PPC64LE-NEXT: clrlwi 4, 4, 16
; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB57_1:
; PPC64LE-NEXT: lharx 6, 0, 3
define void @test58(i16* %ptr, i16 %cmp, i16 %val) {
; PPC64LE-LABEL: test58:
; PPC64LE: # %bb.0:
-; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31
+; PPC64LE-NEXT: clrlwi 4, 4, 16
; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB58_1:
; PPC64LE-NEXT: lharx 6, 0, 3
define void @test59(i16* %ptr, i16 %cmp, i16 %val) {
; PPC64LE-LABEL: test59:
; PPC64LE: # %bb.0:
-; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31
+; PPC64LE-NEXT: clrlwi 4, 4, 16
; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB59_1:
; PPC64LE-NEXT: lharx 6, 0, 3
define void @test80(i8* %ptr, i8 %cmp, i8 %val) {
; PPC64LE-LABEL: test80:
; PPC64LE: # %bb.0:
-; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31
+; PPC64LE-NEXT: clrlwi 4, 4, 24
; PPC64LE-NEXT: .LBB80_1:
; PPC64LE-NEXT: lbarx 6, 0, 3
; PPC64LE-NEXT: cmpw 4, 6
define void @test81(i8* %ptr, i8 %cmp, i8 %val) {
; PPC64LE-LABEL: test81:
; PPC64LE: # %bb.0:
-; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31
+; PPC64LE-NEXT: clrlwi 4, 4, 24
; PPC64LE-NEXT: .LBB81_1:
; PPC64LE-NEXT: lbarx 6, 0, 3
; PPC64LE-NEXT: cmpw 4, 6
define void @test82(i8* %ptr, i8 %cmp, i8 %val) {
; PPC64LE-LABEL: test82:
; PPC64LE: # %bb.0:
-; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31
+; PPC64LE-NEXT: clrlwi 4, 4, 24
; PPC64LE-NEXT: .LBB82_1:
; PPC64LE-NEXT: lbarx 6, 0, 3
; PPC64LE-NEXT: cmpw 4, 6
define void @test83(i8* %ptr, i8 %cmp, i8 %val) {
; PPC64LE-LABEL: test83:
; PPC64LE: # %bb.0:
-; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31
+; PPC64LE-NEXT: clrlwi 4, 4, 24
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB83_1:
; PPC64LE-NEXT: lbarx 6, 0, 3
define void @test84(i8* %ptr, i8 %cmp, i8 %val) {
; PPC64LE-LABEL: test84:
; PPC64LE: # %bb.0:
-; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31
+; PPC64LE-NEXT: clrlwi 4, 4, 24
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB84_1:
; PPC64LE-NEXT: lbarx 6, 0, 3
define void @test85(i8* %ptr, i8 %cmp, i8 %val) {
; PPC64LE-LABEL: test85:
; PPC64LE: # %bb.0:
-; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31
+; PPC64LE-NEXT: clrlwi 4, 4, 24
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB85_1:
; PPC64LE-NEXT: lbarx 6, 0, 3
define void @test86(i8* %ptr, i8 %cmp, i8 %val) {
; PPC64LE-LABEL: test86:
; PPC64LE: # %bb.0:
-; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31
+; PPC64LE-NEXT: clrlwi 4, 4, 24
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB86_1:
; PPC64LE-NEXT: lbarx 6, 0, 3
define void @test87(i8* %ptr, i8 %cmp, i8 %val) {
; PPC64LE-LABEL: test87:
; PPC64LE: # %bb.0:
-; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31
+; PPC64LE-NEXT: clrlwi 4, 4, 24
; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB87_1:
; PPC64LE-NEXT: lbarx 6, 0, 3
define void @test88(i8* %ptr, i8 %cmp, i8 %val) {
; PPC64LE-LABEL: test88:
; PPC64LE: # %bb.0:
-; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31
+; PPC64LE-NEXT: clrlwi 4, 4, 24
; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB88_1:
; PPC64LE-NEXT: lbarx 6, 0, 3
define void @test89(i8* %ptr, i8 %cmp, i8 %val) {
; PPC64LE-LABEL: test89:
; PPC64LE: # %bb.0:
-; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31
+; PPC64LE-NEXT: clrlwi 4, 4, 24
; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB89_1:
; PPC64LE-NEXT: lbarx 6, 0, 3
define void @test90(i16* %ptr, i16 %cmp, i16 %val) {
; PPC64LE-LABEL: test90:
; PPC64LE: # %bb.0:
-; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31
+; PPC64LE-NEXT: clrlwi 4, 4, 16
; PPC64LE-NEXT: .LBB90_1:
; PPC64LE-NEXT: lharx 6, 0, 3
; PPC64LE-NEXT: cmpw 4, 6
define void @test91(i16* %ptr, i16 %cmp, i16 %val) {
; PPC64LE-LABEL: test91:
; PPC64LE: # %bb.0:
-; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31
+; PPC64LE-NEXT: clrlwi 4, 4, 16
; PPC64LE-NEXT: .LBB91_1:
; PPC64LE-NEXT: lharx 6, 0, 3
; PPC64LE-NEXT: cmpw 4, 6
define void @test92(i16* %ptr, i16 %cmp, i16 %val) {
; PPC64LE-LABEL: test92:
; PPC64LE: # %bb.0:
-; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31
+; PPC64LE-NEXT: clrlwi 4, 4, 16
; PPC64LE-NEXT: .LBB92_1:
; PPC64LE-NEXT: lharx 6, 0, 3
; PPC64LE-NEXT: cmpw 4, 6
define void @test93(i16* %ptr, i16 %cmp, i16 %val) {
; PPC64LE-LABEL: test93:
; PPC64LE: # %bb.0:
-; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31
+; PPC64LE-NEXT: clrlwi 4, 4, 16
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB93_1:
; PPC64LE-NEXT: lharx 6, 0, 3
define void @test94(i16* %ptr, i16 %cmp, i16 %val) {
; PPC64LE-LABEL: test94:
; PPC64LE: # %bb.0:
-; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31
+; PPC64LE-NEXT: clrlwi 4, 4, 16
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB94_1:
; PPC64LE-NEXT: lharx 6, 0, 3
define void @test95(i16* %ptr, i16 %cmp, i16 %val) {
; PPC64LE-LABEL: test95:
; PPC64LE: # %bb.0:
-; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31
+; PPC64LE-NEXT: clrlwi 4, 4, 16
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB95_1:
; PPC64LE-NEXT: lharx 6, 0, 3
define void @test96(i16* %ptr, i16 %cmp, i16 %val) {
; PPC64LE-LABEL: test96:
; PPC64LE: # %bb.0:
-; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31
+; PPC64LE-NEXT: clrlwi 4, 4, 16
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB96_1:
; PPC64LE-NEXT: lharx 6, 0, 3
define void @test97(i16* %ptr, i16 %cmp, i16 %val) {
; PPC64LE-LABEL: test97:
; PPC64LE: # %bb.0:
-; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31
+; PPC64LE-NEXT: clrlwi 4, 4, 16
; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB97_1:
; PPC64LE-NEXT: lharx 6, 0, 3
define void @test98(i16* %ptr, i16 %cmp, i16 %val) {
; PPC64LE-LABEL: test98:
; PPC64LE: # %bb.0:
-; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31
+; PPC64LE-NEXT: clrlwi 4, 4, 16
; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB98_1:
; PPC64LE-NEXT: lharx 6, 0, 3
define void @test99(i16* %ptr, i16 %cmp, i16 %val) {
; PPC64LE-LABEL: test99:
; PPC64LE: # %bb.0:
-; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31
+; PPC64LE-NEXT: clrlwi 4, 4, 16
; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB99_1:
; PPC64LE-NEXT: lharx 6, 0, 3
; CHECK-P7: lwa 3,
; CHECK: xscvdpspn [[CONVREG:[0-9]+]], 1
; CHECK: xxsldwi [[SHIFTREG:[0-9]+]], [[CONVREG]], [[CONVREG]], 3
-; CHECK: mfvsrwz 3, [[SHIFTREG]]
+; CHECK: mffprwz 3, [[SHIFTREG]]
}
define i64 @f64toi64(double %a) {
ret float %0
; CHECK-P7: stw 3,
; CHECK-P7: lfs 1,
-; CHECK: mtvsrd [[MOVEREG:[0-9]+]], 3
+; CHECK: mtfprd [[MOVEREG:[0-9]+]], 3
; CHECK: xxsldwi [[SHIFTREG:[0-9]+]], [[MOVEREG]], [[MOVEREG]], 1
; CHECK: xscvspdpn 1, [[SHIFTREG]]
}
; CHECK-P7: lwz 3,
; CHECK: xscvdpspn [[CONVREG:[0-9]+]], 1
; CHECK: xxsldwi [[SHIFTREG:[0-9]+]], [[CONVREG]], [[CONVREG]], 3
-; CHECK: mfvsrwz 3, [[SHIFTREG]]
+; CHECK: mffprwz 3, [[SHIFTREG]]
}
define i64 @f64toi64u(double %a) {
ret float %0
; CHECK-P7: stw 3,
; CHECK-P7: lfs 1,
-; CHECK: mtvsrd [[MOVEREG:[0-9]+]], 3
+; CHECK: mtfprd [[MOVEREG:[0-9]+]], 3
; CHECK: xxsldwi [[SHIFTREG:[0-9]+]], [[MOVEREG]], [[MOVEREG]], 1
; CHECK: xscvspdpn 1, [[SHIFTREG]]
}
define i8 @add_zext_cmp_mask_same_size_result(i8 %x) {
; CHECK-LABEL: add_zext_cmp_mask_same_size_result:
; CHECK: # %bb.0:
-; CHECK-NEXT: rlwinm 3, 3, 0, 31, 31
+; CHECK-NEXT: clrlwi 3, 3, 31
; CHECK-NEXT: subfic 3, 3, 27
; CHECK-NEXT: blr
%a = and i8 %x, 1
define i32 @add_zext_cmp_mask_wider_result(i8 %x) {
; CHECK-LABEL: add_zext_cmp_mask_wider_result:
; CHECK: # %bb.0:
-; CHECK-NEXT: rlwinm 3, 3, 0, 31, 31
+; CHECK-NEXT: clrlwi 3, 3, 31
; CHECK-NEXT: subfic 3, 3, 27
; CHECK-NEXT: blr
%a = and i8 %x, 1
define i8 @add_zext_cmp_mask_narrower_result(i32 %x) {
; CHECK-LABEL: add_zext_cmp_mask_narrower_result:
; CHECK: # %bb.0:
-; CHECK-NEXT: rlwinm 3, 3, 0, 31, 31
+; CHECK-NEXT: clrlwi 3, 3, 31
; CHECK-NEXT: subfic 3, 3, 43
; CHECK-NEXT: blr
%a = and i32 %x, 1
define double @testBranchCoal(double %a, double %b, double %c, i32 %x) {
; CHECK-LABEL: @testBranchCoal
-; CHECK: cmplwi [[CMPR:[0-7]+]], 6, 0
-; CHECK: beq [[CMPR]], .LBB[[LAB1:[0-9_]+]]
+; CHECK: cmplwi 6, 0
+; CHECK: beq 0, .LBB[[LAB1:[0-9_]+]]
; CHECK-DAG: addis [[LD1REG:[0-9]+]], 2, .LCPI0_0@toc@ha
; CHECK-DAG: addis [[LD2REG:[0-9]+]], 2, .LCPI0_1@toc@ha
; CHECK-DAG: xxlxor 2, 2, 2
; CHECK-NOCOALESCE-LABEL: testBranchCoal:
; CHECK-NOCOALESCE: # %bb.0: # %entry
-; CHECK-NOCOALESCE-NEXT: cmplwi 0, 6, 0
+; CHECK-NOCOALESCE-NEXT: cmplwi 6, 0
; CHECK-NOCOALESCE-NEXT: bne 0, .LBB0_5
; CHECK-NOCOALESCE-NEXT: # %bb.1: # %entry
; CHECK-NOCOALESCE-NEXT: bne 0, .LBB0_6
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mtvsrdd 34, 3, 3
; CHECK-NEXT: xxbrd 0, 34
-; CHECK-NEXT: mfvsrd 3, 0
+; CHECK-NEXT: mffprd 3, 0
; CHECK-NEXT: blr
;
; NO-ALTIVEC-LABEL: bswap64:
; P8BE: # %bb.0: # %entry
; P8BE-NEXT: rldimi r6, r5, 32, 0
; P8BE-NEXT: rldimi r4, r3, 32, 0
-; P8BE-NEXT: mtvsrd f0, r6
-; P8BE-NEXT: mtvsrd f1, r4
+; P8BE-NEXT: mtfprd f0, r6
+; P8BE-NEXT: mtfprd f1, r4
; P8BE-NEXT: xxmrghd v2, vs1, vs0
; P8BE-NEXT: blr
;
; P8LE: # %bb.0: # %entry
; P8LE-NEXT: rldimi r3, r4, 32, 0
; P8LE-NEXT: rldimi r5, r6, 32, 0
-; P8LE-NEXT: mtvsrd f0, r3
-; P8LE-NEXT: mtvsrd f1, r5
+; P8LE-NEXT: mtfprd f0, r3
+; P8LE-NEXT: mtfprd f1, r5
; P8LE-NEXT: xxmrghd v2, vs1, vs0
; P8LE-NEXT: blr
entry:
; P8BE-NEXT: lwz r3, 72(r3)
; P8BE-NEXT: rldimi r5, r4, 32, 0
; P8BE-NEXT: rldimi r3, r6, 32, 0
-; P8BE-NEXT: mtvsrd f0, r5
-; P8BE-NEXT: mtvsrd f1, r3
+; P8BE-NEXT: mtfprd f0, r5
+; P8BE-NEXT: mtfprd f1, r3
; P8BE-NEXT: xxmrghd v2, vs1, vs0
; P8BE-NEXT: blr
;
; P8LE-NEXT: lwz r3, 352(r3)
; P8LE-NEXT: rldimi r4, r5, 32, 0
; P8LE-NEXT: rldimi r6, r3, 32, 0
-; P8LE-NEXT: mtvsrd f0, r4
-; P8LE-NEXT: mtvsrd f1, r6
+; P8LE-NEXT: mtfprd f0, r4
+; P8LE-NEXT: mtfprd f1, r6
; P8LE-NEXT: xxmrghd v2, vs1, vs0
; P8LE-NEXT: blr
entry:
; P8BE-NEXT: lwz r3, 4(r3)
; P8BE-NEXT: rldimi r5, r4, 32, 0
; P8BE-NEXT: rldimi r3, r6, 32, 0
-; P8BE-NEXT: mtvsrd f0, r5
-; P8BE-NEXT: mtvsrd f1, r3
+; P8BE-NEXT: mtfprd f0, r5
+; P8BE-NEXT: mtfprd f1, r3
; P8BE-NEXT: xxmrghd v2, vs1, vs0
; P8BE-NEXT: blr
;
; P8LE-NEXT: lwz r3, 32(r3)
; P8LE-NEXT: rldimi r4, r5, 32, 0
; P8LE-NEXT: rldimi r6, r3, 32, 0
-; P8LE-NEXT: mtvsrd f0, r4
-; P8LE-NEXT: mtvsrd f1, r6
+; P8LE-NEXT: mtfprd f0, r4
+; P8LE-NEXT: mtfprd f1, r6
; P8LE-NEXT: xxmrghd v2, vs1, vs0
; P8LE-NEXT: blr
entry:
;
; P8BE-LABEL: spltRegVali:
; P8BE: # %bb.0: # %entry
-; P8BE-NEXT: mtvsrwz f0, r3
+; P8BE-NEXT: mtfprwz f0, r3
; P8BE-NEXT: xxspltw v2, vs0, 1
; P8BE-NEXT: blr
;
; P8LE-LABEL: spltRegVali:
; P8LE: # %bb.0: # %entry
-; P8LE-NEXT: mtvsrwz f0, r3
+; P8LE-NEXT: mtfprwz f0, r3
; P8LE-NEXT: xxspltw v2, vs0, 1
; P8LE-NEXT: blr
entry:
; P8BE: # %bb.0: # %entry
; P8BE-NEXT: rldimi r6, r5, 32, 0
; P8BE-NEXT: rldimi r4, r3, 32, 0
-; P8BE-NEXT: mtvsrd f0, r6
-; P8BE-NEXT: mtvsrd f1, r4
+; P8BE-NEXT: mtfprd f0, r6
+; P8BE-NEXT: mtfprd f1, r4
; P8BE-NEXT: xxmrghd v2, vs1, vs0
; P8BE-NEXT: blr
;
; P8LE: # %bb.0: # %entry
; P8LE-NEXT: rldimi r3, r4, 32, 0
; P8LE-NEXT: rldimi r5, r6, 32, 0
-; P8LE-NEXT: mtvsrd f0, r3
-; P8LE-NEXT: mtvsrd f1, r5
+; P8LE-NEXT: mtfprd f0, r3
+; P8LE-NEXT: mtfprd f1, r5
; P8LE-NEXT: xxmrghd v2, vs1, vs0
; P8LE-NEXT: blr
entry:
; P8BE-NEXT: lwz r3, 72(r3)
; P8BE-NEXT: rldimi r5, r4, 32, 0
; P8BE-NEXT: rldimi r3, r6, 32, 0
-; P8BE-NEXT: mtvsrd f0, r5
-; P8BE-NEXT: mtvsrd f1, r3
+; P8BE-NEXT: mtfprd f0, r5
+; P8BE-NEXT: mtfprd f1, r3
; P8BE-NEXT: xxmrghd v2, vs1, vs0
; P8BE-NEXT: blr
;
; P8LE-NEXT: lwz r3, 352(r3)
; P8LE-NEXT: rldimi r4, r5, 32, 0
; P8LE-NEXT: rldimi r6, r3, 32, 0
-; P8LE-NEXT: mtvsrd f0, r4
-; P8LE-NEXT: mtvsrd f1, r6
+; P8LE-NEXT: mtfprd f0, r4
+; P8LE-NEXT: mtfprd f1, r6
; P8LE-NEXT: xxmrghd v2, vs1, vs0
; P8LE-NEXT: blr
entry:
; P8BE-NEXT: lwz r3, 4(r3)
; P8BE-NEXT: rldimi r5, r4, 32, 0
; P8BE-NEXT: rldimi r3, r6, 32, 0
-; P8BE-NEXT: mtvsrd f0, r5
-; P8BE-NEXT: mtvsrd f1, r3
+; P8BE-NEXT: mtfprd f0, r5
+; P8BE-NEXT: mtfprd f1, r3
; P8BE-NEXT: xxmrghd v2, vs1, vs0
; P8BE-NEXT: blr
;
; P8LE-NEXT: lwz r3, 32(r3)
; P8LE-NEXT: rldimi r4, r5, 32, 0
; P8LE-NEXT: rldimi r6, r3, 32, 0
-; P8LE-NEXT: mtvsrd f0, r4
-; P8LE-NEXT: mtvsrd f1, r6
+; P8LE-NEXT: mtfprd f0, r4
+; P8LE-NEXT: mtfprd f1, r6
; P8LE-NEXT: xxmrghd v2, vs1, vs0
; P8LE-NEXT: blr
entry:
;
; P8BE-LABEL: spltRegValui:
; P8BE: # %bb.0: # %entry
-; P8BE-NEXT: mtvsrwz f0, r3
+; P8BE-NEXT: mtfprwz f0, r3
; P8BE-NEXT: xxspltw v2, vs0, 1
; P8BE-NEXT: blr
;
; P8LE-LABEL: spltRegValui:
; P8LE: # %bb.0: # %entry
-; P8LE-NEXT: mtvsrwz f0, r3
+; P8LE-NEXT: mtfprwz f0, r3
; P8LE-NEXT: xxspltw v2, vs0, 1
; P8LE-NEXT: blr
entry:
;
; P8BE-LABEL: fromRegsll:
; P8BE: # %bb.0: # %entry
-; P8BE-NEXT: mtvsrd f0, r4
-; P8BE-NEXT: mtvsrd f1, r3
+; P8BE-NEXT: mtfprd f0, r4
+; P8BE-NEXT: mtfprd f1, r3
; P8BE-NEXT: xxmrghd v2, vs1, vs0
; P8BE-NEXT: blr
;
; P8LE-LABEL: fromRegsll:
; P8LE: # %bb.0: # %entry
-; P8LE-NEXT: mtvsrd f0, r3
-; P8LE-NEXT: mtvsrd f1, r4
+; P8LE-NEXT: mtfprd f0, r3
+; P8LE-NEXT: mtfprd f1, r4
; P8LE-NEXT: xxmrghd v2, vs1, vs0
; P8LE-NEXT: blr
entry:
; P8BE: # %bb.0: # %entry
; P8BE-NEXT: ld r4, 144(r3)
; P8BE-NEXT: ld r3, 32(r3)
-; P8BE-NEXT: mtvsrd f0, r4
-; P8BE-NEXT: mtvsrd f1, r3
+; P8BE-NEXT: mtfprd f0, r4
+; P8BE-NEXT: mtfprd f1, r3
; P8BE-NEXT: xxmrghd v2, vs1, vs0
; P8BE-NEXT: blr
;
; P8LE: # %bb.0: # %entry
; P8LE-NEXT: ld r4, 32(r3)
; P8LE-NEXT: ld r3, 144(r3)
-; P8LE-NEXT: mtvsrd f0, r4
-; P8LE-NEXT: mtvsrd f1, r3
+; P8LE-NEXT: mtfprd f0, r4
+; P8LE-NEXT: mtfprd f1, r3
; P8LE-NEXT: xxmrghd v2, vs1, vs0
; P8LE-NEXT: blr
entry:
; P8BE-NEXT: add r3, r3, r4
; P8BE-NEXT: ld r4, 8(r3)
; P8BE-NEXT: ld r3, 32(r3)
-; P8BE-NEXT: mtvsrd f0, r4
-; P8BE-NEXT: mtvsrd f1, r3
+; P8BE-NEXT: mtfprd f0, r4
+; P8BE-NEXT: mtfprd f1, r3
; P8BE-NEXT: xxmrghd v2, vs1, vs0
; P8BE-NEXT: blr
;
; P8LE-NEXT: add r3, r3, r4
; P8LE-NEXT: ld r4, 32(r3)
; P8LE-NEXT: ld r3, 8(r3)
-; P8LE-NEXT: mtvsrd f0, r4
-; P8LE-NEXT: mtvsrd f1, r3
+; P8LE-NEXT: mtfprd f0, r4
+; P8LE-NEXT: mtfprd f1, r3
; P8LE-NEXT: xxmrghd v2, vs1, vs0
; P8LE-NEXT: blr
entry:
;
; P8BE-LABEL: spltRegValll:
; P8BE: # %bb.0: # %entry
-; P8BE-NEXT: mtvsrd f0, r3
+; P8BE-NEXT: mtfprd f0, r3
; P8BE-NEXT: xxspltd v2, vs0, 0
; P8BE-NEXT: blr
;
; P8LE-LABEL: spltRegValll:
; P8LE: # %bb.0: # %entry
-; P8LE-NEXT: mtvsrd f0, r3
+; P8LE-NEXT: mtfprd f0, r3
; P8LE-NEXT: xxspltd v2, vs0, 0
; P8LE-NEXT: blr
entry:
;
; P8BE-LABEL: fromRegsull:
; P8BE: # %bb.0: # %entry
-; P8BE-NEXT: mtvsrd f0, r4
-; P8BE-NEXT: mtvsrd f1, r3
+; P8BE-NEXT: mtfprd f0, r4
+; P8BE-NEXT: mtfprd f1, r3
; P8BE-NEXT: xxmrghd v2, vs1, vs0
; P8BE-NEXT: blr
;
; P8LE-LABEL: fromRegsull:
; P8LE: # %bb.0: # %entry
-; P8LE-NEXT: mtvsrd f0, r3
-; P8LE-NEXT: mtvsrd f1, r4
+; P8LE-NEXT: mtfprd f0, r3
+; P8LE-NEXT: mtfprd f1, r4
; P8LE-NEXT: xxmrghd v2, vs1, vs0
; P8LE-NEXT: blr
entry:
; P8BE: # %bb.0: # %entry
; P8BE-NEXT: ld r4, 144(r3)
; P8BE-NEXT: ld r3, 32(r3)
-; P8BE-NEXT: mtvsrd f0, r4
-; P8BE-NEXT: mtvsrd f1, r3
+; P8BE-NEXT: mtfprd f0, r4
+; P8BE-NEXT: mtfprd f1, r3
; P8BE-NEXT: xxmrghd v2, vs1, vs0
; P8BE-NEXT: blr
;
; P8LE: # %bb.0: # %entry
; P8LE-NEXT: ld r4, 32(r3)
; P8LE-NEXT: ld r3, 144(r3)
-; P8LE-NEXT: mtvsrd f0, r4
-; P8LE-NEXT: mtvsrd f1, r3
+; P8LE-NEXT: mtfprd f0, r4
+; P8LE-NEXT: mtfprd f1, r3
; P8LE-NEXT: xxmrghd v2, vs1, vs0
; P8LE-NEXT: blr
entry:
; P8BE-NEXT: add r3, r3, r4
; P8BE-NEXT: ld r4, 8(r3)
; P8BE-NEXT: ld r3, 32(r3)
-; P8BE-NEXT: mtvsrd f0, r4
-; P8BE-NEXT: mtvsrd f1, r3
+; P8BE-NEXT: mtfprd f0, r4
+; P8BE-NEXT: mtfprd f1, r3
; P8BE-NEXT: xxmrghd v2, vs1, vs0
; P8BE-NEXT: blr
;
; P8LE-NEXT: add r3, r3, r4
; P8LE-NEXT: ld r4, 32(r3)
; P8LE-NEXT: ld r3, 8(r3)
-; P8LE-NEXT: mtvsrd f0, r4
-; P8LE-NEXT: mtvsrd f1, r3
+; P8LE-NEXT: mtfprd f0, r4
+; P8LE-NEXT: mtfprd f1, r3
; P8LE-NEXT: xxmrghd v2, vs1, vs0
; P8LE-NEXT: blr
entry:
;
; P8BE-LABEL: spltRegValull:
; P8BE: # %bb.0: # %entry
-; P8BE-NEXT: mtvsrd f0, r3
+; P8BE-NEXT: mtfprd f0, r3
; P8BE-NEXT: xxspltd v2, vs0, 0
; P8BE-NEXT: blr
;
; P8LE-LABEL: spltRegValull:
; P8LE: # %bb.0: # %entry
-; P8LE-NEXT: mtvsrd f0, r3
+; P8LE-NEXT: mtfprd f0, r3
; P8LE-NEXT: xxspltd v2, vs0, 0
; P8LE-NEXT: blr
entry:
; CHECK-P8-NEXT: ld r3, 0(r3)
; CHECK-P8-NEXT: addis r4, r2, .LCPI12_0@toc@ha
; CHECK-P8-NEXT: xxlxor v4, v4, v4
-; CHECK-P8-NEXT: mtvsrd f0, r3
+; CHECK-P8-NEXT: mtfprd f0, r3
; CHECK-P8-NEXT: addi r3, r4, .LCPI12_0@toc@l
; CHECK-P8-NEXT: lvx v3, 0, r3
; CHECK-P8-NEXT: xxswapd v2, vs0
%3 = LI -37
%4 = RLDCL_rec %0, killed %3, 0, implicit-def $cr0
; CHECK: RLDICL_rec %0, 27, 0, implicit-def $cr0
- ; CHECK-LATE: rldicl. 5, 3, 27, 0
+ ; CHECK-LATE: rotldi. 5, 3, 27
%5 = COPY killed $cr0
%6 = ISEL8 %2, %0, %5.sub_eq
$x3 = COPY %6
%3 = LI 37
%4 = RLDCL_rec %0, killed %3, 0, implicit-def $cr0
; CHECK: RLDICL_rec %0, 37, 0, implicit-def $cr0
- ; CHECK-LATE: rldicl. 5, 3, 37, 0
+ ; CHECK-LATE: rotldi. 5, 3, 37
%5 = COPY killed $cr0
%6 = ISEL8 %2, %0, %5.sub_eq
$x3 = COPY %6
ret i32 %cond
; CHECK-LABEL: @exttest7
-; CHECK-DAG: cmpwi {{[0-9]+}}, 3, 5
+; CHECK-DAG: cmpwi 3, 5
; CHECK-DAG: li [[REG1:[0-9]+]], 8
; CHECK-DAG: li [[REG2:[0-9]+]], 7
; CHECK: isel 3, [[REG2]], [[REG1]],
; CHECK-NEXT: ldx 3, 3, 8
; CHECK-NEXT: mffprd 8, 0
; CHECK-NEXT: mfvsrld 10, 1
-; CHECK-NEXT: mfvsrd 11, 1
+; CHECK-NEXT: mffprd 11, 1
; CHECK-NEXT: mulld 8, 9, 8
; CHECK-NEXT: mulld 5, 8, 5
; CHECK-NEXT: mulld 5, 5, 10
; CHECK-LABEL: @testExpandISELToIfElse
; CHECK: addi r5, r3, 1
-; CHECK-NEXT: cmpwi cr0, r3, 0
+; CHECK-NEXT: cmpwi r3, 0
; CHECK-NEXT: bc 12, gt, [[TRUE:.LBB[0-9]+]]
; CHECK: ori r3, r4, 0
; CHECK-NEXT: b [[SUCCESSOR:.LBB[0-9]+]]
ret i32 %add
; CHECK-LABEL: @testExpandISELsTo2ORIs1ADDI
-; CHECK: cmpwi cr0, r7, 0
+; CHECK: cmpwi r7, 0
; CHECK-NEXT: bc 12, gt, [[TRUE:.LBB[0-9]+]]
; CHECK: ori r3, r4, 0
; CHECK-NEXT: ori r4, r6, 0
ret i32 %add2
; CHECK-LABEL: @testExpandISELsTo1ORI1ADDI
-; CHECK: cmpwi cr0, r7, 0
+; CHECK: cmpwi r7, 0
; CHECK-NEXT: bc 12, gt, [[TRUE:.LBB[0-9]+]]
; CHECK: ori r5, r6, 0
; CHECK-NEXT: b [[SUCCESSOR:.LBB[0-9]+]]
ret i32 %sub1
; CHECK-LABEL: @testExpandISELsTo0ORI2ADDIs
-; CHECK: cmpwi cr0, r7, 0
+; CHECK: cmpwi r7, 0
; CHECK-NEXT: bc 12, gt, [[TRUE:.LBB[0-9]+]]
; CHECK-NEXT: b [[SUCCESSOR:.LBB[0-9]+]]
; CHECK-NEXT: [[TRUE]]
; CHECK-NEXT: mfvsrd r3, vs34
; CHECK-NEXT: rldicl r6, r3, 32, 56
; CHECK-NEXT: rldicl r3, r3, 56, 56
-; CHECK-NEXT: mfvsrd r4, f0
+; CHECK-NEXT: mffprd r4, f0
; CHECK-NEXT: stb r6, 1(r5)
; CHECK-NEXT: stb r3, 2(r5)
; CHECK-NEXT: rldicl r6, r4, 32, 56
; CHECK-BE-NEXT: xxswapd vs0, vs34
; CHECK-BE-NEXT: mfvsrd r3, vs34
; CHECK-BE-NEXT: rldicl r6, r3, 40, 56
-; CHECK-BE-NEXT: mfvsrd r4, f0
+; CHECK-BE-NEXT: mffprd r4, f0
; CHECK-BE-NEXT: stb r6, 0(r5)
; CHECK-BE-NEXT: rldicl r6, r4, 40, 56
; CHECK-BE-NEXT: rldicl r4, r4, 16, 56
; CHECK-NEXT: rldicl r6, r3, 56, 56
; CHECK-NEXT: stb r4, 1(r5)
; CHECK-NEXT: rldicl r4, r3, 40, 56
-; CHECK-NEXT: mfvsrd r7, f0
+; CHECK-NEXT: mffprd r7, f0
; CHECK-NEXT: stb r6, 2(r5)
; CHECK-NEXT: rldicl r6, r3, 24, 56
; CHECK-NEXT: stb r4, 6(r5)
; CHECK-BE-NEXT: clrldi r6, r3, 56
; CHECK-BE-NEXT: stb r4, 0(r5)
; CHECK-BE-NEXT: rldicl r4, r3, 56, 56
-; CHECK-BE-NEXT: mfvsrd r7, f0
+; CHECK-BE-NEXT: mffprd r7, f0
; CHECK-BE-NEXT: stb r6, 3(r5)
; CHECK-BE-NEXT: rldicl r6, r3, 8, 56
; CHECK-BE-NEXT: stb r4, 4(r5)
; CHECK-DAG: std r7, 64(r1)
; CHECK-DAG: std r6, 56(r1)
; CHECK-DAG: std r4, 40(r1)
-; CHECK-DAG: cmpwi cr0, r3, 1
+; CHECK-DAG: cmpwi r3, 1
; CHECK-DAG: std r5, 48(r1)
; CHECK-DAG: addis [[REG:r[0-9]+]], r2, .LCPI17_0@toc@ha
; CHECK-DAG: addi [[REG1:r[0-9]+]], [[REG]], .LCPI17_0@toc@l
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xscvdpsxws f0, f1
; CHECK-NEXT: stfs f1, -4(r1)
-; CHECK-NEXT: mfvsrwz r3, f0
+; CHECK-NEXT: mffprwz r3, f0
; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xscvdpsxws f0, f1
; CHECK-NEXT: stfd f1, -8(r1)
-; CHECK-NEXT: mfvsrwz r3, f0
+; CHECK-NEXT: mffprwz r3, f0
; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xscvdpsxws f0, f1
; CHECK-NEXT: stfs f1, -4(r1)
-; CHECK-NEXT: mfvsrwz r3, f0
+; CHECK-NEXT: mffprwz r3, f0
; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xscvdpsxws f0, f1
; CHECK-NEXT: stfd f1, -8(r1)
-; CHECK-NEXT: mfvsrwz r3, f0
+; CHECK-NEXT: mffprwz r3, f0
; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xscvdpsxws f0, f1
; CHECK-NEXT: stfs f1, -4(r1)
-; CHECK-NEXT: mfvsrwz r3, f0
+; CHECK-NEXT: mffprwz r3, f0
; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xscvdpsxws f0, f1
; CHECK-NEXT: stfd f1, -8(r1)
-; CHECK-NEXT: mfvsrwz r3, f0
+; CHECK-NEXT: mffprwz r3, f0
; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xscvdpuxws f0, f1
; CHECK-NEXT: stfs f1, -4(r1)
-; CHECK-NEXT: mfvsrwz r3, f0
+; CHECK-NEXT: mffprwz r3, f0
; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xscvdpuxws f0, f1
; CHECK-NEXT: stfd f1, -8(r1)
-; CHECK-NEXT: mfvsrwz r3, f0
+; CHECK-NEXT: mffprwz r3, f0
; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
define i8 @rotl_i8_const_shift(i8 %x) {
; CHECK-LABEL: rotl_i8_const_shift:
; CHECK: # %bb.0:
-; CHECK-NEXT: rlwinm 4, 3, 27, 0, 31
+; CHECK-NEXT: rotlwi 4, 3, 27
; CHECK-NEXT: rlwimi 4, 3, 3, 0, 28
; CHECK-NEXT: mr 3, 4
; CHECK-NEXT: blr
; CHECK: # %bb.0:
; CHECK-NEXT: neg 5, 4
; CHECK-NEXT: clrlwi 6, 3, 16
-; CHECK-NEXT: rlwinm 4, 4, 0, 28, 31
+; CHECK-NEXT: clrlwi 4, 4, 28
; CHECK-NEXT: clrlwi 5, 5, 28
; CHECK-NEXT: slw 3, 3, 4
; CHECK-NEXT: srw 4, 6, 5
define i32 @rotl_i32(i32 %x, i32 %z) {
; CHECK-LABEL: rotl_i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: rlwnm 3, 3, 4, 0, 31
+; CHECK-NEXT: rotlw 3, 3, 4
; CHECK-NEXT: blr
%f = call i32 @llvm.fshl.i32(i32 %x, i32 %x, i32 %z)
ret i32 %f
define i64 @rotl_i64(i64 %x, i64 %z) {
; CHECK-LABEL: rotl_i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: rldcl 3, 3, 4, 0
+; CHECK-NEXT: rotld 3, 3, 4
; CHECK-NEXT: blr
%f = call i64 @llvm.fshl.i64(i64 %x, i64 %x, i64 %z)
ret i64 %f
define i8 @rotr_i8_const_shift(i8 %x) {
; CHECK-LABEL: rotr_i8_const_shift:
; CHECK: # %bb.0:
-; CHECK-NEXT: rlwinm 4, 3, 29, 0, 31
+; CHECK-NEXT: rotlwi 4, 3, 29
; CHECK-NEXT: rlwimi 4, 3, 5, 0, 26
; CHECK-NEXT: mr 3, 4
; CHECK-NEXT: blr
define i32 @rotr_i32_const_shift(i32 %x) {
; CHECK-LABEL: rotr_i32_const_shift:
; CHECK: # %bb.0:
-; CHECK-NEXT: rlwinm 3, 3, 29, 0, 31
+; CHECK-NEXT: rotlwi 3, 3, 29
; CHECK-NEXT: blr
%f = call i32 @llvm.fshr.i32(i32 %x, i32 %x, i32 3)
ret i32 %f
; CHECK: # %bb.0:
; CHECK-NEXT: neg 5, 4
; CHECK-NEXT: clrlwi 6, 3, 16
-; CHECK-NEXT: rlwinm 4, 4, 0, 28, 31
+; CHECK-NEXT: clrlwi 4, 4, 28
; CHECK-NEXT: clrlwi 5, 5, 28
; CHECK-NEXT: srw 4, 6, 4
; CHECK-NEXT: slw 3, 3, 5
; CHECK-LABEL: rotr_i32:
; CHECK: # %bb.0:
; CHECK-NEXT: neg 4, 4
-; CHECK-NEXT: rlwnm 3, 3, 4, 0, 31
+; CHECK-NEXT: rotlw 3, 3, 4
; CHECK-NEXT: blr
%f = call i32 @llvm.fshr.i32(i32 %x, i32 %x, i32 %z)
ret i32 %f
; CHECK-LABEL: rotr_i64:
; CHECK: # %bb.0:
; CHECK-NEXT: neg 4, 4
-; CHECK-NEXT: rldcl 3, 3, 4, 0
+; CHECK-NEXT: rotld 3, 3, 4
; CHECK-NEXT: blr
%f = call i64 @llvm.fshr.i64(i64 %x, i64 %x, i64 %z)
ret i64 %f
; CHECK-NEXT: mulhdu 6, 5, 6
; CHECK-NEXT: rldicl 6, 6, 59, 5
; CHECK-NEXT: mulli 6, 6, 37
-; CHECK-NEXT: subf. 5, 6, 5
+; CHECK-NEXT: sub. 5, 5, 6
; CHECK-NEXT: subfic 6, 5, 37
; CHECK-NEXT: sld 5, 3, 5
; CHECK-NEXT: srd 4, 4, 6
define i32 @fshl_i32_const_shift(i32 %x, i32 %y) {
; CHECK-LABEL: fshl_i32_const_shift:
; CHECK: # %bb.0:
-; CHECK-NEXT: rlwinm 4, 4, 9, 0, 31
+; CHECK-NEXT: rotlwi 4, 4, 9
; CHECK-NEXT: rlwimi 4, 3, 9, 0, 22
; CHECK-NEXT: mr 3, 4
; CHECK-NEXT: blr
define i32 @fshl_i32_const_overshift(i32 %x, i32 %y) {
; CHECK-LABEL: fshl_i32_const_overshift:
; CHECK: # %bb.0:
-; CHECK-NEXT: rlwinm 4, 4, 9, 0, 31
+; CHECK-NEXT: rotlwi 4, 4, 9
; CHECK-NEXT: rlwimi 4, 3, 9, 0, 22
; CHECK-NEXT: mr 3, 4
; CHECK-NEXT: blr
; CHECK-NEXT: mulhdu 6, 5, 6
; CHECK-NEXT: rldicl 6, 6, 59, 5
; CHECK-NEXT: mulli 6, 6, 37
-; CHECK-NEXT: subf. 5, 6, 5
+; CHECK-NEXT: sub. 5, 5, 6
; CHECK-NEXT: clrldi 6, 4, 27
; CHECK-NEXT: subfic 7, 5, 37
; CHECK-NEXT: srd 5, 6, 5
define i32 @fshr_i32_const_shift(i32 %x, i32 %y) {
; CHECK-LABEL: fshr_i32_const_shift:
; CHECK: # %bb.0:
-; CHECK-NEXT: rlwinm 4, 4, 23, 0, 31
+; CHECK-NEXT: rotlwi 4, 4, 23
; CHECK-NEXT: rlwimi 4, 3, 23, 0, 8
; CHECK-NEXT: mr 3, 4
; CHECK-NEXT: blr
define i32 @fshr_i32_const_overshift(i32 %x, i32 %y) {
; CHECK-LABEL: fshr_i32_const_overshift:
; CHECK: # %bb.0:
-; CHECK-NEXT: rlwinm 4, 4, 23, 0, 31
+; CHECK-NEXT: rotlwi 4, 4, 23
; CHECK-NEXT: rlwimi 4, 3, 23, 0, 8
; CHECK-NEXT: mr 3, 4
; CHECK-NEXT: blr
; CHECK: sc
; CHECK: #NO_APP
-; CHECK: cmpwi {{[0-9]+}}, [[REG]], 1
+; CHECK: cmpwi [[REG]], 1
; CHECK: blr
define dso_local signext i32 @spillCRSET(i32 signext %p1, i32 signext %p2) {
; CHECK-LABEL: spillCRSET:
; CHECK: # %bb.2:
-; CHECK-DAG: crnor [[CREG:.*]]*cr5+lt, eq, eq
+; CHECK-DAG: crnot [[CREG:.*]]*cr5+lt, eq
; CHECK-DAG: mfocrf [[REG2:.*]], [[CREG]]
; CHECK-DAG: rlwinm [[REG2]], [[REG2]]
; CHECK: .LBB0_3:
; P8-LABEL: adjusted_lxvwsx:
; P8: # %bb.0: # %entry
; P8-NEXT: ld r3, 0(r3)
-; P8-NEXT: mtvsrd f0, r3
+; P8-NEXT: mtfprd f0, r3
; P8-NEXT: xxswapd v2, vs0
; P8-NEXT: xxspltw v2, v2, 2
; P8-NEXT: blr
define void @test(i8* %ptr, i8 %cmp, i8 %val) {
; PPC64LE-LABEL: test:
; PPC64LE: # %bb.0:
-; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31
+; PPC64LE-NEXT: clrlwi 4, 4, 24
; PPC64LE-NEXT: .LBB0_1:
; PPC64LE-NEXT: lbarx 6, 0, 3
; PPC64LE-NEXT: cmpw 4, 6
; CHECK: # %bb.0:
; CHECK-NEXT: ldbrx 3, 0, 3
; CHECK-NEXT: ldbrx 4, 0, 4
-; CHECK-NEXT: subfc 5, 3, 4
+; CHECK-NEXT: subc 5, 4, 3
; CHECK-NEXT: subfe 5, 4, 4
-; CHECK-NEXT: subfc 4, 4, 3
+; CHECK-NEXT: subc 4, 3, 4
; CHECK-NEXT: subfe 3, 3, 3
; CHECK-NEXT: neg 4, 5
; CHECK-NEXT: neg 3, 3
define i64 @fool(i64 %a, i64 %b, i64* nocapture %c) #0 {
; CHECK-LABEL: fool:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: subf. 6, 4, 3
+; CHECK-NEXT: sub. 6, 3, 4
; CHECK-NEXT: isel 3, 3, 4, 1
; CHECK-NEXT: std 6, 0(5)
; CHECK-NEXT: blr
;
; CHECK-NO-ISEL-LABEL: fool:
; CHECK-NO-ISEL: # %bb.0: # %entry
-; CHECK-NO-ISEL-NEXT: subf. 6, 4, 3
+; CHECK-NO-ISEL-NEXT: sub. 6, 3, 4
; CHECK-NO-ISEL-NEXT: bc 12, 1, .LBB2_2
; CHECK-NO-ISEL-NEXT: # %bb.1: # %entry
; CHECK-NO-ISEL-NEXT: ori 3, 4, 0
define i64 @foolb(i64 %a, i64 %b, i64* nocapture %c) #0 {
; CHECK-LABEL: foolb:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: subf. 6, 4, 3
+; CHECK-NEXT: sub. 6, 3, 4
; CHECK-NEXT: isel 3, 4, 3, 1
; CHECK-NEXT: std 6, 0(5)
; CHECK-NEXT: blr
;
; CHECK-NO-ISEL-LABEL: foolb:
; CHECK-NO-ISEL: # %bb.0: # %entry
-; CHECK-NO-ISEL-NEXT: subf. 6, 4, 3
+; CHECK-NO-ISEL-NEXT: sub. 6, 3, 4
; CHECK-NO-ISEL-NEXT: bc 12, 1, .LBB3_1
; CHECK-NO-ISEL-NEXT: b .LBB3_2
; CHECK-NO-ISEL-NEXT: .LBB3_1: # %entry
define i64 @foolc(i64 %a, i64 %b, i64* nocapture %c) #0 {
; CHECK-LABEL: foolc:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: subf. 6, 3, 4
+; CHECK-NEXT: sub. 6, 4, 3
; CHECK-NEXT: isel 3, 3, 4, 0
; CHECK-NEXT: std 6, 0(5)
; CHECK-NEXT: blr
;
; CHECK-NO-ISEL-LABEL: foolc:
; CHECK-NO-ISEL: # %bb.0: # %entry
-; CHECK-NO-ISEL-NEXT: subf. 6, 3, 4
+; CHECK-NO-ISEL-NEXT: sub. 6, 4, 3
; CHECK-NO-ISEL-NEXT: bc 12, 0, .LBB4_2
; CHECK-NO-ISEL-NEXT: # %bb.1: # %entry
; CHECK-NO-ISEL-NEXT: ori 3, 4, 0
define i64 @foold(i64 %a, i64 %b, i64* nocapture %c) #0 {
; CHECK-LABEL: foold:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: subf. 6, 3, 4
+; CHECK-NEXT: sub. 6, 4, 3
; CHECK-NEXT: isel 3, 3, 4, 1
; CHECK-NEXT: std 6, 0(5)
; CHECK-NEXT: blr
;
; CHECK-NO-ISEL-LABEL: foold:
; CHECK-NO-ISEL: # %bb.0: # %entry
-; CHECK-NO-ISEL-NEXT: subf. 6, 3, 4
+; CHECK-NO-ISEL-NEXT: sub. 6, 4, 3
; CHECK-NO-ISEL-NEXT: bc 12, 1, .LBB5_2
; CHECK-NO-ISEL-NEXT: # %bb.1: # %entry
; CHECK-NO-ISEL-NEXT: ori 3, 4, 0
define i64 @foold2(i64 %a, i64 %b, i64* nocapture %c) #0 {
; CHECK-LABEL: foold2:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: subf. 6, 4, 3
+; CHECK-NEXT: sub. 6, 3, 4
; CHECK-NEXT: isel 3, 3, 4, 0
; CHECK-NEXT: std 6, 0(5)
; CHECK-NEXT: blr
;
; CHECK-NO-ISEL-LABEL: foold2:
; CHECK-NO-ISEL: # %bb.0: # %entry
-; CHECK-NO-ISEL-NEXT: subf. 6, 4, 3
+; CHECK-NO-ISEL-NEXT: sub. 6, 3, 4
; CHECK-NO-ISEL-NEXT: bc 12, 0, .LBB6_2
; CHECK-NO-ISEL-NEXT: # %bb.1: # %entry
; CHECK-NO-ISEL-NEXT: ori 3, 4, 0
; CHECK-NEXT: li r4, 3
; CHECK-NEXT: isel r4, r5, r4, eq
; CHECK-NEXT: srd r3, r3, r4
-; CHECK-NEXT: rlwinm r3, r3, 0, 9, 31
-; CHECK-NEXT: mtvsrd f0, r3
+; CHECK-NEXT: clrlwi r3, r3, 9
+; CHECK-NEXT: mtfprd f0, r3
; CHECK-NEXT: xxsldwi vs0, vs0, vs0, 1
; CHECK-NEXT: xscvspdpn f1, vs0
; CHECK-NEXT: blr
; CHECK: sldi r3, r3, 56
; CHECK: mtvsrd v2, r3
; CHECK-LE-LABEL: buildc
-; CHECK-LE: mtvsrd f0, r3
+; CHECK-LE: mtfprd f0, r3
; CHECK-LE: xxswapd v2, vs0
}
; CHECK: sldi r3, r3, 48
; CHECK: mtvsrd v2, r3
; CHECK-LE-LABEL: builds
-; CHECK-LE: mtvsrd f0, r3
+; CHECK-LE: mtfprd f0, r3
; CHECK-LE: xxswapd v2, vs0
}
%splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer
ret <4 x i32> %splat.splat
; CHECK-LABEL: buildi
-; CHECK: mtvsrwz f0, r3
+; CHECK: mtfprwz f0, r3
; CHECK: xxspltw v2, vs0, 1
; CHECK-LE-LABEL: buildi
-; CHECK-LE: mtvsrwz f0, r3
+; CHECK-LE: mtfprwz f0, r3
; CHECK-LE: xxspltw v2, vs0, 1
}
%splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer
ret <2 x i64> %splat.splat
; CHECK-LABEL: buildl
-; CHECK: mtvsrd f0, r3
+; CHECK: mtfprd f0, r3
; CHECK-LE-LABEL: buildl
-; CHECK-LE: mtvsrd f0, r3
+; CHECK-LE: mtfprd f0, r3
; CHECK-LE: xxspltd v2, vs0, 0
}
; CHECK: rldicl r3, r3, 8, 56
; CHECK: extsb r3, r3
; CHECK-LE-LABEL: @getsc0
-; CHECK-LE: mfvsrd r3, f0
+; CHECK-LE: mffprd r3, f0
; CHECK-LE: clrldi r3, r3, 56
; CHECK-LE: extsb r3, r3
}
; CHECK: rldicl r3, r3, 16, 56
; CHECK: extsb r3, r3
; CHECK-LE-LABEL: @getsc1
-; CHECK-LE: mfvsrd r3, f0
+; CHECK-LE: mffprd r3, f0
; CHECK-LE: rldicl r3, r3, 56, 56
; CHECK-LE: extsb r3, r3
}
; CHECK: rldicl r3, r3, 24, 56
; CHECK: extsb r3, r3
; CHECK-LE-LABEL: @getsc2
-; CHECK-LE: mfvsrd r3, f0
+; CHECK-LE: mffprd r3, f0
; CHECK-LE: rldicl r3, r3, 48, 56
; CHECK-LE: extsb r3, r3
}
; CHECK: rldicl r3, r3, 32, 56
; CHECK: extsb r3, r3
; CHECK-LE-LABEL: @getsc3
-; CHECK-LE: mfvsrd r3, f0
+; CHECK-LE: mffprd r3, f0
; CHECK-LE: rldicl r3, r3, 40, 56
; CHECK-LE: extsb r3, r3
}
; CHECK: rldicl r3, r3, 40, 56
; CHECK: extsb r3, r3
; CHECK-LE-LABEL: @getsc4
-; CHECK-LE: mfvsrd r3, f0
+; CHECK-LE: mffprd r3, f0
; CHECK-LE: rldicl r3, r3, 32, 56
; CHECK-LE: extsb r3, r3
}
; CHECK: rldicl r3, r3, 48, 56
; CHECK: extsb r3, r3
; CHECK-LE-LABEL: @getsc5
-; CHECK-LE: mfvsrd r3, f0
+; CHECK-LE: mffprd r3, f0
; CHECK-LE: rldicl r3, r3, 24, 56
; CHECK-LE: extsb r3, r3
}
; CHECK: rldicl r3, r3, 56, 56
; CHECK: extsb r3, r3
; CHECK-LE-LABEL: @getsc6
-; CHECK-LE: mfvsrd r3, f0
+; CHECK-LE: mffprd r3, f0
; CHECK-LE: rldicl r3, r3, 16, 56
; CHECK-LE: extsb r3, r3
}
; CHECK: clrldi r3, r3, 56
; CHECK: extsb r3, r3
; CHECK-LE-LABEL: @getsc7
-; CHECK-LE: mfvsrd r3, f0
+; CHECK-LE: mffprd r3, f0
; CHECK-LE: rldicl r3, r3, 8, 56
; CHECK-LE: extsb r3, r3
}
%vecext = extractelement <16 x i8> %vsc, i32 8
ret i8 %vecext
; CHECK-LABEL: @getsc8
-; CHECK: mfvsrd r3, f0
+; CHECK: mffprd r3, f0
; CHECK: rldicl r3, r3, 8, 56
; CHECK: extsb r3, r3
; CHECK-LE-LABEL: @getsc8
%vecext = extractelement <16 x i8> %vsc, i32 9
ret i8 %vecext
; CHECK-LABEL: @getsc9
-; CHECK: mfvsrd r3, f0
+; CHECK: mffprd r3, f0
; CHECK: rldicl r3, r3, 16, 56
; CHECK: extsb r3, r3
; CHECK-LE-LABEL: @getsc9
%vecext = extractelement <16 x i8> %vsc, i32 10
ret i8 %vecext
; CHECK-LABEL: @getsc10
-; CHECK: mfvsrd r3, f0
+; CHECK: mffprd r3, f0
; CHECK: rldicl r3, r3, 24, 56
; CHECK: extsb r3, r3
; CHECK-LE-LABEL: @getsc10
%vecext = extractelement <16 x i8> %vsc, i32 11
ret i8 %vecext
; CHECK-LABEL: @getsc11
-; CHECK: mfvsrd r3, f0
+; CHECK: mffprd r3, f0
; CHECK: rldicl r3, r3, 32, 56
; CHECK: extsb r3, r3
; CHECK-LE-LABEL: @getsc11
%vecext = extractelement <16 x i8> %vsc, i32 12
ret i8 %vecext
; CHECK-LABEL: @getsc12
-; CHECK: mfvsrd r3, f0
+; CHECK: mffprd r3, f0
; CHECK: rldicl r3, r3, 40, 56
; CHECK: extsb r3, r3
; CHECK-LE-LABEL: @getsc12
%vecext = extractelement <16 x i8> %vsc, i32 13
ret i8 %vecext
; CHECK-LABEL: @getsc13
-; CHECK: mfvsrd r3, f0
+; CHECK: mffprd r3, f0
; CHECK: rldicl r3, r3, 48, 56
; CHECK: extsb r3, r3
; CHECK-LE-LABEL: @getsc13
%vecext = extractelement <16 x i8> %vsc, i32 14
ret i8 %vecext
; CHECK-LABEL: @getsc14
-; CHECK: mfvsrd r3, f0
+; CHECK: mffprd r3, f0
; CHECK: rldicl r3, r3, 56, 56
; CHECK: extsb r3, r3
; CHECK-LE-LABEL: @getsc14
%vecext = extractelement <16 x i8> %vsc, i32 15
ret i8 %vecext
; CHECK-LABEL: @getsc15
-; CHECK: mfvsrd r3, f0
+; CHECK: mffprd r3, f0
; CHECK: clrldi r3, r3, 56
; CHECK: extsb r3, r3
; CHECK-LE-LABEL: @getsc15
; CHECK: mfvsrd r3, v2
; CHECK: rldicl r3, r3, 8, 56
; CHECK-LE-LABEL: @getuc0
-; CHECK-LE: mfvsrd r3, f0
+; CHECK-LE: mffprd r3, f0
; CHECK-LE: clrldi r3, r3, 56
}
; CHECK: mfvsrd r3, v2
; CHECK: rldicl r3, r3, 16, 56
; CHECK-LE-LABEL: @getuc1
-; CHECK-LE: mfvsrd r3, f0
+; CHECK-LE: mffprd r3, f0
; CHECK-LE: rldicl r3, r3, 56, 56
}
; CHECK: mfvsrd r3, v2
; CHECK: rldicl r3, r3, 24, 56
; CHECK-LE-LABEL: @getuc2
-; CHECK-LE: mfvsrd r3, f0
+; CHECK-LE: mffprd r3, f0
; CHECK-LE: rldicl r3, r3, 48, 56
}
; CHECK: mfvsrd r3, v2
; CHECK: rldicl r3, r3, 32, 56
; CHECK-LE-LABEL: @getuc3
-; CHECK-LE: mfvsrd r3, f0
+; CHECK-LE: mffprd r3, f0
; CHECK-LE: rldicl r3, r3, 40, 56
}
; CHECK: mfvsrd r3, v2
; CHECK: rldicl r3, r3, 40, 56
; CHECK-LE-LABEL: @getuc4
-; CHECK-LE: mfvsrd r3, f0
+; CHECK-LE: mffprd r3, f0
; CHECK-LE: rldicl r3, r3, 32, 56
}
; CHECK: mfvsrd r3, v2
; CHECK: rldicl r3, r3, 48, 56
; CHECK-LE-LABEL: @getuc5
-; CHECK-LE: mfvsrd r3, f0
+; CHECK-LE: mffprd r3, f0
; CHECK-LE: rldicl r3, r3, 24, 56
}
; CHECK: mfvsrd r3, v2
; CHECK: rldicl r3, r3, 56, 56
; CHECK-LE-LABEL: @getuc6
-; CHECK-LE: mfvsrd r3, f0
+; CHECK-LE: mffprd r3, f0
; CHECK-LE: rldicl r3, r3, 16, 56
}
; CHECK: mfvsrd r3, v2
; CHECK: clrldi r3, r3, 56
; CHECK-LE-LABEL: @getuc7
-; CHECK-LE: mfvsrd r3, f0
+; CHECK-LE: mffprd r3, f0
; CHECK-LE: rldicl r3, r3, 8, 56
}
%vecext = extractelement <16 x i8> %vuc, i32 8
ret i8 %vecext
; CHECK-LABEL: @getuc8
-; CHECK: mfvsrd r3, f0
+; CHECK: mffprd r3, f0
; CHECK: rldicl r3, r3, 8, 56
; CHECK-LE-LABEL: @getuc8
; CHECK-LE: mfvsrd r3, v2
%vecext = extractelement <16 x i8> %vuc, i32 9
ret i8 %vecext
; CHECK-LABEL: @getuc9
-; CHECK: mfvsrd r3, f0
+; CHECK: mffprd r3, f0
; CHECK: rldicl r3, r3, 16, 56
; CHECK-LE-LABEL: @getuc9
; CHECK-LE: mfvsrd r3, v2
%vecext = extractelement <16 x i8> %vuc, i32 10
ret i8 %vecext
; CHECK-LABEL: @getuc10
-; CHECK: mfvsrd r3, f0
+; CHECK: mffprd r3, f0
; CHECK: rldicl r3, r3, 24, 56
; CHECK-LE-LABEL: @getuc10
; CHECK-LE: mfvsrd r3, v2
%vecext = extractelement <16 x i8> %vuc, i32 11
ret i8 %vecext
; CHECK-LABEL: @getuc11
-; CHECK: mfvsrd r3, f0
+; CHECK: mffprd r3, f0
; CHECK: rldicl r3, r3, 32, 56
; CHECK-LE-LABEL: @getuc11
; CHECK-LE: mfvsrd r3, v2
%vecext = extractelement <16 x i8> %vuc, i32 12
ret i8 %vecext
; CHECK-LABEL: @getuc12
-; CHECK: mfvsrd r3, f0
+; CHECK: mffprd r3, f0
; CHECK: rldicl r3, r3, 40, 56
; CHECK-LE-LABEL: @getuc12
; CHECK-LE: mfvsrd r3, v2
%vecext = extractelement <16 x i8> %vuc, i32 13
ret i8 %vecext
; CHECK-LABEL: @getuc13
-; CHECK: mfvsrd r3, f0
+; CHECK: mffprd r3, f0
; CHECK: rldicl r3, r3, 48, 56
; CHECK-LE-LABEL: @getuc13
; CHECK-LE: mfvsrd r3, v2
%vecext = extractelement <16 x i8> %vuc, i32 14
ret i8 %vecext
; CHECK-LABEL: @getuc14
-; CHECK: mfvsrd r3, f0
+; CHECK: mffprd r3, f0
; CHECK: rldicl r3, r3, 56, 56
; CHECK-LE-LABEL: @getuc14
; CHECK-LE: mfvsrd r3, v2
%vecext = extractelement <16 x i8> %vuc, i32 15
ret i8 %vecext
; CHECK-LABEL: @getuc15
-; CHECK: mfvsrd r3, f0
+; CHECK: mffprd r3, f0
; CHECK: clrldi r3, r3, 56
; CHECK-LE-LABEL: @getuc15
; CHECK-LE: mfvsrd r3, v2
; CHECK: rldicl r3, r3, 16, 48
; CHECK: extsh r3, r3
; CHECK-LE-LABEL: @getss0
-; CHECK-LE: mfvsrd r3, f0
+; CHECK-LE: mffprd r3, f0
; CHECK-LE: clrldi r3, r3, 48
; CHECK-LE: extsh r3, r3
}
; CHECK: rldicl r3, r3, 32, 48
; CHECK: extsh r3, r3
; CHECK-LE-LABEL: @getss1
-; CHECK-LE: mfvsrd r3, f0
+; CHECK-LE: mffprd r3, f0
; CHECK-LE: rldicl r3, r3, 48, 48
; CHECK-LE: extsh r3, r3
}
; CHECK: rldicl r3, r3, 48, 48
; CHECK: extsh r3, r3
; CHECK-LE-LABEL: @getss2
-; CHECK-LE: mfvsrd r3, f0
+; CHECK-LE: mffprd r3, f0
; CHECK-LE: rldicl r3, r3, 32, 48
; CHECK-LE: extsh r3, r3
}
; CHECK: clrldi r3, r3, 48
; CHECK: extsh r3, r3
; CHECK-LE-LABEL: @getss3
-; CHECK-LE: mfvsrd r3, f0
+; CHECK-LE: mffprd r3, f0
; CHECK-LE: rldicl r3, r3, 16, 48
; CHECK-LE: extsh r3, r3
}
%vecext = extractelement <8 x i16> %vss, i32 4
ret i16 %vecext
; CHECK-LABEL: @getss4
-; CHECK: mfvsrd r3, f0
+; CHECK: mffprd r3, f0
; CHECK: rldicl r3, r3, 16, 48
; CHECK: extsh r3, r3
; CHECK-LE-LABEL: @getss4
%vecext = extractelement <8 x i16> %vss, i32 5
ret i16 %vecext
; CHECK-LABEL: @getss5
-; CHECK: mfvsrd r3, f0
+; CHECK: mffprd r3, f0
; CHECK: rldicl r3, r3, 32, 48
; CHECK: extsh r3, r3
; CHECK-LE-LABEL: @getss5
%vecext = extractelement <8 x i16> %vss, i32 6
ret i16 %vecext
; CHECK-LABEL: @getss6
-; CHECK: mfvsrd r3, f0
+; CHECK: mffprd r3, f0
; CHECK: rldicl r3, r3, 48, 48
; CHECK: extsh r3, r3
; CHECK-LE-LABEL: @getss6
%vecext = extractelement <8 x i16> %vss, i32 7
ret i16 %vecext
; CHECK-LABEL: @getss7
-; CHECK: mfvsrd r3, f0
+; CHECK: mffprd r3, f0
; CHECK: clrldi r3, r3, 48
; CHECK: extsh r3, r3
; CHECK-LE-LABEL: @getss7
; CHECK: mfvsrd r3, v2
; CHECK: rldicl r3, r3, 16, 48
; CHECK-LE-LABEL: @getus0
-; CHECK-LE: mfvsrd r3, f0
+; CHECK-LE: mffprd r3, f0
; CHECK-LE: clrldi r3, r3, 48
}
; CHECK: mfvsrd r3, v2
; CHECK: rldicl r3, r3, 32, 48
; CHECK-LE-LABEL: @getus1
-; CHECK-LE: mfvsrd r3, f0
+; CHECK-LE: mffprd r3, f0
; CHECK-LE: rldicl r3, r3, 48, 48
}
; CHECK: mfvsrd r3, v2
; CHECK: rldicl r3, r3, 48, 48
; CHECK-LE-LABEL: @getus2
-; CHECK-LE: mfvsrd r3, f0
+; CHECK-LE: mffprd r3, f0
; CHECK-LE: rldicl r3, r3, 32, 48
}
; CHECK: mfvsrd r3, v2
; CHECK: clrldi r3, r3, 48
; CHECK-LE-LABEL: @getus3
-; CHECK-LE: mfvsrd r3, f0
+; CHECK-LE: mffprd r3, f0
; CHECK-LE: rldicl r3, r3, 16, 48
}
%vecext = extractelement <8 x i16> %vus, i32 4
ret i16 %vecext
; CHECK-LABEL: @getus4
-; CHECK: mfvsrd r3, f0
+; CHECK: mffprd r3, f0
; CHECK: rldicl r3, r3, 16, 48
; CHECK-LE-LABEL: @getus4
; CHECK-LE: mfvsrd r3, v2
%vecext = extractelement <8 x i16> %vus, i32 5
ret i16 %vecext
; CHECK-LABEL: @getus5
-; CHECK: mfvsrd r3, f0
+; CHECK: mffprd r3, f0
; CHECK: rldicl r3, r3, 32, 48
; CHECK-LE-LABEL: @getus5
; CHECK-LE: mfvsrd r3, v2
%vecext = extractelement <8 x i16> %vus, i32 6
ret i16 %vecext
; CHECK-LABEL: @getus6
-; CHECK: mfvsrd r3, f0
+; CHECK: mffprd r3, f0
; CHECK: rldicl r3, r3, 48, 48
; CHECK-LE-LABEL: @getus6
; CHECK-LE: mfvsrd r3, v2
%vecext = extractelement <8 x i16> %vus, i32 7
ret i16 %vecext
; CHECK-LABEL: @getus7
-; CHECK: mfvsrd r3, f0
+; CHECK: mffprd r3, f0
; CHECK: clrldi r3, r3, 48
; CHECK-LE-LABEL: @getus7
; CHECK-LE: mfvsrd r3, v2
ret i32 %vecext
; CHECK-LABEL: @getsi0
; CHECK: xxsldwi vs0, v2, v2, 3
-; CHECK: mfvsrwz r3, f0
+; CHECK: mffprwz r3, f0
; CHECK: extsw r3, r3
; CHECK-LE-LABEL: @getsi0
; CHECK-LE: xxswapd vs0, v2
-; CHECK-LE: mfvsrwz r3, f0
+; CHECK-LE: mffprwz r3, f0
; CHECK-LE: extsw r3, r3
}
; CHECK: extsw r3, r3
; CHECK-LE-LABEL: @getsi1
; CHECK-LE: xxsldwi vs0, v2, v2, 1
-; CHECK-LE: mfvsrwz r3, f0
+; CHECK-LE: mffprwz r3, f0
; CHECK-LE: extsw r3, r3
}
ret i32 %vecext
; CHECK-LABEL: @getsi2
; CHECK: xxsldwi vs0, v2, v2, 1
-; CHECK: mfvsrwz r3, f0
+; CHECK: mffprwz r3, f0
; CHECK: extsw r3, r3
; CHECK-LE-LABEL: @getsi2
; CHECK-LE: mfvsrwz r3, v2
ret i32 %vecext
; CHECK-LABEL: @getsi3
; CHECK: xxswapd vs0, v2
-; CHECK: mfvsrwz r3, f0
+; CHECK: mffprwz r3, f0
; CHECK: extsw r3, r3
; CHECK-LE-LABEL: @getsi3
; CHECK-LE: xxsldwi vs0, v2, v2, 3
-; CHECK-LE: mfvsrwz r3, f0
+; CHECK-LE: mffprwz r3, f0
; CHECK-LE: extsw r3, r3
}
ret i32 %vecext
; CHECK-LABEL: @getui0
; CHECK: xxsldwi vs0, v2, v2, 3
-; CHECK: mfvsrwz r3, f0
+; CHECK: mffprwz r3, f0
; CHECK-LE-LABEL: @getui0
; CHECK-LE: xxswapd vs0, v2
-; CHECK-LE: mfvsrwz r3, f0
+; CHECK-LE: mffprwz r3, f0
}
; Function Attrs: norecurse nounwind readnone
; CHECK: mfvsrwz r3, v2
; CHECK-LE-LABEL: @getui1
; CHECK-LE: xxsldwi vs0, v2, v2, 1
-; CHECK-LE: mfvsrwz r3, f0
+; CHECK-LE: mffprwz r3, f0
}
; Function Attrs: norecurse nounwind readnone
ret i32 %vecext
; CHECK-LABEL: @getui2
; CHECK: xxsldwi vs0, v2, v2, 1
-; CHECK: mfvsrwz r3, f0
+; CHECK: mffprwz r3, f0
; CHECK-LE-LABEL: @getui2
; CHECK-LE: mfvsrwz r3, v2
}
ret i32 %vecext
; CHECK-LABEL: @getui3
; CHECK: xxswapd vs0, v2
-; CHECK: mfvsrwz r3, f0
+; CHECK: mffprwz r3, f0
; CHECK-LE-LABEL: @getui3
; CHECK-LE: xxsldwi vs0, v2, v2, 3
-; CHECK-LE: mfvsrwz r3, f0
+; CHECK-LE: mffprwz r3, f0
}
; Function Attrs: norecurse nounwind readnone
; CHECK: mfvsrd r3, v2
; CHECK-LE-LABEL: @getsl0
; CHECK-LE: xxswapd vs0, v2
-; CHECK-LE: mfvsrd r3, f0
+; CHECK-LE: mffprd r3, f0
}
; Function Attrs: norecurse nounwind readnone
ret i64 %vecext
; CHECK-LABEL: @getsl1
; CHECK: xxswapd vs0, v2
-; CHECK: mfvsrd r3, f0
+; CHECK: mffprd r3, f0
; CHECK-LE-LABEL: @getsl1
; CHECK-LE: mfvsrd r3, v2
}
; CHECK: mfvsrd r3, v2
; CHECK-LE-LABEL: @getul0
; CHECK-LE: xxswapd vs0, v2
-; CHECK-LE: mfvsrd r3, f0
+; CHECK-LE: mffprd r3, f0
}
; Function Attrs: norecurse nounwind readnone
ret i64 %vecext
; CHECK-LABEL: @getul1
; CHECK: xxswapd vs0, v2
-; CHECK: mfvsrd r3, f0
+; CHECK: mffprd r3, f0
; CHECK-LE-LABEL: @getul1
; CHECK-LE: mfvsrd r3, v2
}
define <4 x i32> @_Z10testInsEltILj0EDv4_jjET0_S1_T1_(<4 x i32> %a, i32 zeroext %b) {
entry:
; CHECK-LABEL: _Z10testInsEltILj0EDv4_jjET0_S1_T1_
-; CHECK: mtvsrwz 0, 5
+; CHECK: mtfprwz 0, 5
; CHECK: xxinsertw 34, 0, 12
; CHECK-BE-LABEL: _Z10testInsEltILj0EDv4_jjET0_S1_T1_
-; CHECK-BE: mtvsrwz 0, 5
+; CHECK-BE: mtfprwz 0, 5
; CHECK-BE: xxinsertw 34, 0, 0
%vecins = insertelement <4 x i32> %a, i32 %b, i32 0
ret <4 x i32> %vecins
define <4 x i32> @_Z10testInsEltILj1EDv4_jjET0_S1_T1_(<4 x i32> %a, i32 zeroext %b) {
entry:
; CHECK-LABEL: _Z10testInsEltILj1EDv4_jjET0_S1_T1_
-; CHECK: mtvsrwz 0, 5
+; CHECK: mtfprwz 0, 5
; CHECK: xxinsertw 34, 0, 8
; CHECK-BE-LABEL: _Z10testInsEltILj1EDv4_jjET0_S1_T1_
-; CHECK-BE: mtvsrwz 0, 5
+; CHECK-BE: mtfprwz 0, 5
; CHECK-BE: xxinsertw 34, 0, 4
%vecins = insertelement <4 x i32> %a, i32 %b, i32 1
ret <4 x i32> %vecins
define <4 x i32> @_Z10testInsEltILj2EDv4_jjET0_S1_T1_(<4 x i32> %a, i32 zeroext %b) {
entry:
; CHECK-LABEL: _Z10testInsEltILj2EDv4_jjET0_S1_T1_
-; CHECK: mtvsrwz 0, 5
+; CHECK: mtfprwz 0, 5
; CHECK: xxinsertw 34, 0, 4
; CHECK-BE-LABEL: _Z10testInsEltILj2EDv4_jjET0_S1_T1_
-; CHECK-BE: mtvsrwz 0, 5
+; CHECK-BE: mtfprwz 0, 5
; CHECK-BE: xxinsertw 34, 0, 8
%vecins = insertelement <4 x i32> %a, i32 %b, i32 2
ret <4 x i32> %vecins
define <4 x i32> @_Z10testInsEltILj3EDv4_jjET0_S1_T1_(<4 x i32> %a, i32 zeroext %b) {
entry:
; CHECK-LABEL: _Z10testInsEltILj3EDv4_jjET0_S1_T1_
-; CHECK: mtvsrwz 0, 5
+; CHECK: mtfprwz 0, 5
; CHECK: xxinsertw 34, 0, 0
; CHECK-BE-LABEL: _Z10testInsEltILj3EDv4_jjET0_S1_T1_
-; CHECK-BE: mtvsrwz 0, 5
+; CHECK-BE: mtfprwz 0, 5
; CHECK-BE: xxinsertw 34, 0, 12
%vecins = insertelement <4 x i32> %a, i32 %b, i32 3
ret <4 x i32> %vecins
; SLOW-LABEL: zpop_i8_i16:
; SLOW: # %bb.0:
; SLOW-NEXT: clrlwi 5, 3, 24
-; SLOW-NEXT: rlwinm 3, 3, 31, 0, 31
+; SLOW-NEXT: rotlwi 3, 3, 31
; SLOW-NEXT: andi. 3, 3, 85
; SLOW-NEXT: lis 4, 13107
; SLOW-NEXT: subf 3, 3, 5
; SLOW-LABEL: popz_i8_i16:
; SLOW: # %bb.0:
; SLOW-NEXT: clrlwi 5, 3, 24
-; SLOW-NEXT: rlwinm 3, 3, 31, 0, 31
+; SLOW-NEXT: rotlwi 3, 3, 31
; SLOW-NEXT: andi. 3, 3, 85
; SLOW-NEXT: lis 4, 13107
; SLOW-NEXT: subf 3, 3, 5
define i32 @zpop_i8_i32(i8 %x) {
; FAST-LABEL: zpop_i8_i32:
; FAST: # %bb.0:
-; FAST-NEXT: rlwinm 3, 3, 0, 24, 31
+; FAST-NEXT: clrlwi 3, 3, 24
; FAST-NEXT: popcntw 3, 3
; FAST-NEXT: blr
;
; SLOW-LABEL: zpop_i8_i32:
; SLOW: # %bb.0:
; SLOW-NEXT: clrlwi 5, 3, 24
-; SLOW-NEXT: rlwinm 3, 3, 31, 0, 31
+; SLOW-NEXT: rotlwi 3, 3, 31
; SLOW-NEXT: andi. 3, 3, 85
; SLOW-NEXT: lis 4, 13107
; SLOW-NEXT: subf 3, 3, 5
; SLOW-LABEL: popz_i8_32:
; SLOW: # %bb.0:
; SLOW-NEXT: clrlwi 5, 3, 24
-; SLOW-NEXT: rlwinm 3, 3, 31, 0, 31
+; SLOW-NEXT: rotlwi 3, 3, 31
; SLOW-NEXT: andi. 3, 3, 85
; SLOW-NEXT: lis 4, 13107
; SLOW-NEXT: subf 3, 3, 5
define i32 @zpop_i16_i32(i16 %x) {
; FAST-LABEL: zpop_i16_i32:
; FAST: # %bb.0:
-; FAST-NEXT: rlwinm 3, 3, 0, 16, 31
+; FAST-NEXT: clrlwi 3, 3, 16
; FAST-NEXT: popcntw 3, 3
; FAST-NEXT: blr
;
; SLOW-LABEL: zpop_i16_i32:
; SLOW: # %bb.0:
; SLOW-NEXT: clrlwi 5, 3, 16
-; SLOW-NEXT: rlwinm 3, 3, 31, 0, 31
+; SLOW-NEXT: rotlwi 3, 3, 31
; SLOW-NEXT: andi. 3, 3, 21845
; SLOW-NEXT: lis 4, 13107
; SLOW-NEXT: subf 3, 3, 5
; SLOW-LABEL: popz_i16_32:
; SLOW: # %bb.0:
; SLOW-NEXT: clrlwi 5, 3, 16
-; SLOW-NEXT: rlwinm 3, 3, 31, 0, 31
+; SLOW-NEXT: rotlwi 3, 3, 31
; SLOW-NEXT: andi. 3, 3, 21845
; SLOW-NEXT: lis 4, 13107
; SLOW-NEXT: subf 3, 3, 5
; SLOW-LABEL: popa_i16_i64:
; SLOW: # %bb.0:
; SLOW-NEXT: clrlwi 5, 3, 16
-; SLOW-NEXT: rlwinm 3, 3, 31, 0, 31
+; SLOW-NEXT: rotlwi 3, 3, 31
; SLOW-NEXT: andi. 3, 3, 21845
; SLOW-NEXT: lis 4, 13107
; SLOW-NEXT: subf 3, 3, 5
; CHECK-LABEL: @crbitsoff
; CHECK-NO-ISEL-LABEL: @crbitsoff
-; CHECK-DAG: cmplwi {{[0-9]+}}, 3, 0
+; CHECK-DAG: cmplwi 3, 0
; CHECK-DAG: li [[REG2:[0-9]+]], 1
; CHECK-DAG: cntlzw [[REG3:[0-9]+]],
; CHECK: isel [[REG4:[0-9]+]], 0, [[REG2]]
;
; Compare the arguments and return
; No prologue needed.
-; ENABLE: cmpw 0, 3, 4
+; ENABLE: cmpw 3, 4
; ENABLE-NEXT: bgelr 0
;
; Prologue code.
;
; Compare the arguments and jump to exit.
; After the prologue is set.
-; DISABLE: cmpw 0, 3, 4
+; DISABLE: cmpw 3, 4
; DISABLE-NEXT: bge 0, .[[EXIT_LABEL:LBB[0-9_]+]]
;
; Store %a on the stack
; CHECK-LABEL: freqSaveAndRestoreOutsideLoop:
;
; Shrink-wrapping allows to skip the prologue in the else case.
-; ENABLE: cmplwi 0, 3, 0
+; ENABLE: cmplwi 3, 0
; ENABLE: beq 0, .[[ELSE_LABEL:LBB[0-9_]+]]
;
; Prologue code.
; Make sure we save the link register
; CHECK: mflr {{[0-9]+}}
;
-; DISABLE: cmplwi 0, 3, 0
+; DISABLE: cmplwi 3, 0
; DISABLE: beq 0, .[[ELSE_LABEL:LBB[0-9_]+]]
;
; Loop preheader
; restore outside.
; CHECK-LABEL: loopInfoSaveOutsideLoop:
;
-; ENABLE: cmplwi 0, 3, 0
+; ENABLE: cmplwi 3, 0
; ENABLE-NEXT: beq 0, .[[ELSE_LABEL:LBB[0-9_]+]]
;
; Prologue code.
;
; DISABLE: std
; DISABLE-NEXT: std
-; DISABLE: cmplwi 0, 3, 0
+; DISABLE: cmplwi 3, 0
; DISABLE-NEXT: beq 0, .[[ELSE_LABEL:LBB[0-9_]+]]
;
; Loop preheader
; save outside.
; CHECK-LABEL: loopInfoRestoreOutsideLoop:
;
-; ENABLE: cmplwi 0, 3, 0
+; ENABLE: cmplwi 3, 0
; ENABLE-NEXT: beq 0, .[[ELSE_LABEL:LBB[0-9_]+]]
;
; Prologue code.
;
; DISABLE: std
; DISABLE-NEXT: std
-; DISABLE: cmplwi 0, 3, 0
+; DISABLE: cmplwi 3, 0
; DISABLE-NEXT: beq 0, .[[ELSE_LABEL:LBB[0-9_]+]]
;
; CHECK: bl somethingElse
; Check that we handle inline asm correctly.
; CHECK-LABEL: inlineAsm:
;
-; ENABLE: cmplwi 0, 3, 0
+; ENABLE: cmplwi 3, 0
; ENABLE-NEXT: beq 0, .[[ELSE_LABEL:LBB[0-9_]+]]
;
; Prologue code.
; ENABLE-DAG: li [[IV:[0-9]+]], 10
; ENABLE-DAG: std 14, -[[STACK_OFFSET:[0-9]+]](1) # 8-byte Folded Spill
;
-; DISABLE: cmplwi 0, 3, 0
+; DISABLE: cmplwi 3, 0
; DISABLE-NEXT: std 14, -[[STACK_OFFSET:[0-9]+]](1) # 8-byte Folded Spill
; DISABLE-NEXT: beq 0, .[[ELSE_LABEL:LBB[0-9_]+]]
; DISABLE: li [[IV:[0-9]+]], 10
; Check that we handle calls to variadic functions correctly.
; CHECK-LABEL: callVariadicFunc:
;
-; ENABLE: cmplwi 0, 3, 0
+; ENABLE: cmplwi 3, 0
; ENABLE-NEXT: beq 0, .[[ELSE_LABEL:LBB[0-9_]+]]
;
; Prologue code.
; CHECK: mflr {{[0-9]+}}
;
-; DISABLE: cmplwi 0, 3, 0
+; DISABLE: cmplwi 3, 0
; DISABLE-NEXT: beq 0, .[[ELSE_LABEL:LBB[0-9_]+]]
;
; Setup of the varags.
; CHECK-LABEL: noreturn:
; DISABLE: mflr {{[0-9]+}}
;
-; CHECK: cmplwi 0, 3, 0
+; CHECK: cmplwi 3, 0
; CHECK-NEXT: bne{{[-]?}} 0, .[[ABORT:LBB[0-9_]+]]
;
; CHECK: li 3, 42
; CHECK-NOT: li
; CHECK: cmpd {{c?r?(0, )?}}r3, r4
; CHECK-NEXT: setb r3, cr0
-; CHECK-NOT: subfc
+; CHECK-NOT: subc
; CHECK-NOT: adde
; CHECK-NOT: xori
; CHECK-NOT: isel
; CHECK-PWR8-DAG: rldicl
; CHECK-PWR8-DAG: li
; CHECK-PWR8-DAG: cmpd
-; CHECK-PWR8-DAG: subfc
+; CHECK-PWR8-DAG: subc
; CHECK-PWR8-DAG: adde
; CHECK-PWR8-DAG: xori
; CHECK-PWR8: isel
; CHECK-NOT: li
; CHECK: cmpd {{c?r?(0, )?}}r3, r4
; CHECK-NEXT: setb r3, cr0
-; CHECK-NOT: subfc
+; CHECK-NOT: subc
; CHECK-NOT: adde
; CHECK-NOT: xori
; CHECK-NOT: isel
; CHECK-PWR8-DAG: rldicl
; CHECK-PWR8-DAG: li
; CHECK-PWR8-DAG: cmpd
-; CHECK-PWR8-DAG: subfc
+; CHECK-PWR8-DAG: subc
; CHECK-PWR8-DAG: adde
; CHECK-PWR8-DAG: xori
; CHECK-PWR8: isel
; CHECK-NOT: li
; CHECK: cmpd {{c?r?(0, )?}}r3, r4
; CHECK-NEXT: setb r3, cr0
-; CHECK-NOT: subfc
+; CHECK-NOT: subc
; CHECK-NOT: adde
; CHECK-NOT: xori
; CHECK-NOT: isel
; CHECK-PWR8-DAG: rldicl
; CHECK-PWR8-DAG: li
; CHECK-PWR8-DAG: cmpd
-; CHECK-PWR8-DAG: subfc
+; CHECK-PWR8-DAG: subc
; CHECK-PWR8-DAG: adde
; CHECK-PWR8-DAG: xori
; CHECK-PWR8: isel
; CHECK-NOT: li
; CHECK: cmpd {{c?r?(0, )?}}r3, r4
; CHECK-NEXT: setb r3, cr0
-; CHECK-NOT: subfc
+; CHECK-NOT: subc
; CHECK-NOT: adde
; CHECK-NOT: xori
; CHECK-NOT: isel
; CHECK-PWR8-DAG: rldicl
; CHECK-PWR8-DAG: li
; CHECK-PWR8-DAG: cmpd
-; CHECK-PWR8-DAG: subfc
+; CHECK-PWR8-DAG: subc
; CHECK-PWR8-DAG: adde
; CHECK-PWR8-DAG: xori
; CHECK-PWR8: isel
; CHECK-NOT: li
; CHECK: cmpd {{c?r?(0, )?}}r3, r4
; CHECK-NEXT: setb r3, cr0
-; CHECK-NOT: subfc
+; CHECK-NOT: subc
; CHECK-NOT: adde
; CHECK-NOT: xori
; CHECK-NOT: neg
; CHECK-PWR8-DAG: rldicl
; CHECK-PWR8-DAG: li
; CHECK-PWR8-DAG: cmpd
-; CHECK-PWR8-DAG: subfc
+; CHECK-PWR8-DAG: subc
; CHECK-PWR8-DAG: adde
; CHECK-PWR8-DAG: xori
; CHECK-PWR8-DAG: neg
; CHECK-NOT: li
; CHECK: cmpd {{c?r?(0, )?}}r3, r4
; CHECK-NEXT: setb r3, cr0
-; CHECK-NOT: subfc
+; CHECK-NOT: subc
; CHECK-NOT: adde
; CHECK-NOT: xori
; CHECK-NOT: neg
; CHECK-PWR8-DAG: rldicl
; CHECK-PWR8-DAG: li
; CHECK-PWR8-DAG: cmpd
-; CHECK-PWR8-DAG: subfc
+; CHECK-PWR8-DAG: subc
; CHECK-PWR8-DAG: adde
; CHECK-PWR8-DAG: xori
; CHECK-PWR8-DAG: neg
; CHECK-NOT: li
; CHECK: cmpd {{c?r?(0, )?}}r3, r4
; CHECK-NEXT: setb r3, cr0
-; CHECK-NOT: subfc
+; CHECK-NOT: subc
; CHECK-NOT: adde
; CHECK-NOT: xori
; CHECK-NOT: neg
; CHECK-PWR8-DAG: rldicl
; CHECK-PWR8-DAG: li
; CHECK-PWR8-DAG: cmpd
-; CHECK-PWR8-DAG: subfc
+; CHECK-PWR8-DAG: subc
; CHECK-PWR8-DAG: adde
; CHECK-PWR8-DAG: xori
; CHECK-PWR8-DAG: neg
; CHECK-NOT: li
; CHECK: cmpd {{c?r?(0, )?}}r3, r4
; CHECK-NEXT: setb r3, cr0
-; CHECK-NOT: subfc
+; CHECK-NOT: subc
; CHECK-NOT: adde
; CHECK-NOT: xori
; CHECK-NOT: neg
; CHECK-PWR8-DAG: rldicl
; CHECK-PWR8-DAG: li
; CHECK-PWR8-DAG: cmpd
-; CHECK-PWR8-DAG: subfc
+; CHECK-PWR8-DAG: subc
; CHECK-PWR8-DAG: adde
; CHECK-PWR8-DAG: xori
; CHECK-PWR8-DAG: neg
; CHECK-NOT: li
; CHECK: cmpd {{c?r?(0, )?}}r3, r4
; CHECK-NEXT: setb r3, cr0
-; CHECK-NOT: subfc
+; CHECK-NOT: subc
; CHECK-NOT: adde
; CHECK-NOT: xori
; CHECK-NOT: isel
; CHECK: blr
; CHECK-PWR8-LABEL: setb29
; CHECK-PWR8-DAG: cmpd
-; CHECK-PWR8-DAG: subfc
+; CHECK-PWR8-DAG: subc
; CHECK-PWR8-DAG: adde
; CHECK-PWR8: isel
; CHECK-PWR8: blr
; CHECK-NOT: li
; CHECK: cmpld {{c?r?(0, )?}}r3, r4
; CHECK-NEXT: setb r3, cr0
-; CHECK-NOT: subfc
+; CHECK-NOT: subc
; CHECK-NOT: subfe
; CHECK-NOT: neg
; CHECK-NOT: isel
; CHECK: blr
; CHECK-PWR8-LABEL: setbud1
-; CHECK-PWR8-DAG: subfc
+; CHECK-PWR8-DAG: subc
; CHECK-PWR8-DAG: subfe
; CHECK-PWR8-DAG: cmpld
; CHECK-PWR8-DAG: neg
%t4 = select i1 %t1, i64 1, i64 %t3
ret i64 %t4
; CHECK-LABEL: setbuh:
-; CHECK-DAG: rlwinm [[RA:r[0-9]+]], r3, 0, 16, 31
-; CHECK-DAG: rlwinm [[RB:r[0-9]+]], r4, 0, 16, 31
+; CHECK-DAG: clrlwi [[RA:r[0-9]+]], r3, 16
+; CHECK-DAG: clrlwi [[RB:r[0-9]+]], r4, 16
; CHECK-NOT: li
; CHECK-NOT: xor
; CHECK: cmplw {{c?r?(0, )?}}[[RA]], [[RB]]
; CHECK-NOT: isel
; CHECK: blr
; CHECK-PWR8-LABEL: setbuh
-; CHECK-PWR8: rlwinm
-; CHECK-PWR8: rlwinm
+; CHECK-PWR8: clrlwi
+; CHECK-PWR8: clrlwi
; CHECK-PWR8-DAG: cmplw
; CHECK-PWR8-DAG: cntlzw
; CHECK-PWR8: srwi
%t4 = select i1 %t1, i64 1, i64 %t3
ret i64 %t4
; CHECK-LABEL: setbuc:
-; CHECK-DAG: rlwinm [[RA:r[0-9]+]], r3, 0, 24, 31
-; CHECK-DAG: rlwinm [[RB:r[0-9]+]], r4, 0, 24, 31
+; CHECK-DAG: clrlwi [[RA:r[0-9]+]], r3, 24
+; CHECK-DAG: clrlwi [[RB:r[0-9]+]], r4, 24
; CHECK-NOT: li
; CHECK-NOT: clrldi
; CHECK: cmplw {{c?r?(0, )?}}[[RA]], [[RB]]
; CHECK-NOT: isel
; CHECK: blr
; CHECK-PWR8-LABEL: setbuc
-; CHECK-PWR8: rlwinm
-; CHECK-PWR8: rlwinm
+; CHECK-PWR8: clrlwi
+; CHECK-PWR8: clrlwi
; CHECK-PWR8-DAG: clrldi
; CHECK-PWR8-DAG: clrldi
; CHECK-PWR8-DAG: cmplw
; LE-NEXT: xxsldwi 1, 34, 34, 1
; LE-NEXT: mfvsrwz 4, 35
; LE-NEXT: xxsldwi 4, 34, 34, 3
-; LE-NEXT: mtvsrd 2, 3
-; LE-NEXT: mfvsrwz 3, 0
+; LE-NEXT: mtfprd 2, 3
+; LE-NEXT: mffprwz 3, 0
; LE-NEXT: xxswapd 0, 35
-; LE-NEXT: mtvsrd 3, 4
+; LE-NEXT: mtfprd 3, 4
; LE-NEXT: xxsldwi 5, 35, 35, 1
-; LE-NEXT: mfvsrwz 4, 1
+; LE-NEXT: mffprwz 4, 1
; LE-NEXT: xxsldwi 7, 35, 35, 3
-; LE-NEXT: mtvsrd 1, 3
+; LE-NEXT: mtfprd 1, 3
; LE-NEXT: xxswapd 33, 3
-; LE-NEXT: mfvsrwz 3, 4
-; LE-NEXT: mtvsrd 4, 4
+; LE-NEXT: mffprwz 3, 4
+; LE-NEXT: mtfprd 4, 4
; LE-NEXT: xxswapd 34, 1
-; LE-NEXT: mfvsrwz 4, 0
-; LE-NEXT: mtvsrd 0, 3
+; LE-NEXT: mffprwz 4, 0
+; LE-NEXT: mtfprd 0, 3
; LE-NEXT: xxswapd 35, 4
-; LE-NEXT: mfvsrwz 3, 5
-; LE-NEXT: mtvsrd 6, 4
+; LE-NEXT: mffprwz 3, 5
+; LE-NEXT: mtfprd 6, 4
; LE-NEXT: xxswapd 36, 0
-; LE-NEXT: mtvsrd 1, 3
-; LE-NEXT: mfvsrwz 3, 7
+; LE-NEXT: mtfprd 1, 3
+; LE-NEXT: mffprwz 3, 7
; LE-NEXT: xxswapd 37, 6
; LE-NEXT: vmrglh 2, 3, 2
; LE-NEXT: xxswapd 35, 2
-; LE-NEXT: mtvsrd 2, 3
+; LE-NEXT: mtfprd 2, 3
; LE-NEXT: xxswapd 32, 1
; LE-NEXT: addis 3, 2, .LCPI0_1@toc@ha
; LE-NEXT: addi 3, 3, .LCPI0_1@toc@l
; BE-NEXT: mfvsrwz 3, 35
; BE-NEXT: xxsldwi 1, 35, 35, 1
; BE-NEXT: sldi 3, 3, 48
-; BE-NEXT: mfvsrwz 4, 0
+; BE-NEXT: mffprwz 4, 0
; BE-NEXT: xxsldwi 0, 35, 35, 3
; BE-NEXT: mtvsrd 36, 3
-; BE-NEXT: mfvsrwz 3, 1
+; BE-NEXT: mffprwz 3, 1
; BE-NEXT: sldi 4, 4, 48
; BE-NEXT: xxswapd 1, 34
; BE-NEXT: mtvsrd 35, 4
; BE-NEXT: mfvsrwz 4, 34
; BE-NEXT: sldi 3, 3, 48
; BE-NEXT: mtvsrd 37, 3
-; BE-NEXT: mfvsrwz 3, 0
+; BE-NEXT: mffprwz 3, 0
; BE-NEXT: sldi 4, 4, 48
; BE-NEXT: xxsldwi 0, 34, 34, 1
; BE-NEXT: vmrghh 3, 5, 3
; BE-NEXT: mtvsrd 37, 4
; BE-NEXT: sldi 3, 3, 48
-; BE-NEXT: mfvsrwz 4, 1
+; BE-NEXT: mffprwz 4, 1
; BE-NEXT: xxsldwi 1, 34, 34, 3
; BE-NEXT: mtvsrd 34, 3
-; BE-NEXT: mfvsrwz 3, 0
+; BE-NEXT: mffprwz 3, 0
; BE-NEXT: sldi 4, 4, 48
; BE-NEXT: mtvsrd 32, 4
-; BE-NEXT: mfvsrwz 4, 1
+; BE-NEXT: mffprwz 4, 1
; BE-NEXT: sldi 3, 3, 48
; BE-NEXT: mtvsrd 33, 3
; BE-NEXT: sldi 3, 4, 48
; CHECK-NEXT: and 3, 3, 4
; CHECK-NEXT: or 3, 3, 5
; CHECK-NEXT: rldicl 4, 3, 32, 32
-; CHECK-NEXT: rlwinm 5, 3, 24, 0, 31
-; CHECK-NEXT: rlwinm 6, 4, 24, 0, 31
+; CHECK-NEXT: rotlwi 5, 3, 24
+; CHECK-NEXT: rotlwi 6, 4, 24
; CHECK-NEXT: rlwimi 5, 3, 8, 8, 15
; CHECK-NEXT: rlwimi 5, 3, 8, 24, 31
; CHECK-NEXT: rlwimi 6, 4, 8, 8, 15
; CHECK: subfze 6, 4
; CHECK: sradi 7, 6, 63
; CHECK: srad 6, 6, 3
-; CHECK: subfc 5, 5, 7
+; CHECK: subc 5, 7, 5
; CHECK: subfe 5, 4, 6
; CHECK: sradi 5, 5, 63
; MSSA: subfic 5, 3, 0
; MSSA: subfze 5, 4
; MSSA: sradi 5, 5, 63
-; MSSA: subfc 3, 3, 5
+; MSSA: subc 3, 5, 3
; MSSA: subfe 3, 4, 5
; MSSA: sradi 3, 3, 63
; MSSA: std 3, 0(3)
; CHECK-NEXT: sradi r4, r3, 63
; CHECK-NEXT: mulhdu r3, r3, r5
; CHECK-NEXT: maddld r6, r4, r5, r3
-; CHECK-NEXT: crnor 4*cr5+gt, eq, eq
+; CHECK-NEXT: crnot 4*cr5+gt, eq
; CHECK-NEXT: cmpld r6, r3
; CHECK-NEXT: mulld r3, r4, r5
; CHECK-NEXT: cmpldi cr1, r3, 0
; CHECK-NEXT: lxsihzx v2, r6, r7
; CHECK-NEXT: lxsihzx v4, r3, r4
; CHECK-NEXT: li r6, 0
-; CHECK-NEXT: mtvsrd f0, r6
+; CHECK-NEXT: mtfprd f0, r6
; CHECK-NEXT: vsplth v4, v4, 3
; CHECK-NEXT: xxswapd v3, vs0
; CHECK-NEXT: vsplth v2, v2, 3
; CHECK-NEXT: xxspltw v3, v2, 2
; CHECK-NEXT: vadduwm v2, v2, v3
; CHECK-NEXT: vextuwrx r3, r3, v2
-; CHECK-NEXT: cmpw cr0, r3, r5
+; CHECK-NEXT: cmpw r3, r5
; CHECK-NEXT: bgelr+ cr0
; CHECK-NEXT: # %bb.1: # %if.then
;
; P9BE-NEXT: xxspltw v3, v2, 1
; P9BE-NEXT: vadduwm v2, v2, v3
; P9BE-NEXT: vextuwlx r3, r3, v2
-; P9BE-NEXT: cmpw cr0, r3, r5
+; P9BE-NEXT: cmpw r3, r5
; P9BE-NEXT: bgelr+ cr0
; P9BE-NEXT: # %bb.1: # %if.then
entry:
; CHECK-NEXT: add r6, r3, r4
; CHECK-NEXT: lxsibzx v2, r3, r4
; CHECK-NEXT: li r3, 0
-; CHECK-NEXT: mtvsrd f0, r3
+; CHECK-NEXT: mtfprd f0, r3
; CHECK-NEXT: li r3, 8
; CHECK-NEXT: lxsibzx v5, r6, r3
; CHECK-NEXT: xxswapd v3, vs0
; CHECK-NEXT: xxspltw v3, v2, 2
; CHECK-NEXT: vadduwm v2, v2, v3
; CHECK-NEXT: vextuwrx r3, r3, v2
-; CHECK-NEXT: cmpw cr0, r3, r5
+; CHECK-NEXT: cmpw r3, r5
; CHECK-NEXT: bgelr+ cr0
; CHECK-NEXT: # %bb.1: # %if.then
;
; P9BE-NEXT: xxspltw v3, v2, 1
; P9BE-NEXT: vadduwm v2, v2, v3
; P9BE-NEXT: vextuwlx r3, r3, v2
-; P9BE-NEXT: cmpw cr0, r3, r5
+; P9BE-NEXT: cmpw r3, r5
; P9BE-NEXT: bgelr+ cr0
; P9BE-NEXT: # %bb.1: # %if.then
entry:
; CHECK-DAG: qvlfiwzx [[REG2:[0-9]+]],
; CHECK-DAG: qvfcfidu [[REG3:[0-9]+]], [[REG2]]
; CHECK: qvfcmpeq [[REG4:[0-9]+]], [[REG3]], [[REG1]]
-; CHECK: qvflogical 1, 1, [[REG4]], 1
+; CHECK: qvfand 1, 1, [[REG4]]
; CHECK: blr
}
; CHECK-DAG: qvlfiwzx [[REG2:[0-9]+]],
; CHECK-DAG: qvfcfidu [[REG3:[0-9]+]], [[REG2]]
; CHECK: qvfcmpeq [[REG4:[0-9]+]], [[REG3]], [[REG1]]
-; CHECK: qvflogical 1, 1, [[REG4]], 1
+; CHECK: qvfand 1, 1, [[REG4]]
; CHECK: blr
}
; CHECK-P9-NEXT: li r3, 0
; CHECK-P9-NEXT: blr
; CHECK-P9-NEXT: .LBB0_4: # %lor.lhs.false
-; CHECK-P9-NEXT: cmplwi cr0, r4, 0
+; CHECK-P9-NEXT: cmplwi r4, 0
; CHECK-P9-NEXT: bne cr0, .LBB0_2
; CHECK-P9-NEXT: .LBB0_5: # %cleanup16
; CHECK-P9-NEXT: mr r3, r5
define i8 @unsigned_sat_constant_i8_using_cmp_sum(i8 %x) {
; CHECK-LABEL: unsigned_sat_constant_i8_using_cmp_sum:
; CHECK: # %bb.0:
-; CHECK-NEXT: rlwinm 3, 3, 0, 24, 31
+; CHECK-NEXT: clrlwi 3, 3, 24
; CHECK-NEXT: addi 3, 3, 42
; CHECK-NEXT: andi. 4, 3, 256
; CHECK-NEXT: li 4, -1
define i16 @unsigned_sat_constant_i16_using_cmp_sum(i16 %x) {
; CHECK-LABEL: unsigned_sat_constant_i16_using_cmp_sum:
; CHECK: # %bb.0:
-; CHECK-NEXT: rlwinm 3, 3, 0, 16, 31
+; CHECK-NEXT: clrlwi 3, 3, 16
; CHECK-NEXT: addi 3, 3, 42
; CHECK-NEXT: andis. 4, 3, 1
; CHECK-NEXT: li 4, -1
; CHECK: # %bb.0:
; CHECK-NEXT: addi 5, 3, 42
; CHECK-NEXT: li 4, -1
-; CHECK-NEXT: cmplw 0, 5, 3
+; CHECK-NEXT: cmplw 5, 3
; CHECK-NEXT: isel 3, 4, 5, 0
; CHECK-NEXT: blr
%a = add i32 %x, 42
; CHECK: # %bb.0:
; CHECK-NEXT: li 4, -43
; CHECK-NEXT: addi 5, 3, 42
-; CHECK-NEXT: cmplw 0, 3, 4
+; CHECK-NEXT: cmplw 3, 4
; CHECK-NEXT: li 3, -1
; CHECK-NEXT: isel 3, 3, 5, 1
; CHECK-NEXT: blr
define i8 @unsigned_sat_variable_i8_using_cmp_sum(i8 %x, i8 %y) {
; CHECK-LABEL: unsigned_sat_variable_i8_using_cmp_sum:
; CHECK: # %bb.0:
-; CHECK-NEXT: rlwinm 4, 4, 0, 24, 31
-; CHECK-NEXT: rlwinm 3, 3, 0, 24, 31
+; CHECK-NEXT: clrlwi 4, 4, 24
+; CHECK-NEXT: clrlwi 3, 3, 24
; CHECK-NEXT: add 3, 3, 4
; CHECK-NEXT: andi. 4, 3, 256
; CHECK-NEXT: li 4, -1
define i16 @unsigned_sat_variable_i16_using_cmp_sum(i16 %x, i16 %y) {
; CHECK-LABEL: unsigned_sat_variable_i16_using_cmp_sum:
; CHECK: # %bb.0:
-; CHECK-NEXT: rlwinm 4, 4, 0, 16, 31
-; CHECK-NEXT: rlwinm 3, 3, 0, 16, 31
+; CHECK-NEXT: clrlwi 4, 4, 16
+; CHECK-NEXT: clrlwi 3, 3, 16
; CHECK-NEXT: add 3, 3, 4
; CHECK-NEXT: andis. 4, 3, 1
; CHECK-NEXT: li 4, -1
; CHECK: # %bb.0:
; CHECK-NEXT: add 4, 3, 4
; CHECK-NEXT: li 5, -1
-; CHECK-NEXT: cmplw 0, 4, 3
+; CHECK-NEXT: cmplw 4, 3
; CHECK-NEXT: isel 3, 5, 4, 0
; CHECK-NEXT: blr
%a = add i32 %x, %y
; CHECK-LABEL: @testi32slt
; CHECK-NO-ISEL-LABEL: @testi32slt
-; CHECK-DAG: cmpw {{[0-9]+}}, 5, 6
+; CHECK-DAG: cmpw 5, 6
; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4
; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
; CHECK: isel 3, 7, 8, [[REG1]]
ret i32 %cond
; CHECK-NO-ISEL-LABEL: @testi32ult
-; CHECK-DAG: cmpw {{[0-9]+}}, 5, 6
+; CHECK-DAG: cmpw 5, 6
; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4
; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
; CHECK: isel 3, 7, 8, [[REG1]]
; CHECK-LABEL: @testi32sle
; CHECK-NO-ISEL-LABEL: @testi32sle
-; CHECK-DAG: cmpw {{[0-9]+}}, 5, 6
+; CHECK-DAG: cmpw 5, 6
; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4
; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
; CHECK: isel 3, 7, 8, [[REG1]]
; CHECK-LABEL: @testi32ule
; CHECK-NO-ISEL-LABEL: @testi32ule
-; CHECK-DAG: cmpw {{[0-9]+}}, 5, 6
+; CHECK-DAG: cmpw 5, 6
; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4
; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
; CHECK: isel 3, 7, 8, [[REG1]]
; CHECK-LABEL: @testi32eq
; CHECK-NO-ISEL-LABEL: @testi32eq
-; CHECK-DAG: cmpw {{[0-9]+}}, 5, 6
+; CHECK-DAG: cmpw 5, 6
; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4
; CHECK: creqv [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
; CHECK: isel 3, 7, 8, [[REG1]]
; CHECK-LABEL: @testi32sge
; CHECK-NO-ISEL-LABEL: @testi32sge
-; CHECK-DAG: cmpw {{[0-9]+}}, 5, 6
+; CHECK-DAG: cmpw 5, 6
; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4
; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
; CHECK: isel 3, 7, 8, [[REG1]]
; CHECK-LABEL: @testi32uge
; CHECK-NO-ISEL-LABEL: @testi32uge
-; CHECK-DAG: cmpw {{[0-9]+}}, 5, 6
+; CHECK-DAG: cmpw 5, 6
; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4
; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
; CHECK: isel 3, 7, 8, [[REG1]]
; CHECK-LABEL: @testi32sgt
; CHECK-NO-ISEL-LABEL: @testi32sgt
-; CHECK-DAG: cmpw {{[0-9]+}}, 5, 6
+; CHECK-DAG: cmpw 5, 6
; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4
; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
; CHECK: isel 3, 7, 8, [[REG1]]
; CHECK-LABEL: @testi32ugt
; CHECK-NO-ISEL-LABEL: @testi32ugt
-; CHECK-DAG: cmpw {{[0-9]+}}, 5, 6
+; CHECK-DAG: cmpw 5, 6
; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4
; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
; CHECK: isel 3, 7, 8, [[REG1]]
; CHECK-LABEL: @testi32ne
; CHECK-NO-ISEL-LABEL: @testi32ne
-; CHECK-DAG: cmpw {{[0-9]+}}, 5, 6
+; CHECK-DAG: cmpw 5, 6
; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4
; CHECK: crxor [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
; CHECK: isel 3, 7, 8, [[REG1]]
define i8 @shl_constant_sel_constants(i1 %cond) {
; ALL-LABEL: shl_constant_sel_constants:
; ALL: # %bb.0:
-; ALL-NEXT: rlwinm 3, 3, 0, 31, 31
+; ALL-NEXT: clrlwi 3, 3, 31
; ALL-NEXT: li 4, 1
; ALL-NEXT: subfic 3, 3, 3
; ALL-NEXT: slw 3, 4, 3
define i8 @lshr_constant_sel_constants(i1 %cond) {
; ALL-LABEL: lshr_constant_sel_constants:
; ALL: # %bb.0:
-; ALL-NEXT: rlwinm 3, 3, 0, 31, 31
+; ALL-NEXT: clrlwi 3, 3, 31
; ALL-NEXT: li 4, 64
; ALL-NEXT: subfic 3, 3, 3
; ALL-NEXT: srw 3, 4, 3
define i8 @ashr_constant_sel_constants(i1 %cond) {
; ALL-LABEL: ashr_constant_sel_constants:
; ALL: # %bb.0:
-; ALL-NEXT: rlwinm 3, 3, 0, 31, 31
+; ALL-NEXT: clrlwi 3, 3, 31
; ALL-NEXT: li 4, -128
; ALL-NEXT: subfic 3, 3, 3
; ALL-NEXT: sraw 3, 4, 3
; CHECK-LABEL: all_sign_bits_clear_branch:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: or 3, 3, 4
-; CHECK-NEXT: cmpwi 0, 3, 0
+; CHECK-NEXT: cmpwi 3, 0
; CHECK-NEXT: blt 0, .LBB9_2
; CHECK-NEXT: # %bb.1: # %bb1
; CHECK-NEXT: li 3, 4
; CHECK-LABEL: all_bits_set_branch:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: and 3, 3, 4
-; CHECK-NEXT: cmpwi 0, 3, -1
+; CHECK-NEXT: cmpwi 3, -1
; CHECK-NEXT: bne 0, .LBB10_2
; CHECK-NEXT: # %bb.1: # %bb1
; CHECK-NEXT: li 3, 4
; CHECK-LABEL: all_sign_bits_set_branch:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: and 3, 3, 4
-; CHECK-NEXT: cmpwi 0, 3, -1
+; CHECK-NEXT: cmpwi 3, -1
; CHECK-NEXT: bgt 0, .LBB11_2
; CHECK-NEXT: # %bb.1: # %bb1
; CHECK-NEXT: li 3, 4
; CHECK-LABEL: any_sign_bits_set_branch:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: or 3, 3, 4
-; CHECK-NEXT: cmpwi 0, 3, -1
+; CHECK-NEXT: cmpwi 3, -1
; CHECK-NEXT: bgt 0, .LBB13_2
; CHECK-NEXT: # %bb.1: # %bb1
; CHECK-NEXT: li 3, 4
; CHECK-LABEL: any_bits_clear_branch:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: and 3, 3, 4
-; CHECK-NEXT: cmpwi 0, 3, -1
+; CHECK-NEXT: cmpwi 3, -1
; CHECK-NEXT: beq 0, .LBB14_2
; CHECK-NEXT: # %bb.1: # %bb1
; CHECK-NEXT: li 3, 4
; CHECK-LABEL: any_sign_bits_clear_branch:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: and 3, 3, 4
-; CHECK-NEXT: cmpwi 0, 3, 0
+; CHECK-NEXT: cmpwi 3, 0
; CHECK-NEXT: blt 0, .LBB15_2
; CHECK-NEXT: # %bb.1: # %bb1
; CHECK-NEXT: li 3, 4
define i8 @test000(i8 %a, i8 %b) {
; CHECK-LABEL: test000:
; CHECK: # %bb.0:
-; CHECK-NEXT: rlwinm 4, 4, 0, 29, 31
+; CHECK-NEXT: clrlwi 4, 4, 29
; CHECK-NEXT: slw 3, 3, 4
; CHECK-NEXT: blr
%rem = and i8 %b, 7
define i16 @test001(i16 %a, i16 %b) {
; CHECK-LABEL: test001:
; CHECK: # %bb.0:
-; CHECK-NEXT: rlwinm 4, 4, 0, 28, 31
+; CHECK-NEXT: clrlwi 4, 4, 28
; CHECK-NEXT: slw 3, 3, 4
; CHECK-NEXT: blr
%rem = and i16 %b, 15
define i32 @test002(i32 %a, i32 %b) {
; CHECK-LABEL: test002:
; CHECK: # %bb.0:
-; CHECK-NEXT: rlwinm 4, 4, 0, 27, 31
+; CHECK-NEXT: clrlwi 4, 4, 27
; CHECK-NEXT: slw 3, 3, 4
; CHECK-NEXT: blr
%rem = and i32 %b, 31
define i64 @test003(i64 %a, i64 %b) {
; CHECK-LABEL: test003:
; CHECK: # %bb.0:
-; CHECK-NEXT: rlwinm 4, 4, 0, 26, 31
+; CHECK-NEXT: clrlwi 4, 4, 26
; CHECK-NEXT: sld 3, 3, 4
; CHECK-NEXT: blr
%rem = and i64 %b, 63
define i8 @test100(i8 %a, i8 %b) {
; CHECK-LABEL: test100:
; CHECK: # %bb.0:
-; CHECK-NEXT: rlwinm 3, 3, 0, 24, 31
-; CHECK-NEXT: rlwinm 4, 4, 0, 29, 31
+; CHECK-NEXT: clrlwi 3, 3, 24
+; CHECK-NEXT: clrlwi 4, 4, 29
; CHECK-NEXT: srw 3, 3, 4
; CHECK-NEXT: blr
%rem = and i8 %b, 7
define i16 @test101(i16 %a, i16 %b) {
; CHECK-LABEL: test101:
; CHECK: # %bb.0:
-; CHECK-NEXT: rlwinm 3, 3, 0, 16, 31
-; CHECK-NEXT: rlwinm 4, 4, 0, 28, 31
+; CHECK-NEXT: clrlwi 3, 3, 16
+; CHECK-NEXT: clrlwi 4, 4, 28
; CHECK-NEXT: srw 3, 3, 4
; CHECK-NEXT: blr
%rem = and i16 %b, 15
define i32 @test102(i32 %a, i32 %b) {
; CHECK-LABEL: test102:
; CHECK: # %bb.0:
-; CHECK-NEXT: rlwinm 4, 4, 0, 27, 31
+; CHECK-NEXT: clrlwi 4, 4, 27
; CHECK-NEXT: srw 3, 3, 4
; CHECK-NEXT: blr
%rem = and i32 %b, 31
define i64 @test103(i64 %a, i64 %b) {
; CHECK-LABEL: test103:
; CHECK: # %bb.0:
-; CHECK-NEXT: rlwinm 4, 4, 0, 26, 31
+; CHECK-NEXT: clrlwi 4, 4, 26
; CHECK-NEXT: srd 3, 3, 4
; CHECK-NEXT: blr
%rem = and i64 %b, 63
; CHECK-LABEL: test200:
; CHECK: # %bb.0:
; CHECK-NEXT: extsb 3, 3
-; CHECK-NEXT: rlwinm 4, 4, 0, 29, 31
+; CHECK-NEXT: clrlwi 4, 4, 29
; CHECK-NEXT: sraw 3, 3, 4
; CHECK-NEXT: blr
%rem = and i8 %b, 7
; CHECK-LABEL: test201:
; CHECK: # %bb.0:
; CHECK-NEXT: extsh 3, 3
-; CHECK-NEXT: rlwinm 4, 4, 0, 28, 31
+; CHECK-NEXT: clrlwi 4, 4, 28
; CHECK-NEXT: sraw 3, 3, 4
; CHECK-NEXT: blr
%rem = and i16 %b, 15
define i32 @test202(i32 %a, i32 %b) {
; CHECK-LABEL: test202:
; CHECK: # %bb.0:
-; CHECK-NEXT: rlwinm 4, 4, 0, 27, 31
+; CHECK-NEXT: clrlwi 4, 4, 27
; CHECK-NEXT: sraw 3, 3, 4
; CHECK-NEXT: blr
%rem = and i32 %b, 31
define i64 @test203(i64 %a, i64 %b) {
; CHECK-LABEL: test203:
; CHECK: # %bb.0:
-; CHECK-NEXT: rlwinm 4, 4, 0, 26, 31
+; CHECK-NEXT: clrlwi 4, 4, 26
; CHECK-NEXT: srad 3, 3, 4
; CHECK-NEXT: blr
%rem = and i64 %b, 63
; CHECK-LABEL: sel_ifpos_tval_bigger:
; CHECK: # %bb.0:
; CHECK-NEXT: li 4, 41
-; CHECK-NEXT: cmpwi 0, 3, -1
+; CHECK-NEXT: cmpwi 3, -1
; CHECK-NEXT: li 3, 42
; CHECK-NEXT: isel 3, 3, 4, 1
; CHECK-NEXT: blr
; CHECK-LABEL: sel_ifpos_fval_bigger:
; CHECK: # %bb.0:
; CHECK-NEXT: li 4, 42
-; CHECK-NEXT: cmpwi 0, 3, -1
+; CHECK-NEXT: cmpwi 3, -1
; CHECK-NEXT: li 3, 41
; CHECK-NEXT: isel 3, 3, 4, 1
; CHECK-NEXT: blr
; CHECK-LABEL: sel_ifneg_tval_bigger:
; CHECK: # %bb.0:
; CHECK-NEXT: li 4, 41
-; CHECK-NEXT: cmpwi 0, 3, 0
+; CHECK-NEXT: cmpwi 3, 0
; CHECK-NEXT: li 3, 42
; CHECK-NEXT: isel 3, 3, 4, 0
; CHECK-NEXT: blr
; CHECK-LABEL: sel_ifneg_fval_bigger:
; CHECK: # %bb.0:
; CHECK-NEXT: li 4, 42
-; CHECK-NEXT: cmpwi 0, 3, 0
+; CHECK-NEXT: cmpwi 3, 0
; CHECK-NEXT: li 3, 41
; CHECK-NEXT: isel 3, 3, 4, 0
; CHECK-NEXT: blr
define void @test(i32 zeroext %parts) {
; CHECK-LABEL: test:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: cmplwi 0, 3, 1
+; CHECK-NEXT: cmplwi 3, 1
; CHECK-NEXT: bnelr+ 0
; CHECK-NEXT: # %bb.1: # %test2.exit.us.unr-lcssa
; CHECK-NEXT: ld 3, 0(3)
; CHECK-NEXT: lwz 3, 0(3)
; CHECK-NEXT: addi 3, 3, -1
; CHECK-NEXT: clrldi 4, 3, 32
-; CHECK-NEXT: cmplwi 0, 3, 1
+; CHECK-NEXT: cmplwi 3, 1
; CHECK-NEXT: li 3, 1
; CHECK-NEXT: isel 3, 4, 3, 1
; CHECK-NEXT: li 4, 2
define void @p9_setb_spill() {
; CHECK-P9-LABEL: p9_setb_spill:
; CHECK-P9: # %bb.1: # %if.then
-; CHECK-P9-DAG: crnor 4*cr[[CREG:.*]]+lt, eq, eq
+; CHECK-P9-DAG: crnot 4*cr[[CREG:.*]]+lt, eq
; CHECK-P9-DAG: setb [[REG1:.*]], cr[[CREG]]
; CHECK-P9-DAG: stw [[REG1]]
; CHECK-P9: blr
;
; CHECK-P8-LABEL: p9_setb_spill:
; CHECK-P8: # %bb.1: # %if.then
-; CHECK-P8-DAG: crnor 4*cr[[CREG2:.*]]+lt, eq, eq
+; CHECK-P8-DAG: crnot 4*cr[[CREG2:.*]]+lt, eq
; CHECK-P8-DAG: mfocrf [[REG2:.*]],
; CHECK-P8-DAG: rlwinm [[REG2]], [[REG2]]
; CHECK-P8-DAG: stw [[REG2]]
; P9LE-NEXT: lis r5, 31710
; P9LE-NEXT: mulli r4, r4, 95
; P9LE-NEXT: subf r3, r4, r3
-; P9LE-NEXT: mtvsrd f0, r3
+; P9LE-NEXT: mtfprd f0, r3
; P9LE-NEXT: li r3, 2
; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: extsh r4, r3
; P9LE-NEXT: mulli r4, r4, -124
; P9LE-NEXT: subf r3, r4, r3
; P9LE-NEXT: xxswapd v3, vs0
-; P9LE-NEXT: mtvsrd f0, r3
+; P9LE-NEXT: mtfprd f0, r3
; P9LE-NEXT: li r3, 4
; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: extsh r4, r3
; P9LE-NEXT: mulli r4, r4, 98
; P9LE-NEXT: subf r3, r4, r3
; P9LE-NEXT: xxswapd v4, vs0
-; P9LE-NEXT: mtvsrd f0, r3
+; P9LE-NEXT: mtfprd f0, r3
; P9LE-NEXT: li r3, 6
; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: extsh r4, r3
; P9LE-NEXT: subf r3, r4, r3
; P9LE-NEXT: vmrglh v3, v4, v3
; P9LE-NEXT: xxswapd v4, vs0
-; P9LE-NEXT: mtvsrd f0, r3
+; P9LE-NEXT: mtfprd f0, r3
; P9LE-NEXT: xxswapd v2, vs0
; P9LE-NEXT: vmrglh v2, v2, v4
; P9LE-NEXT: vmrglw v2, v2, v3
; P8LE-NEXT: ori r4, r4, 33437
; P8LE-NEXT: ori r9, r9, 63249
; P8LE-NEXT: ori r11, r11, 37253
-; P8LE-NEXT: mfvsrd r5, f0
+; P8LE-NEXT: mffprd r5, f0
; P8LE-NEXT: rldicl r3, r5, 32, 48
; P8LE-NEXT: rldicl r6, r5, 16, 48
; P8LE-NEXT: clrldi r7, r5, 48
; P8LE-NEXT: mulli r8, r8, -124
; P8LE-NEXT: subf r3, r4, r3
; P8LE-NEXT: subf r4, r9, r6
-; P8LE-NEXT: mtvsrd f0, r3
+; P8LE-NEXT: mtfprd f0, r3
; P8LE-NEXT: subf r3, r10, r7
-; P8LE-NEXT: mtvsrd f1, r4
+; P8LE-NEXT: mtfprd f1, r4
; P8LE-NEXT: subf r4, r8, r5
-; P8LE-NEXT: mtvsrd f2, r3
+; P8LE-NEXT: mtfprd f2, r3
; P8LE-NEXT: xxswapd v2, vs0
-; P8LE-NEXT: mtvsrd f3, r4
+; P8LE-NEXT: mtfprd f3, r4
; P8LE-NEXT: xxswapd v3, vs1
; P8LE-NEXT: xxswapd v4, vs2
; P8LE-NEXT: xxswapd v5, vs3
; P9LE-NEXT: add r4, r4, r6
; P9LE-NEXT: mulli r4, r4, 95
; P9LE-NEXT: subf r3, r4, r3
-; P9LE-NEXT: mtvsrd f0, r3
+; P9LE-NEXT: mtfprd f0, r3
; P9LE-NEXT: li r3, 2
; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: extsh r4, r3
; P9LE-NEXT: mulli r4, r4, 95
; P9LE-NEXT: subf r3, r4, r3
; P9LE-NEXT: xxswapd v3, vs0
-; P9LE-NEXT: mtvsrd f0, r3
+; P9LE-NEXT: mtfprd f0, r3
; P9LE-NEXT: li r3, 4
; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: extsh r4, r3
; P9LE-NEXT: mulli r4, r4, 95
; P9LE-NEXT: subf r3, r4, r3
; P9LE-NEXT: xxswapd v4, vs0
-; P9LE-NEXT: mtvsrd f0, r3
+; P9LE-NEXT: mtfprd f0, r3
; P9LE-NEXT: li r3, 6
; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: extsh r4, r3
; P9LE-NEXT: subf r3, r4, r3
; P9LE-NEXT: vmrglh v3, v4, v3
; P9LE-NEXT: xxswapd v4, vs0
-; P9LE-NEXT: mtvsrd f0, r3
+; P9LE-NEXT: mtfprd f0, r3
; P9LE-NEXT: xxswapd v2, vs0
; P9LE-NEXT: vmrglh v2, v2, v4
; P9LE-NEXT: vmrglw v2, v2, v3
; P8LE-NEXT: lis r4, -21386
; P8LE-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; P8LE-NEXT: ori r4, r4, 37253
-; P8LE-NEXT: mfvsrd r5, f0
+; P8LE-NEXT: mffprd r5, f0
; P8LE-NEXT: clrldi r3, r5, 48
; P8LE-NEXT: rldicl r7, r5, 32, 48
; P8LE-NEXT: extsh r8, r3
; P8LE-NEXT: mulli r4, r4, 95
; P8LE-NEXT: subf r3, r8, r3
; P8LE-NEXT: subf r6, r9, r6
-; P8LE-NEXT: mtvsrd f0, r3
+; P8LE-NEXT: mtfprd f0, r3
; P8LE-NEXT: subf r3, r10, r7
; P8LE-NEXT: subf r4, r4, r5
-; P8LE-NEXT: mtvsrd f1, r6
-; P8LE-NEXT: mtvsrd f2, r3
+; P8LE-NEXT: mtfprd f1, r6
+; P8LE-NEXT: mtfprd f2, r3
; P8LE-NEXT: xxswapd v2, vs0
-; P8LE-NEXT: mtvsrd f3, r4
+; P8LE-NEXT: mtfprd f3, r4
; P8LE-NEXT: xxswapd v3, vs1
; P8LE-NEXT: xxswapd v4, vs2
; P8LE-NEXT: xxswapd v5, vs3
; P9LE-NEXT: add r4, r4, r6
; P9LE-NEXT: mulli r6, r4, 95
; P9LE-NEXT: subf r3, r6, r3
-; P9LE-NEXT: mtvsrd f0, r3
+; P9LE-NEXT: mtfprd f0, r3
; P9LE-NEXT: li r3, 2
; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: extsh r6, r3
; P9LE-NEXT: mulli r7, r6, 95
; P9LE-NEXT: subf r3, r7, r3
; P9LE-NEXT: xxswapd v3, vs0
-; P9LE-NEXT: mtvsrd f0, r3
+; P9LE-NEXT: mtfprd f0, r3
; P9LE-NEXT: li r3, 4
; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: extsh r7, r3
; P9LE-NEXT: mulli r8, r7, 95
; P9LE-NEXT: subf r3, r8, r3
; P9LE-NEXT: xxswapd v4, vs0
-; P9LE-NEXT: mtvsrd f0, r3
+; P9LE-NEXT: mtfprd f0, r3
; P9LE-NEXT: li r3, 6
; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: extsh r8, r3
; P9LE-NEXT: subf r3, r8, r3
; P9LE-NEXT: vmrglh v3, v4, v3
; P9LE-NEXT: xxswapd v4, vs0
-; P9LE-NEXT: mtvsrd f0, r3
+; P9LE-NEXT: mtfprd f0, r3
; P9LE-NEXT: xxswapd v2, vs0
-; P9LE-NEXT: mtvsrd f0, r4
+; P9LE-NEXT: mtfprd f0, r4
; P9LE-NEXT: vmrglh v2, v2, v4
; P9LE-NEXT: vmrglw v2, v2, v3
; P9LE-NEXT: xxswapd v3, vs0
-; P9LE-NEXT: mtvsrd f0, r6
+; P9LE-NEXT: mtfprd f0, r6
; P9LE-NEXT: xxswapd v4, vs0
-; P9LE-NEXT: mtvsrd f0, r7
+; P9LE-NEXT: mtfprd f0, r7
; P9LE-NEXT: vmrglh v3, v4, v3
; P9LE-NEXT: xxswapd v4, vs0
-; P9LE-NEXT: mtvsrd f0, r5
+; P9LE-NEXT: mtfprd f0, r5
; P9LE-NEXT: xxswapd v5, vs0
; P9LE-NEXT: vmrglh v4, v5, v4
; P9LE-NEXT: vmrglw v3, v4, v3
; P8LE-NEXT: lis r5, -21386
; P8LE-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; P8LE-NEXT: ori r5, r5, 37253
-; P8LE-NEXT: mfvsrd r6, f0
+; P8LE-NEXT: mffprd r6, f0
; P8LE-NEXT: clrldi r3, r6, 48
; P8LE-NEXT: rldicl r4, r6, 48, 48
; P8LE-NEXT: rldicl r7, r6, 32, 48
; P8LE-NEXT: add r9, r0, r9
; P8LE-NEXT: mulli r0, r8, 95
; P8LE-NEXT: add r10, r12, r10
-; P8LE-NEXT: mtvsrd f0, r8
+; P8LE-NEXT: mtfprd f0, r8
; P8LE-NEXT: srwi r8, r5, 31
; P8LE-NEXT: srawi r5, r5, 6
; P8LE-NEXT: mulli r11, r9, 95
-; P8LE-NEXT: mtvsrd f1, r9
+; P8LE-NEXT: mtfprd f1, r9
; P8LE-NEXT: mulli r9, r10, 95
; P8LE-NEXT: add r5, r5, r8
; P8LE-NEXT: xxswapd v2, vs0
-; P8LE-NEXT: mtvsrd f2, r10
-; P8LE-NEXT: mtvsrd f3, r5
+; P8LE-NEXT: mtfprd f2, r10
+; P8LE-NEXT: mtfprd f3, r5
; P8LE-NEXT: mulli r5, r5, 95
; P8LE-NEXT: xxswapd v3, vs1
; P8LE-NEXT: subf r3, r0, r3
; P8LE-NEXT: xxswapd v1, vs2
-; P8LE-NEXT: mtvsrd f0, r3
+; P8LE-NEXT: mtfprd f0, r3
; P8LE-NEXT: subf r4, r11, r4
; P8LE-NEXT: xxswapd v6, vs3
; P8LE-NEXT: subf r3, r9, r7
-; P8LE-NEXT: mtvsrd f1, r4
-; P8LE-NEXT: mtvsrd f4, r3
+; P8LE-NEXT: mtfprd f1, r4
+; P8LE-NEXT: mtfprd f4, r3
; P8LE-NEXT: subf r3, r5, r6
-; P8LE-NEXT: mtvsrd f5, r3
+; P8LE-NEXT: mtfprd f5, r3
; P8LE-NEXT: xxswapd v4, vs1
; P8LE-NEXT: vmrglh v2, v3, v2
; P8LE-NEXT: xxswapd v3, vs0
; P9LE-NEXT: addze r4, r4
; P9LE-NEXT: slwi r4, r4, 6
; P9LE-NEXT: subf r3, r4, r3
-; P9LE-NEXT: mtvsrd f0, r3
+; P9LE-NEXT: mtfprd f0, r3
; P9LE-NEXT: li r3, 2
; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: extsh r4, r3
; P9LE-NEXT: slwi r4, r4, 5
; P9LE-NEXT: subf r3, r4, r3
; P9LE-NEXT: xxswapd v3, vs0
-; P9LE-NEXT: mtvsrd f0, r3
+; P9LE-NEXT: mtfprd f0, r3
; P9LE-NEXT: li r3, 6
; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: extsh r4, r3
; P9LE-NEXT: add r4, r4, r5
; P9LE-NEXT: mulli r4, r4, 95
; P9LE-NEXT: subf r3, r4, r3
-; P9LE-NEXT: mtvsrd f0, r3
+; P9LE-NEXT: mtfprd f0, r3
; P9LE-NEXT: li r3, 4
; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: extsh r4, r3
; P9LE-NEXT: slwi r4, r4, 3
; P9LE-NEXT: subf r3, r4, r3
; P9LE-NEXT: xxswapd v4, vs0
-; P9LE-NEXT: mtvsrd f0, r3
+; P9LE-NEXT: mtfprd f0, r3
; P9LE-NEXT: xxswapd v2, vs0
; P9LE-NEXT: vmrglh v2, v4, v2
; P9LE-NEXT: vmrglw v2, v2, v3
; P8LE-NEXT: xxswapd vs0, v2
; P8LE-NEXT: lis r3, -21386
; P8LE-NEXT: ori r3, r3, 37253
-; P8LE-NEXT: mfvsrd r4, f0
+; P8LE-NEXT: mffprd r4, f0
; P8LE-NEXT: rldicl r5, r4, 16, 48
; P8LE-NEXT: clrldi r7, r4, 48
; P8LE-NEXT: extsh r6, r5
; P8LE-NEXT: slwi r8, r8, 6
; P8LE-NEXT: subf r7, r8, r7
; P8LE-NEXT: rldicl r3, r3, 32, 32
-; P8LE-NEXT: mtvsrd f0, r7
+; P8LE-NEXT: mtfprd f0, r7
; P8LE-NEXT: add r3, r3, r6
; P8LE-NEXT: addze r6, r10
; P8LE-NEXT: srwi r10, r3, 31
; P8LE-NEXT: subf r6, r6, r9
; P8LE-NEXT: mulli r3, r3, 95
; P8LE-NEXT: srawi r8, r10, 3
-; P8LE-NEXT: mtvsrd f1, r6
+; P8LE-NEXT: mtfprd f1, r6
; P8LE-NEXT: addze r7, r8
; P8LE-NEXT: xxswapd v3, vs1
; P8LE-NEXT: subf r3, r3, r5
; P8LE-NEXT: slwi r5, r7, 3
; P8LE-NEXT: subf r4, r5, r4
-; P8LE-NEXT: mtvsrd f2, r3
-; P8LE-NEXT: mtvsrd f3, r4
+; P8LE-NEXT: mtfprd f2, r3
+; P8LE-NEXT: mtfprd f3, r4
; P8LE-NEXT: xxswapd v4, vs2
; P8LE-NEXT: vmrglh v2, v3, v2
; P8LE-NEXT: xxswapd v5, vs3
; P9LE-NEXT: lis r5, -19946
; P9LE-NEXT: mulli r4, r4, 654
; P9LE-NEXT: subf r3, r4, r3
-; P9LE-NEXT: mtvsrd f0, r3
+; P9LE-NEXT: mtfprd f0, r3
; P9LE-NEXT: li r3, 4
; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: extsh r4, r3
; P9LE-NEXT: mulli r4, r4, 23
; P9LE-NEXT: subf r3, r4, r3
; P9LE-NEXT: xxswapd v3, vs0
-; P9LE-NEXT: mtvsrd f0, r3
+; P9LE-NEXT: mtfprd f0, r3
; P9LE-NEXT: li r3, 6
; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: extsh r4, r3
; P9LE-NEXT: subf r3, r4, r3
; P9LE-NEXT: vmrglh v3, v3, v4
; P9LE-NEXT: xxswapd v4, vs0
-; P9LE-NEXT: mtvsrd f0, r3
+; P9LE-NEXT: mtfprd f0, r3
; P9LE-NEXT: xxswapd v2, vs0
; P9LE-NEXT: vmrglh v2, v2, v4
; P9LE-NEXT: vmrglw v2, v2, v3
; P8LE-NEXT: xxlxor v5, v5, v5
; P8LE-NEXT: ori r3, r3, 47143
; P8LE-NEXT: ori r8, r8, 17097
-; P8LE-NEXT: mfvsrd r4, f0
+; P8LE-NEXT: mffprd r4, f0
; P8LE-NEXT: rldicl r5, r4, 16, 48
; P8LE-NEXT: rldicl r6, r4, 32, 48
; P8LE-NEXT: rldicl r4, r4, 48, 48
; P8LE-NEXT: mulli r8, r8, 23
; P8LE-NEXT: mulli r7, r7, 654
; P8LE-NEXT: subf r3, r3, r5
-; P8LE-NEXT: mtvsrd f0, r3
+; P8LE-NEXT: mtfprd f0, r3
; P8LE-NEXT: subf r3, r8, r6
; P8LE-NEXT: subf r4, r7, r4
-; P8LE-NEXT: mtvsrd f1, r3
-; P8LE-NEXT: mtvsrd f2, r4
+; P8LE-NEXT: mtfprd f1, r3
+; P8LE-NEXT: mtfprd f2, r4
; P8LE-NEXT: xxswapd v2, vs0
; P8LE-NEXT: xxswapd v3, vs1
; P8LE-NEXT: xxswapd v4, vs2
; P9LE-NEXT: lis r5, 24749
; P9LE-NEXT: mulli r4, r4, 23
; P9LE-NEXT: subf r3, r4, r3
-; P9LE-NEXT: mtvsrd f0, r3
+; P9LE-NEXT: mtfprd f0, r3
; P9LE-NEXT: li r3, 6
; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: extsh r4, r3
; P9LE-NEXT: mulli r4, r4, 5423
; P9LE-NEXT: subf r3, r4, r3
; P9LE-NEXT: xxswapd v3, vs0
-; P9LE-NEXT: mtvsrd f0, r3
+; P9LE-NEXT: mtfprd f0, r3
; P9LE-NEXT: li r3, 2
; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: extsh r4, r3
; P9LE-NEXT: slwi r4, r4, 15
; P9LE-NEXT: subf r3, r4, r3
; P9LE-NEXT: xxswapd v4, vs0
-; P9LE-NEXT: mtvsrd f0, r3
+; P9LE-NEXT: mtfprd f0, r3
; P9LE-NEXT: xxswapd v2, vs0
; P9LE-NEXT: vmrglh v3, v4, v3
; P9LE-NEXT: xxlxor v4, v4, v4
; P8LE-NEXT: xxlxor v5, v5, v5
; P8LE-NEXT: ori r6, r6, 47143
; P8LE-NEXT: ori r7, r7, 17097
-; P8LE-NEXT: mfvsrd r3, f0
+; P8LE-NEXT: mffprd r3, f0
; P8LE-NEXT: rldicl r4, r3, 16, 48
; P8LE-NEXT: rldicl r5, r3, 32, 48
; P8LE-NEXT: extsh r8, r4
; P8LE-NEXT: srawi r8, r8, 15
; P8LE-NEXT: subf r4, r6, r4
; P8LE-NEXT: addze r6, r8
-; P8LE-NEXT: mtvsrd f0, r4
+; P8LE-NEXT: mtfprd f0, r4
; P8LE-NEXT: slwi r4, r6, 15
; P8LE-NEXT: subf r5, r7, r5
; P8LE-NEXT: subf r3, r4, r3
-; P8LE-NEXT: mtvsrd f1, r5
+; P8LE-NEXT: mtfprd f1, r5
; P8LE-NEXT: xxswapd v2, vs0
-; P8LE-NEXT: mtvsrd f2, r3
+; P8LE-NEXT: mtfprd f2, r3
; P8LE-NEXT: xxswapd v3, vs1
; P8LE-NEXT: xxswapd v4, vs2
; P8LE-NEXT: vmrglh v2, v2, v3
; P8LE-NEXT: sldi r5, r5, 32
; P8LE-NEXT: oris r3, r3, 58853
; P8LE-NEXT: oris r4, r4, 22795
-; P8LE-NEXT: mfvsrd r8, f0
+; P8LE-NEXT: mffprd r8, f0
; P8LE-NEXT: oris r5, r5, 1603
; P8LE-NEXT: ori r3, r3, 6055
; P8LE-NEXT: ori r4, r4, 8549
; P8LE-NEXT: add r4, r4, r9
; P8LE-NEXT: mulli r4, r4, 23
; P8LE-NEXT: sub r3, r6, r3
-; P8LE-NEXT: mtvsrd f0, r3
+; P8LE-NEXT: mtfprd f0, r3
; P8LE-NEXT: sub r5, r7, r5
-; P8LE-NEXT: mtvsrd f1, r5
+; P8LE-NEXT: mtfprd f1, r5
; P8LE-NEXT: sub r3, r8, r4
; P8LE-NEXT: li r4, 0
-; P8LE-NEXT: mtvsrd f2, r3
-; P8LE-NEXT: mtvsrd f3, r4
+; P8LE-NEXT: mtfprd f2, r3
+; P8LE-NEXT: mtfprd f3, r4
; P8LE-NEXT: xxmrghd v3, vs0, vs2
; P8LE-NEXT: xxmrghd v2, vs1, vs3
; P8LE-NEXT: blr
; P8BE-NEXT: oris r4, r4, 22795
; P8BE-NEXT: sldi r5, r5, 32
; P8BE-NEXT: oris r3, r3, 58853
-; P8BE-NEXT: mfvsrd r7, f0
+; P8BE-NEXT: mffprd r7, f0
; P8BE-NEXT: ori r4, r4, 8549
; P8BE-NEXT: ori r3, r3, 6055
; P8BE-NEXT: oris r5, r5, 1603
-; P8BE-NEXT: mfvsrd r8, f1
+; P8BE-NEXT: mffprd r8, f1
; P8BE-NEXT: mulhd r4, r6, r4
; P8BE-NEXT: mulhd r3, r7, r3
; P8BE-NEXT: ori r5, r5, 21445
; P8BE-NEXT: mulli r5, r5, 654
; P8BE-NEXT: sub r3, r7, r3
; P8BE-NEXT: sub r4, r6, r4
-; P8BE-NEXT: mtvsrd f0, r3
+; P8BE-NEXT: mtfprd f0, r3
; P8BE-NEXT: sub r3, r8, r5
-; P8BE-NEXT: mtvsrd f1, r4
+; P8BE-NEXT: mtfprd f1, r4
; P8BE-NEXT: li r4, 0
-; P8BE-NEXT: mtvsrd f2, r3
-; P8BE-NEXT: mtvsrd f3, r4
+; P8BE-NEXT: mtfprd f2, r3
+; P8BE-NEXT: mtfprd f3, r4
; P8BE-NEXT: xxmrghd v3, vs1, vs0
; P8BE-NEXT: xxmrghd v2, vs3, vs2
; P8BE-NEXT: blr
; CHECK-DAG: std 30, -16(1)
; CHECK-DAG: mr 30, 1
; CHECK-DAG: std 0, 16(1)
-; CHECK-DAG: subfc 0, [[REG3]], [[REG2]]
+; CHECK-DAG: subc 0, [[REG2]], [[REG3]]
; CHECK: stdux 1, 1, 0
; CHECK: .cfi_def_cfa_register r30
; CHECK-NEXT: and 3, 3, 4
; CHECK-NEXT: or 3, 3, 5
; CHECK-NEXT: rldicl 4, 3, 32, 32
-; CHECK-NEXT: rlwinm 5, 3, 24, 0, 31
-; CHECK-NEXT: rlwinm 6, 4, 24, 0, 31
+; CHECK-NEXT: rotlwi 5, 3, 24
+; CHECK-NEXT: rotlwi 6, 4, 24
; CHECK-NEXT: rlwimi 5, 3, 8, 8, 15
; CHECK-NEXT: rlwimi 5, 3, 8, 24, 31
; CHECK-NEXT: rlwimi 6, 4, 8, 8, 15
define signext i32 @testCompare2(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: testCompare2:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: rlwinm r3, r3, 0, 31, 31
-; CHECK-NEXT: rlwinm r4, r4, 0, 31, 31
+; CHECK-NEXT: clrlwi r3, r3, 31
+; CHECK-NEXT: clrlwi r4, r4, 31
; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: clrldi r4, r4, 32
; CHECK-NEXT: sub r3, r4, r3
define signext i32 @test(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: test:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: rlwinm r3, r3, 0, 31, 31
-; CHECK-NEXT: rlwinm r4, r4, 0, 31, 31
+; CHECK-NEXT: clrlwi r3, r3, 31
+; CHECK-NEXT: clrlwi r4, r4, 31
; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: clrldi r4, r4, 32
; CHECK-NEXT: sub r3, r4, r3
define signext i32 @testCompare2(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: testCompare2:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: rlwinm r3, r3, 0, 31, 31
-; CHECK-NEXT: rlwinm r4, r4, 0, 31, 31
+; CHECK-NEXT: clrlwi r3, r3, 31
+; CHECK-NEXT: clrlwi r4, r4, 31
; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: clrldi r4, r4, 32
; CHECK-NEXT: sub r3, r3, r4
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: sradi r5, r3, 63
; CHECK-BE-NEXT: rldicl r6, r4, 1, 63
-; CHECK-BE-NEXT: subfc r3, r4, r3
+; CHECK-BE-NEXT: subc r3, r3, r4
; CHECK-BE-NEXT: adde r3, r5, r6
; CHECK-BE-NEXT: blr
;
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sradi r5, r3, 63
; CHECK-LE-NEXT: rldicl r6, r4, 1, 63
-; CHECK-LE-NEXT: subfc r3, r4, r3
+; CHECK-LE-NEXT: subc r3, r3, r4
; CHECK-LE-NEXT: adde r3, r5, r6
; CHECK-LE-NEXT: blr
entry:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: sradi r5, r3, 63
; CHECK-BE-NEXT: rldicl r6, r4, 1, 63
-; CHECK-BE-NEXT: subfc r3, r4, r3
+; CHECK-BE-NEXT: subc r3, r3, r4
; CHECK-BE-NEXT: adde r3, r5, r6
; CHECK-BE-NEXT: neg r3, r3
; CHECK-BE-NEXT: blr
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sradi r5, r3, 63
; CHECK-LE-NEXT: rldicl r6, r4, 1, 63
-; CHECK-LE-NEXT: subfc r3, r4, r3
+; CHECK-LE-NEXT: subc r3, r3, r4
; CHECK-LE-NEXT: adde r3, r5, r6
; CHECK-LE-NEXT: neg r3, r3
; CHECK-LE-NEXT: blr
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: sradi r6, r3, 63
; CHECK-BE-NEXT: ld r5, .LC0@toc@l(r5)
-; CHECK-BE-NEXT: subfc r3, r4, r3
+; CHECK-BE-NEXT: subc r3, r3, r4
; CHECK-BE-NEXT: rldicl r3, r4, 1, 63
; CHECK-BE-NEXT: adde r3, r6, r3
; CHECK-BE-NEXT: std r3, 0(r5)
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sradi r6, r3, 63
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
-; CHECK-LE-NEXT: subfc r3, r4, r3
+; CHECK-LE-NEXT: subc r3, r3, r4
; CHECK-LE-NEXT: rldicl r3, r4, 1, 63
; CHECK-LE-NEXT: adde r3, r6, r3
; CHECK-LE-NEXT: std r3, glob@toc@l(r5)
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: sradi r6, r3, 63
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
-; CHECK-BE-NEXT: subfc r3, r4, r3
+; CHECK-BE-NEXT: subc r3, r3, r4
; CHECK-BE-NEXT: rldicl r3, r4, 1, 63
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: adde r3, r6, r3
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sradi r6, r3, 63
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
-; CHECK-LE-NEXT: subfc r3, r4, r3
+; CHECK-LE-NEXT: subc r3, r3, r4
; CHECK-LE-NEXT: rldicl r3, r4, 1, 63
; CHECK-LE-NEXT: adde r3, r6, r3
; CHECK-LE-NEXT: neg r3, r3
define signext i32 @test_igeull(i64 %a, i64 %b) {
; CHECK-LABEL: test_igeull:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: subfc r3, r4, r3
+; CHECK-NEXT: subc r3, r3, r4
; CHECK-NEXT: subfe r3, r4, r4
; CHECK-NEXT: addi r3, r3, 1
; CHECK-NEXT: blr
define signext i32 @test_igeull_sext(i64 %a, i64 %b) {
; CHECK-LABEL: test_igeull_sext:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: subfc r3, r4, r3
+; CHECK-NEXT: subc r3, r3, r4
; CHECK-NEXT: subfe r3, r4, r4
; CHECK-NEXT: not r3, r3
; CHECK-NEXT: blr
; BE-LABEL: test_igeull_store:
; BE: # %bb.0: # %entry
; BE-NEXT: addis r5, r2, .LC0@toc@ha
-; BE-NEXT: subfc r3, r4, r3
+; BE-NEXT: subc r3, r3, r4
; BE-NEXT: ld r3, .LC0@toc@l(r5)
; BE-NEXT: subfe r4, r4, r4
; BE-NEXT: addi r4, r4, 1
;
; LE-LABEL: test_igeull_store:
; LE: # %bb.0: # %entry
-; LE-NEXT: subfc r3, r4, r3
+; LE-NEXT: subc r3, r3, r4
; LE-NEXT: addis r5, r2, glob@toc@ha
; LE-NEXT: subfe r3, r4, r4
; LE-NEXT: addi r3, r3, 1
; BE-LABEL: test_igeull_sext_store:
; BE: # %bb.0: # %entry
; BE-NEXT: addis r5, r2, .LC0@toc@ha
-; BE-NEXT: subfc r3, r4, r3
+; BE-NEXT: subc r3, r3, r4
; BE-NEXT: ld r3, .LC0@toc@l(r5)
; BE-NEXT: subfe r4, r4, r4
; BE-NEXT: not r4, r4
;
; LE-LABEL: test_igeull_sext_store:
; LE: # %bb.0: # %entry
-; LE-NEXT: subfc r3, r4, r3
+; LE-NEXT: subc r3, r3, r4
; LE-NEXT: addis r5, r2, glob@toc@ha
; LE-NEXT: subfe r3, r4, r4
; LE-NEXT: not r3, r3
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sradi r5, r4, 63
; CHECK-NEXT: rldicl r6, r3, 1, 63
-; CHECK-NEXT: subfc r3, r3, r4
+; CHECK-NEXT: subc r3, r4, r3
; CHECK-NEXT: adde r3, r6, r5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sradi r5, r4, 63
; CHECK-NEXT: rldicl r6, r3, 1, 63
-; CHECK-NEXT: subfc r3, r3, r4
+; CHECK-NEXT: subc r3, r4, r3
; CHECK-NEXT: adde r3, r6, r5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sradi r6, r4, 63
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
-; CHECK-NEXT: subfc r4, r3, r4
+; CHECK-NEXT: subc r4, r4, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: adde r3, r3, r6
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sradi r6, r4, 63
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
-; CHECK-NEXT: subfc r4, r3, r4
+; CHECK-NEXT: subc r4, r4, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: adde r3, r3, r6
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: sradi r5, r4, 63
; CHECK-BE-NEXT: rldicl r6, r3, 1, 63
-; CHECK-BE-NEXT: subfc r3, r3, r4
+; CHECK-BE-NEXT: subc r3, r4, r3
; CHECK-BE-NEXT: adde r3, r5, r6
; CHECK-BE-NEXT: blr
;
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sradi r5, r4, 63
; CHECK-LE-NEXT: rldicl r6, r3, 1, 63
-; CHECK-LE-NEXT: subfc r3, r3, r4
+; CHECK-LE-NEXT: subc r3, r4, r3
; CHECK-LE-NEXT: adde r3, r5, r6
; CHECK-LE-NEXT: blr
entry:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: sradi r5, r4, 63
; CHECK-BE-NEXT: rldicl r6, r3, 1, 63
-; CHECK-BE-NEXT: subfc r3, r3, r4
+; CHECK-BE-NEXT: subc r3, r4, r3
; CHECK-BE-NEXT: adde r3, r5, r6
; CHECK-BE-NEXT: neg r3, r3
; CHECK-BE-NEXT: blr
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sradi r5, r4, 63
; CHECK-LE-NEXT: rldicl r6, r3, 1, 63
-; CHECK-LE-NEXT: subfc r3, r3, r4
+; CHECK-LE-NEXT: subc r3, r4, r3
; CHECK-LE-NEXT: adde r3, r5, r6
; CHECK-LE-NEXT: neg r3, r3
; CHECK-LE-NEXT: blr
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: sradi r6, r4, 63
; CHECK-BE-NEXT: ld r5, .LC0@toc@l(r5)
-; CHECK-BE-NEXT: subfc r4, r3, r4
+; CHECK-BE-NEXT: subc r4, r4, r3
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
; CHECK-BE-NEXT: adde r3, r6, r3
; CHECK-BE-NEXT: std r3, 0(r5)
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sradi r6, r4, 63
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
-; CHECK-LE-NEXT: subfc r4, r3, r4
+; CHECK-LE-NEXT: subc r4, r4, r3
; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
; CHECK-LE-NEXT: adde r3, r6, r3
; CHECK-LE-NEXT: std r3, glob@toc@l(r5)
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: sradi r6, r4, 63
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
-; CHECK-BE-NEXT: subfc r4, r3, r4
+; CHECK-BE-NEXT: subc r4, r4, r3
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: adde r3, r6, r3
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sradi r6, r4, 63
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
-; CHECK-LE-NEXT: subfc r4, r3, r4
+; CHECK-LE-NEXT: subc r4, r4, r3
; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
; CHECK-LE-NEXT: adde r3, r6, r3
; CHECK-LE-NEXT: neg r3, r3
define signext i32 @test_ileull(i64 %a, i64 %b) {
; CHECK-LABEL: test_ileull:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: subfc r4, r3, r4
+; CHECK-NEXT: subc r4, r4, r3
; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: addi r3, r3, 1
; CHECK-NEXT: blr
define signext i32 @test_ileull_sext(i64 %a, i64 %b) {
; CHECK-LABEL: test_ileull_sext:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: subfc r4, r3, r4
+; CHECK-NEXT: subc r4, r4, r3
; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: not r3, r3
; CHECK-NEXT: blr
; BE-LABEL: test_ileull_store:
; BE: # %bb.0: # %entry
; BE-NEXT: addis r5, r2, .LC0@toc@ha
-; BE-NEXT: subfc r4, r3, r4
+; BE-NEXT: subc r4, r4, r3
; BE-NEXT: ld r4, .LC0@toc@l(r5)
; BE-NEXT: subfe r3, r3, r3
; BE-NEXT: addi r3, r3, 1
;
; LE-LABEL: test_ileull_store:
; LE: # %bb.0: # %entry
-; LE-NEXT: subfc r4, r3, r4
+; LE-NEXT: subc r4, r4, r3
; LE-NEXT: addis r5, r2, glob@toc@ha
; LE-NEXT: subfe r3, r3, r3
; LE-NEXT: addi r3, r3, 1
; BE-LABEL: test_ileull_sext_store:
; BE: # %bb.0: # %entry
; BE-NEXT: addis r5, r2, .LC0@toc@ha
-; BE-NEXT: subfc r4, r3, r4
+; BE-NEXT: subc r4, r4, r3
; BE-NEXT: ld r4, .LC0@toc@l(r5)
; BE-NEXT: subfe r3, r3, r3
; BE-NEXT: not r3, r3
;
; LE-LABEL: test_ileull_sext_store:
; LE: # %bb.0: # %entry
-; LE-NEXT: subfc r4, r3, r4
+; LE-NEXT: subc r4, r4, r3
; LE-NEXT: addis r5, r2, glob@toc@ha
; LE-NEXT: subfe r3, r3, r3
; LE-NEXT: not r3, r3
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sradi r5, r3, 63
; CHECK-NEXT: rldicl r6, r4, 1, 63
-; CHECK-NEXT: subfc r3, r4, r3
+; CHECK-NEXT: subc r3, r3, r4
; CHECK-NEXT: adde r3, r6, r5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sradi r5, r3, 63
; CHECK-NEXT: rldicl r6, r4, 1, 63
-; CHECK-NEXT: subfc r3, r4, r3
+; CHECK-NEXT: subc r3, r3, r4
; CHECK-NEXT: adde r3, r6, r5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3
; BE: # %bb.0: # %entry
; BE-NEXT: sradi r6, r3, 63
; BE-NEXT: addis r5, r2, .LC0@toc@ha
-; BE-NEXT: subfc r3, r4, r3
+; BE-NEXT: subc r3, r3, r4
; BE-NEXT: rldicl r3, r4, 1, 63
; BE-NEXT: ld r4, .LC0@toc@l(r5)
; BE-NEXT: adde r3, r3, r6
; LE: # %bb.0: # %entry
; LE-NEXT: sradi r6, r3, 63
; LE-NEXT: addis r5, r2, glob@toc@ha
-; LE-NEXT: subfc r3, r4, r3
+; LE-NEXT: subc r3, r3, r4
; LE-NEXT: rldicl r3, r4, 1, 63
; LE-NEXT: adde r3, r3, r6
; LE-NEXT: xori r3, r3, 1
; BE: # %bb.0: # %entry
; BE-NEXT: sradi r6, r3, 63
; BE-NEXT: addis r5, r2, .LC0@toc@ha
-; BE-NEXT: subfc r3, r4, r3
+; BE-NEXT: subc r3, r3, r4
; BE-NEXT: rldicl r3, r4, 1, 63
; BE-NEXT: ld r4, .LC0@toc@l(r5)
; BE-NEXT: adde r3, r3, r6
; LE: # %bb.0: # %entry
; LE-NEXT: sradi r6, r3, 63
; LE-NEXT: addis r5, r2, glob@toc@ha
-; LE-NEXT: subfc r3, r4, r3
+; LE-NEXT: subc r3, r3, r4
; LE-NEXT: rldicl r3, r4, 1, 63
; LE-NEXT: adde r3, r3, r6
; LE-NEXT: xori r3, r3, 1
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: sradi r5, r3, 63
; CHECK-BE-NEXT: rldicl r6, r4, 1, 63
-; CHECK-BE-NEXT: subfc r3, r4, r3
+; CHECK-BE-NEXT: subc r3, r3, r4
; CHECK-BE-NEXT: adde r3, r5, r6
; CHECK-BE-NEXT: blr
;
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sradi r5, r3, 63
; CHECK-LE-NEXT: rldicl r6, r4, 1, 63
-; CHECK-LE-NEXT: subfc r3, r4, r3
+; CHECK-LE-NEXT: subc r3, r3, r4
; CHECK-LE-NEXT: adde r3, r5, r6
; CHECK-LE-NEXT: blr
entry:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: sradi r5, r3, 63
; CHECK-BE-NEXT: rldicl r6, r4, 1, 63
-; CHECK-BE-NEXT: subfc r3, r4, r3
+; CHECK-BE-NEXT: subc r3, r3, r4
; CHECK-BE-NEXT: adde r3, r5, r6
; CHECK-BE-NEXT: neg r3, r3
; CHECK-BE-NEXT: blr
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sradi r5, r3, 63
; CHECK-LE-NEXT: rldicl r6, r4, 1, 63
-; CHECK-LE-NEXT: subfc r3, r4, r3
+; CHECK-LE-NEXT: subc r3, r3, r4
; CHECK-LE-NEXT: adde r3, r5, r6
; CHECK-LE-NEXT: neg r3, r3
; CHECK-LE-NEXT: blr
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: sradi r6, r3, 63
; CHECK-BE-NEXT: ld r5, .LC0@toc@l(r5)
-; CHECK-BE-NEXT: subfc r3, r4, r3
+; CHECK-BE-NEXT: subc r3, r3, r4
; CHECK-BE-NEXT: rldicl r3, r4, 1, 63
; CHECK-BE-NEXT: adde r3, r6, r3
; CHECK-BE-NEXT: std r3, 0(r5)
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sradi r6, r3, 63
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
-; CHECK-LE-NEXT: subfc r3, r4, r3
+; CHECK-LE-NEXT: subc r3, r3, r4
; CHECK-LE-NEXT: rldicl r3, r4, 1, 63
; CHECK-LE-NEXT: adde r3, r6, r3
; CHECK-LE-NEXT: std r3, glob@toc@l(r5)
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: sradi r6, r3, 63
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
-; CHECK-BE-NEXT: subfc r3, r4, r3
+; CHECK-BE-NEXT: subc r3, r3, r4
; CHECK-BE-NEXT: rldicl r3, r4, 1, 63
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: adde r3, r6, r3
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sradi r6, r3, 63
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
-; CHECK-LE-NEXT: subfc r3, r4, r3
+; CHECK-LE-NEXT: subc r3, r3, r4
; CHECK-LE-NEXT: rldicl r3, r4, 1, 63
; CHECK-LE-NEXT: adde r3, r6, r3
; CHECK-LE-NEXT: neg r3, r3
define i64 @test_llgeull(i64 %a, i64 %b) {
; CHECK-LABEL: test_llgeull:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: subfc r3, r4, r3
+; CHECK-NEXT: subc r3, r3, r4
; CHECK-NEXT: subfe r3, r4, r4
; CHECK-NEXT: addi r3, r3, 1
; CHECK-NEXT: blr
define i64 @test_llgeull_sext(i64 %a, i64 %b) {
; CHECK-LABEL: test_llgeull_sext:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: subfc r3, r4, r3
+; CHECK-NEXT: subc r3, r3, r4
; CHECK-NEXT: subfe r3, r4, r4
; CHECK-NEXT: not r3, r3
; CHECK-NEXT: blr
; BE-LABEL: test_llgeull_store:
; BE: # %bb.0: # %entry
; BE-NEXT: addis r5, r2, .LC0@toc@ha
-; BE-NEXT: subfc r3, r4, r3
+; BE-NEXT: subc r3, r3, r4
; BE-NEXT: ld r3, .LC0@toc@l(r5)
; BE-NEXT: subfe r4, r4, r4
; BE-NEXT: addi r4, r4, 1
;
; LE-LABEL: test_llgeull_store:
; LE: # %bb.0: # %entry
-; LE-NEXT: subfc r3, r4, r3
+; LE-NEXT: subc r3, r3, r4
; LE-NEXT: addis r5, r2, glob@toc@ha
; LE-NEXT: subfe r3, r4, r4
; LE-NEXT: addi r3, r3, 1
; BE-LABEL: test_llgeull_sext_store:
; BE: # %bb.0: # %entry
; BE-NEXT: addis r5, r2, .LC0@toc@ha
-; BE-NEXT: subfc r3, r4, r3
+; BE-NEXT: subc r3, r3, r4
; BE-NEXT: ld r3, .LC0@toc@l(r5)
; BE-NEXT: subfe r4, r4, r4
; BE-NEXT: not r4, r4
;
; LE-LABEL: test_llgeull_sext_store:
; LE: # %bb.0: # %entry
-; LE-NEXT: subfc r3, r4, r3
+; LE-NEXT: subc r3, r3, r4
; LE-NEXT: addis r5, r2, glob@toc@ha
; LE-NEXT: subfe r3, r4, r4
; LE-NEXT: not r3, r3
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sradi r5, r4, 63
; CHECK-NEXT: rldicl r6, r3, 1, 63
-; CHECK-NEXT: subfc r3, r3, r4
+; CHECK-NEXT: subc r3, r4, r3
; CHECK-NEXT: adde r3, r6, r5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sradi r5, r4, 63
; CHECK-NEXT: rldicl r6, r3, 1, 63
-; CHECK-NEXT: subfc r3, r3, r4
+; CHECK-NEXT: subc r3, r4, r3
; CHECK-NEXT: adde r3, r6, r5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sradi r6, r4, 63
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
-; CHECK-NEXT: subfc r4, r3, r4
+; CHECK-NEXT: subc r4, r4, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: adde r3, r3, r6
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sradi r6, r4, 63
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
-; CHECK-NEXT: subfc r4, r3, r4
+; CHECK-NEXT: subc r4, r4, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: adde r3, r3, r6
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: sradi r5, r4, 63
; CHECK-BE-NEXT: rldicl r6, r3, 1, 63
-; CHECK-BE-NEXT: subfc r3, r3, r4
+; CHECK-BE-NEXT: subc r3, r4, r3
; CHECK-BE-NEXT: adde r3, r5, r6
; CHECK-BE-NEXT: blr
;
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sradi r5, r4, 63
; CHECK-LE-NEXT: rldicl r6, r3, 1, 63
-; CHECK-LE-NEXT: subfc r3, r3, r4
+; CHECK-LE-NEXT: subc r3, r4, r3
; CHECK-LE-NEXT: adde r3, r5, r6
; CHECK-LE-NEXT: blr
entry:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: sradi r5, r4, 63
; CHECK-BE-NEXT: rldicl r6, r3, 1, 63
-; CHECK-BE-NEXT: subfc r3, r3, r4
+; CHECK-BE-NEXT: subc r3, r4, r3
; CHECK-BE-NEXT: adde r3, r5, r6
; CHECK-BE-NEXT: neg r3, r3
; CHECK-BE-NEXT: blr
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sradi r5, r4, 63
; CHECK-LE-NEXT: rldicl r6, r3, 1, 63
-; CHECK-LE-NEXT: subfc r3, r3, r4
+; CHECK-LE-NEXT: subc r3, r4, r3
; CHECK-LE-NEXT: adde r3, r5, r6
; CHECK-LE-NEXT: neg r3, r3
; CHECK-LE-NEXT: blr
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: sradi r6, r4, 63
; CHECK-BE-NEXT: ld r5, .LC0@toc@l(r5)
-; CHECK-BE-NEXT: subfc r4, r3, r4
+; CHECK-BE-NEXT: subc r4, r4, r3
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
; CHECK-BE-NEXT: adde r3, r6, r3
; CHECK-BE-NEXT: std r3, 0(r5)
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sradi r6, r4, 63
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
-; CHECK-LE-NEXT: subfc r4, r3, r4
+; CHECK-LE-NEXT: subc r4, r4, r3
; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
; CHECK-LE-NEXT: adde r3, r6, r3
; CHECK-LE-NEXT: std r3, glob@toc@l(r5)
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: sradi r6, r4, 63
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
-; CHECK-BE-NEXT: subfc r4, r3, r4
+; CHECK-BE-NEXT: subc r4, r4, r3
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: adde r3, r6, r3
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sradi r6, r4, 63
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
-; CHECK-LE-NEXT: subfc r4, r3, r4
+; CHECK-LE-NEXT: subc r4, r4, r3
; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
; CHECK-LE-NEXT: adde r3, r6, r3
; CHECK-LE-NEXT: neg r3, r3
define i64 @test_llleull(i64 %a, i64 %b) {
; CHECK-LABEL: test_llleull:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: subfc r4, r3, r4
+; CHECK-NEXT: subc r4, r4, r3
; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: addi r3, r3, 1
; CHECK-NEXT: blr
define i64 @test_llleull_sext(i64 %a, i64 %b) {
; CHECK-LABEL: test_llleull_sext:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: subfc r4, r3, r4
+; CHECK-NEXT: subc r4, r4, r3
; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: not r3, r3
; CHECK-NEXT: blr
; BE-LABEL: test_llleull_store:
; BE: # %bb.0: # %entry
; BE-NEXT: addis r5, r2, .LC0@toc@ha
-; BE-NEXT: subfc r4, r3, r4
+; BE-NEXT: subc r4, r4, r3
; BE-NEXT: ld r4, .LC0@toc@l(r5)
; BE-NEXT: subfe r3, r3, r3
; BE-NEXT: addi r3, r3, 1
;
; LE-LABEL: test_llleull_store:
; LE: # %bb.0: # %entry
-; LE-NEXT: subfc r4, r3, r4
+; LE-NEXT: subc r4, r4, r3
; LE-NEXT: addis r5, r2, glob@toc@ha
; LE-NEXT: subfe r3, r3, r3
; LE-NEXT: addi r3, r3, 1
; BE-LABEL: test_llleull_sext_store:
; BE: # %bb.0: # %entry
; BE-NEXT: addis r5, r2, .LC0@toc@ha
-; BE-NEXT: subfc r4, r3, r4
+; BE-NEXT: subc r4, r4, r3
; BE-NEXT: ld r4, .LC0@toc@l(r5)
; BE-NEXT: subfe r3, r3, r3
; BE-NEXT: not r3, r3
;
; LE-LABEL: test_llleull_sext_store:
; LE: # %bb.0: # %entry
-; LE-NEXT: subfc r4, r3, r4
+; LE-NEXT: subc r4, r4, r3
; LE-NEXT: addis r5, r2, glob@toc@ha
; LE-NEXT: subfe r3, r3, r3
; LE-NEXT: not r3, r3
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sradi r5, r3, 63
; CHECK-NEXT: rldicl r6, r4, 1, 63
-; CHECK-NEXT: subfc r3, r4, r3
+; CHECK-NEXT: subc r3, r3, r4
; CHECK-NEXT: adde r3, r6, r5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sradi r5, r3, 63
; CHECK-NEXT: rldicl r6, r4, 1, 63
-; CHECK-NEXT: subfc r3, r4, r3
+; CHECK-NEXT: subc r3, r3, r4
; CHECK-NEXT: adde r3, r6, r5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3
; BE: # %bb.0: # %entry
; BE-NEXT: sradi r6, r3, 63
; BE-NEXT: addis r5, r2, .LC0@toc@ha
-; BE-NEXT: subfc r3, r4, r3
+; BE-NEXT: subc r3, r3, r4
; BE-NEXT: rldicl r3, r4, 1, 63
; BE-NEXT: ld r4, .LC0@toc@l(r5)
; BE-NEXT: adde r3, r3, r6
; LE: # %bb.0: # %entry
; LE-NEXT: sradi r6, r3, 63
; LE-NEXT: addis r5, r2, glob@toc@ha
-; LE-NEXT: subfc r3, r4, r3
+; LE-NEXT: subc r3, r3, r4
; LE-NEXT: rldicl r3, r4, 1, 63
; LE-NEXT: adde r3, r3, r6
; LE-NEXT: xori r3, r3, 1
; BE: # %bb.0: # %entry
; BE-NEXT: sradi r6, r3, 63
; BE-NEXT: addis r5, r2, .LC0@toc@ha
-; BE-NEXT: subfc r3, r4, r3
+; BE-NEXT: subc r3, r3, r4
; BE-NEXT: rldicl r3, r4, 1, 63
; BE-NEXT: ld r4, .LC0@toc@l(r5)
; BE-NEXT: adde r3, r3, r6
; LE: # %bb.0: # %entry
; LE-NEXT: sradi r6, r3, 63
; LE-NEXT: addis r5, r2, glob@toc@ha
-; LE-NEXT: subfc r3, r4, r3
+; LE-NEXT: subc r3, r3, r4
; LE-NEXT: rldicl r3, r4, 1, 63
; LE-NEXT: adde r3, r3, r6
; LE-NEXT: xori r3, r3, 1
; CHECK-NEXT: cmpwi r29, 1
; CHECK-NEXT: bc 12, lt, .LBB0_3
; CHECK-NEXT: # %bb.1: # %entry
-; CHECK-NEXT: cmpwi cr0, r4, 11
+; CHECK-NEXT: cmpwi r4, 11
; CHECK-NEXT: bc 12, lt, .LBB0_3
; CHECK-NEXT: .p2align 5
; CHECK-NEXT: .LBB0_2: # %for.body.us
; CHECK-LABEL: trunc_srl_load:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lhz 4, 2(0)
-; CHECK-NEXT: cmplw 0, 4, 3
+; CHECK-NEXT: cmplw 4, 3
; CHECK-NEXT: ble 0, .LBB0_2
; CHECK-NEXT: # %bb.1: # %exit
; CHECK-NEXT: .LBB0_2: # %cond.false
; P9BE: # %bb.0: # %entry
; P9BE-NEXT: li r3, 0
; P9BE-NEXT: vextuhlx r3, r3, v2
-; P9BE-NEXT: rlwinm r3, r3, 0, 16, 31
+; P9BE-NEXT: clrlwi r3, r3, 16
; P9BE-NEXT: mtfprwz f0, r3
; P9BE-NEXT: li r3, 2
; P9BE-NEXT: vextuhlx r3, r3, v2
-; P9BE-NEXT: rlwinm r3, r3, 0, 16, 31
+; P9BE-NEXT: clrlwi r3, r3, 16
; P9BE-NEXT: mtfprwz f1, r3
; P9BE-NEXT: xscvuxddp f0, f0
; P9BE-NEXT: xscvuxddp f1, f1
; P9LE: # %bb.0: # %entry
; P9LE-NEXT: li r3, 0
; P9LE-NEXT: vextuhrx r3, r3, v2
-; P9LE-NEXT: rlwinm r3, r3, 0, 16, 31
+; P9LE-NEXT: clrlwi r3, r3, 16
; P9LE-NEXT: mtfprwz f0, r3
; P9LE-NEXT: li r3, 2
; P9LE-NEXT: vextuhrx r3, r3, v2
-; P9LE-NEXT: rlwinm r3, r3, 0, 16, 31
+; P9LE-NEXT: clrlwi r3, r3, 16
; P9LE-NEXT: mtfprwz f1, r3
; P9LE-NEXT: xscvuxddp f0, f0
; P9LE-NEXT: xscvuxddp f1, f1
; P8BE-NEXT: mfvsrd r3, v2
; P8BE-NEXT: rldicl r4, r3, 16, 48
; P8BE-NEXT: rldicl r3, r3, 32, 48
-; P8BE-NEXT: rlwinm r4, r4, 0, 16, 31
-; P8BE-NEXT: rlwinm r3, r3, 0, 16, 31
+; P8BE-NEXT: clrlwi r4, r4, 16
+; P8BE-NEXT: clrlwi r3, r3, 16
; P8BE-NEXT: mtfprwz f0, r4
; P8BE-NEXT: mtfprwz f1, r3
; P8BE-NEXT: xscvuxddp f0, f0
; P8LE-LABEL: test1:
; P8LE: # %bb.0: # %entry
; P8LE-NEXT: xxswapd vs0, v2
-; P8LE-NEXT: mfvsrd r3, f0
+; P8LE-NEXT: mffprd r3, f0
; P8LE-NEXT: clrldi r4, r3, 48
; P8LE-NEXT: rldicl r3, r3, 48, 48
-; P8LE-NEXT: rlwinm r4, r4, 0, 16, 31
-; P8LE-NEXT: rlwinm r3, r3, 0, 16, 31
+; P8LE-NEXT: clrlwi r4, r4, 16
+; P8LE-NEXT: clrlwi r3, r3, 16
; P8LE-NEXT: mtfprwz f0, r4
; P8LE-NEXT: mtfprwz f1, r3
; P8LE-NEXT: xscvuxddp f0, f0
; P8BE-NEXT: xxsldwi vs0, v2, v2, 3
; P8BE-NEXT: mfvsrwz r4, v3
; P8BE-NEXT: mtfprwz f1, r4
-; P8BE-NEXT: mfvsrwz r3, f0
+; P8BE-NEXT: mffprwz r3, f0
; P8BE-NEXT: xscvuxddp f1, f1
; P8BE-NEXT: mtfprwz f0, r3
; P8BE-NEXT: xscvuxddp f0, f0
; P8LE: # %bb.0: # %entry
; P8LE-NEXT: xxswapd vs0, v2
; P8LE-NEXT: xxsldwi vs1, v3, v3, 1
-; P8LE-NEXT: mfvsrwz r3, f0
-; P8LE-NEXT: mfvsrwz r4, f1
+; P8LE-NEXT: mffprwz r3, f0
+; P8LE-NEXT: mffprwz r4, f1
; P8LE-NEXT: mtfprwz f0, r3
; P8LE-NEXT: mtfprwz f1, r4
; P8LE-NEXT: xscvuxddp f0, f0
; P9LE-NEXT: rldicl r4, r4, 27, 37
; P9LE-NEXT: mulli r4, r4, 98
; P9LE-NEXT: subf r3, r4, r3
-; P9LE-NEXT: mtvsrd f0, r3
+; P9LE-NEXT: mtfprd f0, r3
; P9LE-NEXT: li r3, 6
; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: rlwinm r4, r3, 0, 16, 31
; P9LE-NEXT: mulli r4, r4, 1003
; P9LE-NEXT: subf r3, r4, r3
; P9LE-NEXT: xxswapd v3, vs0
-; P9LE-NEXT: mtvsrd f0, r3
+; P9LE-NEXT: mtfprd f0, r3
; P9LE-NEXT: li r3, 2
; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: rlwinm r4, r3, 30, 18, 31
; P9LE-NEXT: mulli r4, r4, 124
; P9LE-NEXT: subf r3, r4, r3
; P9LE-NEXT: xxswapd v4, vs0
-; P9LE-NEXT: mtvsrd f0, r3
+; P9LE-NEXT: mtfprd f0, r3
; P9LE-NEXT: li r3, 0
; P9LE-NEXT: vextuhrx r3, r3, v2
-; P9LE-NEXT: rlwinm r4, r3, 0, 16, 31
+; P9LE-NEXT: clrlwi r4, r3, 16
; P9LE-NEXT: lis r6, 22765
; P9LE-NEXT: ori r6, r6, 8969
; P9LE-NEXT: vmrglh v3, v4, v3
; P9LE-NEXT: srwi r4, r4, 6
; P9LE-NEXT: mulli r4, r4, 95
; P9LE-NEXT: subf r3, r4, r3
-; P9LE-NEXT: mtvsrd f0, r3
+; P9LE-NEXT: mtfprd f0, r3
; P9LE-NEXT: xxswapd v2, vs0
; P9LE-NEXT: vmrglh v2, v4, v2
; P9LE-NEXT: vmrglw v2, v3, v2
; P9BE: # %bb.0:
; P9BE-NEXT: li r3, 6
; P9BE-NEXT: vextuhlx r3, r3, v2
-; P9BE-NEXT: rlwinm r3, r3, 0, 16, 31
+; P9BE-NEXT: clrlwi r3, r3, 16
; P9BE-NEXT: lis r5, 16727
; P9BE-NEXT: ori r5, r5, 2287
; P9BE-NEXT: clrldi r4, r3, 32
; P9BE-NEXT: mtvsrd v3, r3
; P9BE-NEXT: li r3, 4
; P9BE-NEXT: vextuhlx r3, r3, v2
-; P9BE-NEXT: rlwinm r3, r3, 0, 16, 31
+; P9BE-NEXT: clrlwi r3, r3, 16
; P9BE-NEXT: clrldi r4, r3, 32
; P9BE-NEXT: mulld r4, r4, r5
; P9BE-NEXT: lis r5, 8456
; P9BE-NEXT: mtvsrd v4, r3
; P9BE-NEXT: li r3, 0
; P9BE-NEXT: vextuhlx r3, r3, v2
-; P9BE-NEXT: rlwinm r3, r3, 0, 16, 31
+; P9BE-NEXT: clrlwi r3, r3, 16
; P9BE-NEXT: clrldi r4, r3, 32
; P9BE-NEXT: mulld r4, r4, r5
; P9BE-NEXT: rldicl r4, r4, 32, 32
; P8LE-NEXT: lis r8, 21399
; P8LE-NEXT: ori r3, r3, 8969
; P8LE-NEXT: ori r8, r8, 33437
-; P8LE-NEXT: mfvsrd r4, f0
+; P8LE-NEXT: mffprd r4, f0
; P8LE-NEXT: clrldi r5, r4, 48
; P8LE-NEXT: rldicl r9, r4, 32, 48
-; P8LE-NEXT: rlwinm r6, r5, 0, 16, 31
+; P8LE-NEXT: clrlwi r6, r5, 16
; P8LE-NEXT: rldicl r10, r4, 16, 48
; P8LE-NEXT: rlwinm r11, r9, 0, 16, 31
; P8LE-NEXT: clrldi r7, r6, 32
; P8LE-NEXT: mulli r8, r8, 124
; P8LE-NEXT: subf r7, r7, r9
; P8LE-NEXT: subf r6, r6, r10
-; P8LE-NEXT: mtvsrd f0, r7
+; P8LE-NEXT: mtfprd f0, r7
; P8LE-NEXT: subf r3, r3, r5
; P8LE-NEXT: subf r4, r8, r4
-; P8LE-NEXT: mtvsrd f1, r6
-; P8LE-NEXT: mtvsrd f2, r3
+; P8LE-NEXT: mtfprd f1, r6
+; P8LE-NEXT: mtfprd f2, r3
; P8LE-NEXT: xxswapd v2, vs0
-; P8LE-NEXT: mtvsrd f3, r4
+; P8LE-NEXT: mtfprd f3, r4
; P8LE-NEXT: xxswapd v3, vs1
; P8LE-NEXT: xxswapd v4, vs2
; P8LE-NEXT: xxswapd v5, vs3
; P8BE-NEXT: ori r9, r9, 2287
; P8BE-NEXT: rldicl r5, r4, 16, 48
; P8BE-NEXT: clrldi r6, r4, 48
-; P8BE-NEXT: rlwinm r5, r5, 0, 16, 31
+; P8BE-NEXT: clrlwi r5, r5, 16
; P8BE-NEXT: rldicl r7, r4, 48, 48
-; P8BE-NEXT: rlwinm r6, r6, 0, 16, 31
+; P8BE-NEXT: clrlwi r6, r6, 16
; P8BE-NEXT: clrldi r8, r5, 32
-; P8BE-NEXT: rlwinm r7, r7, 0, 16, 31
+; P8BE-NEXT: clrlwi r7, r7, 16
; P8BE-NEXT: mulld r3, r8, r3
; P8BE-NEXT: lis r8, 21399
; P8BE-NEXT: clrldi r10, r6, 32
; P8BE-NEXT: ori r10, r10, 16913
; P8BE-NEXT: rlwinm r11, r4, 30, 18, 31
; P8BE-NEXT: rldicl r3, r3, 32, 32
-; P8BE-NEXT: rlwinm r4, r4, 0, 16, 31
+; P8BE-NEXT: clrlwi r4, r4, 16
; P8BE-NEXT: mulld r10, r11, r10
; P8BE-NEXT: subf r11, r3, r5
; P8BE-NEXT: srwi r11, r11, 1
; P9LE: # %bb.0:
; P9LE-NEXT: li r3, 0
; P9LE-NEXT: vextuhrx r3, r3, v2
-; P9LE-NEXT: rlwinm r4, r3, 0, 16, 31
+; P9LE-NEXT: clrlwi r4, r3, 16
; P9LE-NEXT: lis r6, 22765
; P9LE-NEXT: ori r6, r6, 8969
; P9LE-NEXT: clrldi r5, r4, 32
; P9LE-NEXT: srwi r4, r4, 6
; P9LE-NEXT: mulli r4, r4, 95
; P9LE-NEXT: subf r3, r4, r3
-; P9LE-NEXT: mtvsrd f0, r3
+; P9LE-NEXT: mtfprd f0, r3
; P9LE-NEXT: li r3, 2
; P9LE-NEXT: vextuhrx r3, r3, v2
-; P9LE-NEXT: rlwinm r4, r3, 0, 16, 31
+; P9LE-NEXT: clrlwi r4, r3, 16
; P9LE-NEXT: clrldi r5, r4, 32
; P9LE-NEXT: mulld r5, r5, r6
; P9LE-NEXT: rldicl r5, r5, 32, 32
; P9LE-NEXT: mulli r4, r4, 95
; P9LE-NEXT: subf r3, r4, r3
; P9LE-NEXT: xxswapd v3, vs0
-; P9LE-NEXT: mtvsrd f0, r3
+; P9LE-NEXT: mtfprd f0, r3
; P9LE-NEXT: li r3, 4
; P9LE-NEXT: vextuhrx r3, r3, v2
-; P9LE-NEXT: rlwinm r4, r3, 0, 16, 31
+; P9LE-NEXT: clrlwi r4, r3, 16
; P9LE-NEXT: clrldi r5, r4, 32
; P9LE-NEXT: mulld r5, r5, r6
; P9LE-NEXT: rldicl r5, r5, 32, 32
; P9LE-NEXT: mulli r4, r4, 95
; P9LE-NEXT: subf r3, r4, r3
; P9LE-NEXT: xxswapd v4, vs0
-; P9LE-NEXT: mtvsrd f0, r3
+; P9LE-NEXT: mtfprd f0, r3
; P9LE-NEXT: li r3, 6
; P9LE-NEXT: vextuhrx r3, r3, v2
-; P9LE-NEXT: rlwinm r4, r3, 0, 16, 31
+; P9LE-NEXT: clrlwi r4, r3, 16
; P9LE-NEXT: clrldi r5, r4, 32
; P9LE-NEXT: mulld r5, r5, r6
; P9LE-NEXT: rldicl r5, r5, 32, 32
; P9LE-NEXT: subf r3, r4, r3
; P9LE-NEXT: vmrglh v3, v4, v3
; P9LE-NEXT: xxswapd v4, vs0
-; P9LE-NEXT: mtvsrd f0, r3
+; P9LE-NEXT: mtfprd f0, r3
; P9LE-NEXT: xxswapd v2, vs0
; P9LE-NEXT: vmrglh v2, v2, v4
; P9LE-NEXT: vmrglw v2, v2, v3
; P9BE: # %bb.0:
; P9BE-NEXT: li r3, 6
; P9BE-NEXT: vextuhlx r3, r3, v2
-; P9BE-NEXT: rlwinm r3, r3, 0, 16, 31
+; P9BE-NEXT: clrlwi r3, r3, 16
; P9BE-NEXT: lis r5, 22765
; P9BE-NEXT: ori r5, r5, 8969
; P9BE-NEXT: clrldi r4, r3, 32
; P9BE-NEXT: mtvsrd v3, r3
; P9BE-NEXT: li r3, 4
; P9BE-NEXT: vextuhlx r3, r3, v2
-; P9BE-NEXT: rlwinm r3, r3, 0, 16, 31
+; P9BE-NEXT: clrlwi r3, r3, 16
; P9BE-NEXT: clrldi r4, r3, 32
; P9BE-NEXT: mulld r4, r4, r5
; P9BE-NEXT: rldicl r4, r4, 32, 32
; P9BE-NEXT: mtvsrd v4, r3
; P9BE-NEXT: li r3, 2
; P9BE-NEXT: vextuhlx r3, r3, v2
-; P9BE-NEXT: rlwinm r3, r3, 0, 16, 31
+; P9BE-NEXT: clrlwi r3, r3, 16
; P9BE-NEXT: clrldi r4, r3, 32
; P9BE-NEXT: mulld r4, r4, r5
; P9BE-NEXT: rldicl r4, r4, 32, 32
; P9BE-NEXT: mtvsrd v4, r3
; P9BE-NEXT: li r3, 0
; P9BE-NEXT: vextuhlx r3, r3, v2
-; P9BE-NEXT: rlwinm r3, r3, 0, 16, 31
+; P9BE-NEXT: clrlwi r3, r3, 16
; P9BE-NEXT: clrldi r4, r3, 32
; P9BE-NEXT: mulld r4, r4, r5
; P9BE-NEXT: rldicl r4, r4, 32, 32
; P8LE-NEXT: std r29, -24(r1) # 8-byte Folded Spill
; P8LE-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; P8LE-NEXT: ori r4, r4, 8969
-; P8LE-NEXT: mfvsrd r5, f0
+; P8LE-NEXT: mffprd r5, f0
; P8LE-NEXT: clrldi r3, r5, 48
; P8LE-NEXT: rldicl r6, r5, 48, 48
-; P8LE-NEXT: rlwinm r8, r3, 0, 16, 31
+; P8LE-NEXT: clrlwi r8, r3, 16
; P8LE-NEXT: rldicl r7, r5, 32, 48
-; P8LE-NEXT: rlwinm r9, r6, 0, 16, 31
+; P8LE-NEXT: clrlwi r9, r6, 16
; P8LE-NEXT: rldicl r5, r5, 16, 48
; P8LE-NEXT: clrldi r11, r8, 32
-; P8LE-NEXT: rlwinm r10, r7, 0, 16, 31
-; P8LE-NEXT: rlwinm r12, r5, 0, 16, 31
+; P8LE-NEXT: clrlwi r10, r7, 16
+; P8LE-NEXT: clrlwi r12, r5, 16
; P8LE-NEXT: mulld r11, r11, r4
; P8LE-NEXT: clrldi r0, r9, 32
; P8LE-NEXT: clrldi r30, r10, 32
; P8LE-NEXT: mulli r4, r4, 95
; P8LE-NEXT: subf r3, r8, r3
; P8LE-NEXT: subf r6, r9, r6
-; P8LE-NEXT: mtvsrd f0, r3
+; P8LE-NEXT: mtfprd f0, r3
; P8LE-NEXT: subf r3, r10, r7
; P8LE-NEXT: subf r4, r4, r5
-; P8LE-NEXT: mtvsrd f1, r6
-; P8LE-NEXT: mtvsrd f2, r3
+; P8LE-NEXT: mtfprd f1, r6
+; P8LE-NEXT: mtfprd f2, r3
; P8LE-NEXT: xxswapd v2, vs0
-; P8LE-NEXT: mtvsrd f3, r4
+; P8LE-NEXT: mtfprd f3, r4
; P8LE-NEXT: xxswapd v3, vs1
; P8LE-NEXT: xxswapd v4, vs2
; P8LE-NEXT: xxswapd v5, vs3
; P8BE-NEXT: ori r3, r3, 8969
; P8BE-NEXT: clrldi r5, r4, 48
; P8BE-NEXT: rldicl r6, r4, 48, 48
-; P8BE-NEXT: rlwinm r5, r5, 0, 16, 31
+; P8BE-NEXT: clrlwi r5, r5, 16
; P8BE-NEXT: rldicl r7, r4, 32, 48
-; P8BE-NEXT: rlwinm r6, r6, 0, 16, 31
+; P8BE-NEXT: clrlwi r6, r6, 16
; P8BE-NEXT: clrldi r8, r5, 32
; P8BE-NEXT: rldicl r4, r4, 16, 48
-; P8BE-NEXT: rlwinm r7, r7, 0, 16, 31
+; P8BE-NEXT: clrlwi r7, r7, 16
; P8BE-NEXT: clrldi r9, r6, 32
; P8BE-NEXT: mulld r8, r8, r3
-; P8BE-NEXT: rlwinm r4, r4, 0, 16, 31
+; P8BE-NEXT: clrlwi r4, r4, 16
; P8BE-NEXT: clrldi r10, r7, 32
; P8BE-NEXT: mulld r9, r9, r3
; P8BE-NEXT: clrldi r11, r4, 32
; P9LE: # %bb.0:
; P9LE-NEXT: li r3, 0
; P9LE-NEXT: vextuhrx r3, r3, v2
-; P9LE-NEXT: rlwinm r4, r3, 0, 16, 31
+; P9LE-NEXT: clrlwi r4, r3, 16
; P9LE-NEXT: lis r6, 22765
; P9LE-NEXT: ori r6, r6, 8969
; P9LE-NEXT: clrldi r5, r4, 32
; P9LE-NEXT: srwi r4, r4, 6
; P9LE-NEXT: mulli r5, r4, 95
; P9LE-NEXT: subf r3, r5, r3
-; P9LE-NEXT: mtvsrd f0, r3
+; P9LE-NEXT: mtfprd f0, r3
; P9LE-NEXT: li r3, 2
; P9LE-NEXT: vextuhrx r3, r3, v2
-; P9LE-NEXT: rlwinm r5, r3, 0, 16, 31
+; P9LE-NEXT: clrlwi r5, r3, 16
; P9LE-NEXT: clrldi r7, r5, 32
; P9LE-NEXT: mulld r7, r7, r6
; P9LE-NEXT: rldicl r7, r7, 32, 32
; P9LE-NEXT: mulli r7, r5, 95
; P9LE-NEXT: subf r3, r7, r3
; P9LE-NEXT: xxswapd v3, vs0
-; P9LE-NEXT: mtvsrd f0, r3
+; P9LE-NEXT: mtfprd f0, r3
; P9LE-NEXT: li r3, 4
; P9LE-NEXT: vextuhrx r3, r3, v2
-; P9LE-NEXT: rlwinm r7, r3, 0, 16, 31
+; P9LE-NEXT: clrlwi r7, r3, 16
; P9LE-NEXT: clrldi r8, r7, 32
; P9LE-NEXT: mulld r8, r8, r6
; P9LE-NEXT: rldicl r8, r8, 32, 32
; P9LE-NEXT: mulli r8, r7, 95
; P9LE-NEXT: subf r3, r8, r3
; P9LE-NEXT: xxswapd v4, vs0
-; P9LE-NEXT: mtvsrd f0, r3
+; P9LE-NEXT: mtfprd f0, r3
; P9LE-NEXT: li r3, 6
; P9LE-NEXT: vextuhrx r3, r3, v2
-; P9LE-NEXT: rlwinm r8, r3, 0, 16, 31
+; P9LE-NEXT: clrlwi r8, r3, 16
; P9LE-NEXT: clrldi r9, r8, 32
; P9LE-NEXT: mulld r6, r9, r6
; P9LE-NEXT: rldicl r6, r6, 32, 32
; P9LE-NEXT: subf r3, r8, r3
; P9LE-NEXT: vmrglh v3, v4, v3
; P9LE-NEXT: xxswapd v4, vs0
-; P9LE-NEXT: mtvsrd f0, r3
+; P9LE-NEXT: mtfprd f0, r3
; P9LE-NEXT: xxswapd v2, vs0
-; P9LE-NEXT: mtvsrd f0, r4
+; P9LE-NEXT: mtfprd f0, r4
; P9LE-NEXT: vmrglh v2, v2, v4
; P9LE-NEXT: vmrglw v2, v2, v3
; P9LE-NEXT: xxswapd v3, vs0
-; P9LE-NEXT: mtvsrd f0, r5
+; P9LE-NEXT: mtfprd f0, r5
; P9LE-NEXT: xxswapd v4, vs0
-; P9LE-NEXT: mtvsrd f0, r7
+; P9LE-NEXT: mtfprd f0, r7
; P9LE-NEXT: vmrglh v3, v4, v3
; P9LE-NEXT: xxswapd v4, vs0
-; P9LE-NEXT: mtvsrd f0, r6
+; P9LE-NEXT: mtfprd f0, r6
; P9LE-NEXT: xxswapd v5, vs0
; P9LE-NEXT: vmrglh v4, v5, v4
; P9LE-NEXT: vmrglw v3, v4, v3
; P9BE: # %bb.0:
; P9BE-NEXT: li r3, 6
; P9BE-NEXT: vextuhlx r3, r3, v2
-; P9BE-NEXT: rlwinm r4, r3, 0, 16, 31
+; P9BE-NEXT: clrlwi r4, r3, 16
; P9BE-NEXT: lis r6, 22765
; P9BE-NEXT: ori r6, r6, 8969
; P9BE-NEXT: clrldi r5, r4, 32
; P9BE-NEXT: mtvsrd v3, r3
; P9BE-NEXT: li r3, 4
; P9BE-NEXT: vextuhlx r3, r3, v2
-; P9BE-NEXT: rlwinm r5, r3, 0, 16, 31
+; P9BE-NEXT: clrlwi r5, r3, 16
; P9BE-NEXT: clrldi r7, r5, 32
; P9BE-NEXT: mulld r7, r7, r6
; P9BE-NEXT: rldicl r7, r7, 32, 32
; P9BE-NEXT: mtvsrd v4, r3
; P9BE-NEXT: li r3, 2
; P9BE-NEXT: vextuhlx r3, r3, v2
-; P9BE-NEXT: rlwinm r7, r3, 0, 16, 31
+; P9BE-NEXT: clrlwi r7, r3, 16
; P9BE-NEXT: clrldi r8, r7, 32
; P9BE-NEXT: mulld r8, r8, r6
; P9BE-NEXT: rldicl r8, r8, 32, 32
; P9BE-NEXT: mtvsrd v4, r3
; P9BE-NEXT: li r3, 0
; P9BE-NEXT: vextuhlx r3, r3, v2
-; P9BE-NEXT: rlwinm r3, r3, 0, 16, 31
+; P9BE-NEXT: clrlwi r3, r3, 16
; P9BE-NEXT: clrldi r8, r3, 32
; P9BE-NEXT: mulld r6, r8, r6
; P9BE-NEXT: rldicl r6, r6, 32, 32
; P8LE-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; P8LE-NEXT: std r29, -24(r1) # 8-byte Folded Spill
; P8LE-NEXT: ori r5, r5, 8969
-; P8LE-NEXT: mfvsrd r6, f0
+; P8LE-NEXT: mffprd r6, f0
; P8LE-NEXT: clrldi r3, r6, 48
; P8LE-NEXT: rldicl r4, r6, 48, 48
; P8LE-NEXT: rldicl r7, r6, 32, 48
-; P8LE-NEXT: rlwinm r8, r3, 0, 16, 31
-; P8LE-NEXT: rlwinm r9, r4, 0, 16, 31
+; P8LE-NEXT: clrlwi r8, r3, 16
+; P8LE-NEXT: clrlwi r9, r4, 16
; P8LE-NEXT: rldicl r6, r6, 16, 48
-; P8LE-NEXT: rlwinm r10, r7, 0, 16, 31
+; P8LE-NEXT: clrlwi r10, r7, 16
; P8LE-NEXT: clrldi r11, r8, 32
-; P8LE-NEXT: rlwinm r12, r6, 0, 16, 31
+; P8LE-NEXT: clrlwi r12, r6, 16
; P8LE-NEXT: clrldi r0, r9, 32
; P8LE-NEXT: clrldi r30, r10, 32
; P8LE-NEXT: mulld r11, r11, r5
; P8LE-NEXT: mulli r12, r8, 95
; P8LE-NEXT: srwi r10, r10, 6
; P8LE-NEXT: add r5, r11, r5
-; P8LE-NEXT: mtvsrd f0, r8
+; P8LE-NEXT: mtfprd f0, r8
; P8LE-NEXT: mulli r8, r9, 95
-; P8LE-NEXT: mtvsrd f1, r9
+; P8LE-NEXT: mtfprd f1, r9
; P8LE-NEXT: mulli r9, r10, 95
; P8LE-NEXT: srwi r5, r5, 6
-; P8LE-NEXT: mtvsrd f3, r5
+; P8LE-NEXT: mtfprd f3, r5
; P8LE-NEXT: mulli r5, r5, 95
; P8LE-NEXT: xxswapd v2, vs0
; P8LE-NEXT: xxswapd v3, vs1
-; P8LE-NEXT: mtvsrd f2, r10
+; P8LE-NEXT: mtfprd f2, r10
; P8LE-NEXT: subf r3, r12, r3
; P8LE-NEXT: xxswapd v6, vs3
-; P8LE-NEXT: mtvsrd f0, r3
+; P8LE-NEXT: mtfprd f0, r3
; P8LE-NEXT: subf r3, r9, r7
; P8LE-NEXT: subf r4, r8, r4
; P8LE-NEXT: xxswapd v1, vs2
-; P8LE-NEXT: mtvsrd f4, r3
+; P8LE-NEXT: mtfprd f4, r3
; P8LE-NEXT: subf r3, r5, r6
-; P8LE-NEXT: mtvsrd f1, r4
-; P8LE-NEXT: mtvsrd f5, r3
+; P8LE-NEXT: mtfprd f1, r4
+; P8LE-NEXT: mtfprd f5, r3
; P8LE-NEXT: xxswapd v5, vs4
; P8LE-NEXT: vmrglh v2, v3, v2
; P8LE-NEXT: xxswapd v3, vs0
; P8BE-NEXT: ori r5, r5, 8969
; P8BE-NEXT: clrldi r3, r6, 48
; P8BE-NEXT: rldicl r4, r6, 48, 48
-; P8BE-NEXT: rlwinm r8, r3, 0, 16, 31
+; P8BE-NEXT: clrlwi r8, r3, 16
; P8BE-NEXT: rldicl r7, r6, 32, 48
-; P8BE-NEXT: rlwinm r9, r4, 0, 16, 31
+; P8BE-NEXT: clrlwi r9, r4, 16
; P8BE-NEXT: rldicl r6, r6, 16, 48
; P8BE-NEXT: clrldi r11, r8, 32
-; P8BE-NEXT: rlwinm r10, r7, 0, 16, 31
-; P8BE-NEXT: rlwinm r6, r6, 0, 16, 31
+; P8BE-NEXT: clrlwi r10, r7, 16
+; P8BE-NEXT: clrlwi r6, r6, 16
; P8BE-NEXT: clrldi r12, r9, 32
; P8BE-NEXT: mulld r11, r11, r5
; P8BE-NEXT: clrldi r0, r10, 32
; P9LE: # %bb.0:
; P9LE-NEXT: li r3, 0
; P9LE-NEXT: vextuhrx r3, r3, v2
-; P9LE-NEXT: rlwinm r3, r3, 0, 26, 31
-; P9LE-NEXT: mtvsrd f0, r3
+; P9LE-NEXT: clrlwi r3, r3, 26
+; P9LE-NEXT: mtfprd f0, r3
; P9LE-NEXT: li r3, 2
; P9LE-NEXT: vextuhrx r3, r3, v2
-; P9LE-NEXT: rlwinm r3, r3, 0, 27, 31
+; P9LE-NEXT: clrlwi r3, r3, 27
; P9LE-NEXT: xxswapd v3, vs0
-; P9LE-NEXT: mtvsrd f0, r3
+; P9LE-NEXT: mtfprd f0, r3
; P9LE-NEXT: li r3, 6
; P9LE-NEXT: vextuhrx r3, r3, v2
-; P9LE-NEXT: rlwinm r4, r3, 0, 16, 31
+; P9LE-NEXT: clrlwi r4, r3, 16
; P9LE-NEXT: lis r6, 22765
; P9LE-NEXT: ori r6, r6, 8969
; P9LE-NEXT: xxswapd v4, vs0
; P9LE-NEXT: srwi r4, r4, 6
; P9LE-NEXT: mulli r4, r4, 95
; P9LE-NEXT: subf r3, r4, r3
-; P9LE-NEXT: mtvsrd f0, r3
+; P9LE-NEXT: mtfprd f0, r3
; P9LE-NEXT: li r3, 4
; P9LE-NEXT: vextuhrx r3, r3, v2
-; P9LE-NEXT: rlwinm r3, r3, 0, 29, 31
+; P9LE-NEXT: clrlwi r3, r3, 29
; P9LE-NEXT: xxswapd v4, vs0
-; P9LE-NEXT: mtvsrd f0, r3
+; P9LE-NEXT: mtfprd f0, r3
; P9LE-NEXT: xxswapd v2, vs0
; P9LE-NEXT: vmrglh v2, v4, v2
; P9LE-NEXT: vmrglw v2, v2, v3
; P9BE: # %bb.0:
; P9BE-NEXT: li r3, 2
; P9BE-NEXT: vextuhlx r3, r3, v2
-; P9BE-NEXT: rlwinm r3, r3, 0, 27, 31
+; P9BE-NEXT: clrlwi r3, r3, 27
; P9BE-NEXT: sldi r3, r3, 48
; P9BE-NEXT: mtvsrd v3, r3
; P9BE-NEXT: li r3, 0
; P9BE-NEXT: vextuhlx r3, r3, v2
-; P9BE-NEXT: rlwinm r3, r3, 0, 26, 31
+; P9BE-NEXT: clrlwi r3, r3, 26
; P9BE-NEXT: sldi r3, r3, 48
; P9BE-NEXT: mtvsrd v4, r3
; P9BE-NEXT: li r3, 6
; P9BE-NEXT: vextuhlx r3, r3, v2
-; P9BE-NEXT: rlwinm r3, r3, 0, 16, 31
+; P9BE-NEXT: clrlwi r3, r3, 16
; P9BE-NEXT: lis r5, 22765
; P9BE-NEXT: ori r5, r5, 8969
; P9BE-NEXT: vmrghh v3, v4, v3
; P9BE-NEXT: mtvsrd v4, r3
; P9BE-NEXT: li r3, 4
; P9BE-NEXT: vextuhlx r3, r3, v2
-; P9BE-NEXT: rlwinm r3, r3, 0, 29, 31
+; P9BE-NEXT: clrlwi r3, r3, 29
; P9BE-NEXT: sldi r3, r3, 48
; P9BE-NEXT: mtvsrd v2, r3
; P9BE-NEXT: vmrghh v2, v2, v4
; P8LE-NEXT: xxswapd vs0, v2
; P8LE-NEXT: lis r3, 22765
; P8LE-NEXT: ori r3, r3, 8969
-; P8LE-NEXT: mfvsrd r4, f0
+; P8LE-NEXT: mffprd r4, f0
; P8LE-NEXT: rldicl r5, r4, 16, 48
-; P8LE-NEXT: rlwinm r6, r5, 0, 16, 31
+; P8LE-NEXT: clrlwi r6, r5, 16
; P8LE-NEXT: clrldi r7, r6, 32
; P8LE-NEXT: mulld r3, r7, r3
; P8LE-NEXT: rldicl r7, r4, 48, 48
-; P8LE-NEXT: rlwinm r7, r7, 0, 27, 31
-; P8LE-NEXT: mtvsrd f1, r7
+; P8LE-NEXT: clrlwi r7, r7, 27
+; P8LE-NEXT: mtfprd f1, r7
; P8LE-NEXT: rldicl r3, r3, 32, 32
; P8LE-NEXT: xxswapd v3, vs1
; P8LE-NEXT: subf r6, r3, r6
; P8LE-NEXT: clrldi r6, r4, 48
; P8LE-NEXT: srwi r3, r3, 6
; P8LE-NEXT: rldicl r4, r4, 32, 48
-; P8LE-NEXT: rlwinm r6, r6, 0, 26, 31
+; P8LE-NEXT: clrlwi r6, r6, 26
; P8LE-NEXT: mulli r3, r3, 95
-; P8LE-NEXT: rlwinm r4, r4, 0, 29, 31
-; P8LE-NEXT: mtvsrd f0, r6
-; P8LE-NEXT: mtvsrd f3, r4
+; P8LE-NEXT: clrlwi r4, r4, 29
+; P8LE-NEXT: mtfprd f0, r6
+; P8LE-NEXT: mtfprd f3, r4
; P8LE-NEXT: xxswapd v2, vs0
; P8LE-NEXT: xxswapd v5, vs3
; P8LE-NEXT: subf r3, r3, r5
-; P8LE-NEXT: mtvsrd f2, r3
+; P8LE-NEXT: mtfprd f2, r3
; P8LE-NEXT: vmrglh v2, v3, v2
; P8LE-NEXT: xxswapd v4, vs2
; P8LE-NEXT: vmrglh v3, v4, v5
; P8BE-NEXT: ori r3, r3, 8969
; P8BE-NEXT: clrldi r5, r4, 48
; P8BE-NEXT: rldicl r7, r4, 16, 48
-; P8BE-NEXT: rlwinm r5, r5, 0, 16, 31
-; P8BE-NEXT: rlwinm r7, r7, 0, 26, 31
+; P8BE-NEXT: clrlwi r5, r5, 16
+; P8BE-NEXT: clrlwi r7, r7, 26
; P8BE-NEXT: clrldi r6, r5, 32
; P8BE-NEXT: mulld r3, r6, r3
; P8BE-NEXT: rldicl r3, r3, 32, 32
; P8BE-NEXT: rldicl r6, r4, 32, 48
; P8BE-NEXT: srwi r3, r3, 6
; P8BE-NEXT: rldicl r4, r4, 48, 48
-; P8BE-NEXT: rlwinm r6, r6, 0, 27, 31
+; P8BE-NEXT: clrlwi r6, r6, 27
; P8BE-NEXT: mulli r3, r3, 95
; P8BE-NEXT: sldi r6, r6, 48
-; P8BE-NEXT: rlwinm r4, r4, 0, 29, 31
+; P8BE-NEXT: clrlwi r4, r4, 29
; P8BE-NEXT: mtvsrd v2, r6
; P8BE-NEXT: sldi r6, r7, 48
; P8BE-NEXT: sldi r4, r4, 48
; P9LE-NEXT: rldicl r4, r4, 28, 36
; P9LE-NEXT: mulli r4, r4, 23
; P9LE-NEXT: subf r3, r4, r3
-; P9LE-NEXT: mtvsrd f0, r3
+; P9LE-NEXT: mtfprd f0, r3
; P9LE-NEXT: li r3, 6
; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: rlwinm r4, r3, 0, 16, 31
; P9LE-NEXT: mulli r4, r4, 5423
; P9LE-NEXT: subf r3, r4, r3
; P9LE-NEXT: xxswapd v3, vs0
-; P9LE-NEXT: mtvsrd f0, r3
+; P9LE-NEXT: mtfprd f0, r3
; P9LE-NEXT: li r3, 2
; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: rlwinm r4, r3, 31, 17, 31
; P9LE-NEXT: mulli r4, r4, 654
; P9LE-NEXT: subf r3, r4, r3
; P9LE-NEXT: xxswapd v4, vs0
-; P9LE-NEXT: mtvsrd f0, r3
+; P9LE-NEXT: mtfprd f0, r3
; P9LE-NEXT: xxswapd v2, vs0
; P9LE-NEXT: vmrglh v3, v4, v3
; P9LE-NEXT: xxlxor v4, v4, v4
; P9BE: # %bb.0:
; P9BE-NEXT: li r3, 6
; P9BE-NEXT: vextuhlx r3, r3, v2
-; P9BE-NEXT: rlwinm r3, r3, 0, 16, 31
+; P9BE-NEXT: clrlwi r3, r3, 16
; P9BE-NEXT: lis r5, 24749
; P9BE-NEXT: ori r5, r5, 47143
; P9BE-NEXT: clrldi r4, r3, 32
; P9BE-NEXT: mtvsrd v3, r3
; P9BE-NEXT: li r3, 4
; P9BE-NEXT: vextuhlx r3, r3, v2
-; P9BE-NEXT: rlwinm r3, r3, 0, 16, 31
+; P9BE-NEXT: clrlwi r3, r3, 16
; P9BE-NEXT: clrldi r4, r3, 32
; P9BE-NEXT: mulld r4, r4, r6
; P9BE-NEXT: rldicl r4, r4, 28, 36
; P8LE-NEXT: oris r3, r3, 51306
; P8LE-NEXT: ori r5, r5, 17097
; P8LE-NEXT: ori r3, r3, 30865
-; P8LE-NEXT: mfvsrd r4, f0
+; P8LE-NEXT: mffprd r4, f0
; P8LE-NEXT: rldicl r6, r4, 32, 48
; P8LE-NEXT: rldicl r7, r4, 16, 48
; P8LE-NEXT: rlwinm r9, r6, 0, 16, 31
; P8LE-NEXT: mulli r3, r3, 654
; P8LE-NEXT: subf r5, r5, r6
; P8LE-NEXT: subf r6, r8, r7
-; P8LE-NEXT: mtvsrd f0, r5
+; P8LE-NEXT: mtfprd f0, r5
; P8LE-NEXT: subf r3, r3, r4
-; P8LE-NEXT: mtvsrd f1, r6
-; P8LE-NEXT: mtvsrd f2, r3
+; P8LE-NEXT: mtfprd f1, r6
+; P8LE-NEXT: mtfprd f2, r3
; P8LE-NEXT: xxswapd v2, vs0
; P8LE-NEXT: xxswapd v3, vs1
; P8LE-NEXT: xxswapd v4, vs2
; P8BE-NEXT: ori r3, r3, 17097
; P8BE-NEXT: rldicl r4, r4, 48, 48
; P8BE-NEXT: rlwinm r9, r5, 31, 17, 31
-; P8BE-NEXT: rlwinm r7, r7, 0, 16, 31
-; P8BE-NEXT: rlwinm r5, r5, 0, 16, 31
-; P8BE-NEXT: rlwinm r4, r4, 0, 16, 31
+; P8BE-NEXT: clrlwi r7, r7, 16
+; P8BE-NEXT: clrlwi r5, r5, 16
+; P8BE-NEXT: clrlwi r4, r4, 16
; P8BE-NEXT: mulld r6, r9, r6
; P8BE-NEXT: clrldi r9, r7, 32
; P8BE-NEXT: mulld r8, r9, r8
; P8LE-NEXT: sldi r3, r3, 32
; P8LE-NEXT: sldi r4, r4, 32
; P8LE-NEXT: oris r3, r3, 45590
-; P8LE-NEXT: mfvsrd r7, f0
+; P8LE-NEXT: mffprd r7, f0
; P8LE-NEXT: sldi r5, r5, 32
; P8LE-NEXT: oris r4, r4, 52170
; P8LE-NEXT: ori r3, r3, 17097
; P8LE-NEXT: mulli r3, r3, 23
; P8LE-NEXT: sub r4, r8, r4
; P8LE-NEXT: sub r5, r6, r5
-; P8LE-NEXT: mtvsrd f0, r4
+; P8LE-NEXT: mtfprd f0, r4
; P8LE-NEXT: sub r3, r7, r3
; P8LE-NEXT: li r4, 0
-; P8LE-NEXT: mtvsrd f1, r5
-; P8LE-NEXT: mtvsrd f2, r3
-; P8LE-NEXT: mtvsrd f3, r4
+; P8LE-NEXT: mtfprd f1, r5
+; P8LE-NEXT: mtfprd f2, r3
+; P8LE-NEXT: mtfprd f3, r4
; P8LE-NEXT: xxmrghd v3, vs0, vs2
; P8LE-NEXT: xxmrghd v2, vs1, vs3
; P8LE-NEXT: blr
; P8BE-NEXT: sldi r4, r4, 32
; P8BE-NEXT: oris r3, r3, 45590
; P8BE-NEXT: sldi r5, r5, 32
-; P8BE-NEXT: mfvsrd r7, f0
+; P8BE-NEXT: mffprd r7, f0
; P8BE-NEXT: oris r4, r4, 52170
; P8BE-NEXT: ori r3, r3, 17097
-; P8BE-NEXT: mfvsrd r8, f1
+; P8BE-NEXT: mffprd r8, f1
; P8BE-NEXT: oris r5, r5, 1603
; P8BE-NEXT: ori r4, r4, 12109
; P8BE-NEXT: mulhdu r3, r6, r3
; P8BE-NEXT: mulli r5, r5, 654
; P8BE-NEXT: mulli r3, r3, 23
; P8BE-NEXT: sub r4, r7, r4
-; P8BE-NEXT: mtvsrd f0, r4
+; P8BE-NEXT: mtfprd f0, r4
; P8BE-NEXT: sub r4, r8, r5
; P8BE-NEXT: sub r3, r6, r3
-; P8BE-NEXT: mtvsrd f1, r4
+; P8BE-NEXT: mtfprd f1, r4
; P8BE-NEXT: li r4, 0
-; P8BE-NEXT: mtvsrd f2, r3
-; P8BE-NEXT: mtvsrd f3, r4
+; P8BE-NEXT: mtfprd f2, r3
+; P8BE-NEXT: mtfprd f3, r4
; P8BE-NEXT: xxmrghd v3, vs2, vs0
; P8BE-NEXT: xxmrghd v2, vs3, vs1
; P8BE-NEXT: blr
; CHECK-NEXT: xxswapd 1, 34
; CHECK-NEXT: cmpld 4, 3
; CHECK-NEXT: cmpd 1, 4, 3
-; CHECK-NEXT: mfvsrd 3, 0
+; CHECK-NEXT: mffprd 3, 0
; CHECK-NEXT: crandc 20, 4, 2
-; CHECK-NEXT: mfvsrd 4, 1
+; CHECK-NEXT: mffprd 4, 1
; CHECK-NEXT: cmpld 1, 4, 3
; CHECK-NEXT: bc 12, 20, .LBB12_3
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: .LBB12_3:
; CHECK-NEXT: xxswapd 0, 34
; CHECK-NEXT: mfvsrd 4, 34
-; CHECK-NEXT: mfvsrd 3, 0
+; CHECK-NEXT: mffprd 3, 0
; CHECK-NEXT: blr
;
; NOP8VEC-LABEL: invalidv1i128:
; CHECK-NEXT: lvx v2, 0, r4
; CHECK-NEXT: vpkuhum v2, v2, v2
; CHECK-NEXT: xxswapd vs0, v2
-; CHECK-NEXT: mfvsrd r4, f0
+; CHECK-NEXT: mffprd r4, f0
; CHECK-NEXT: clrldi r4, r4, 48
; CHECK-NEXT: sth r4, 0(r3)
; CHECK-NEXT: blr
define <2 x i64> @increment_by_val(<2 x i64> %x, i64 %val) nounwind {
; VSX-LABEL: increment_by_val:
; VSX: # %bb.0:
-; VSX-NEXT: mtvsrd 0, 5
+; VSX-NEXT: mtfprd 0, 5
; VSX-NEXT: xxspltd 35, 0, 0
; VSX-NEXT: vaddudm 2, 2, 3
; VSX-NEXT: blr
define <2 x i64> @decrement_by_val(<2 x i64> %x, i64 %val) nounwind {
; VSX-LABEL: decrement_by_val:
; VSX: # %bb.0:
-; VSX-NEXT: mtvsrd 0, 5
+; VSX-NEXT: mtfprd 0, 5
; VSX-NEXT: xxspltd 35, 0, 0
; VSX-NEXT: vsubudm 2, 2, 3
; VSX-NEXT: blr
define <1 x i128> @increment_by_val(<1 x i128> %x, i128 %val) nounwind {
; VSX-LABEL: increment_by_val:
; VSX: # %bb.0:
-; VSX-NEXT: mtvsrd 0, 6
-; VSX-NEXT: mtvsrd 1, 5
+; VSX-NEXT: mtfprd 0, 6
+; VSX-NEXT: mtfprd 1, 5
; VSX-NEXT: xxmrghd 35, 1, 0
; VSX-NEXT: vadduqm 2, 2, 3
; VSX-NEXT: blr
define <1 x i128> @decrement_by_val(<1 x i128> %x, i128 %val) nounwind {
; VSX-LABEL: decrement_by_val:
; VSX: # %bb.0:
-; VSX-NEXT: mtvsrd 0, 6
-; VSX-NEXT: mtvsrd 1, 5
+; VSX-NEXT: mtfprd 0, 6
+; VSX-NEXT: mtfprd 1, 5
; VSX-NEXT: xxmrghd 35, 1, 0
; VSX-NEXT: vsubuqm 2, 2, 3
; VSX-NEXT: blr
define i32 @test2elt(i64 %a.coerce) local_unnamed_addr #0 {
; CHECK-P8-LABEL: test2elt:
; CHECK-P8: # %bb.0: # %entry
-; CHECK-P8-NEXT: mtvsrd f0, r3
+; CHECK-P8-NEXT: mtfprd f0, r3
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: xscvspdpn f0, vs0
; CHECK-P8-NEXT: xxsldwi vs1, v2, v2, 3
; CHECK-P8-NEXT: xscvspdpn f1, vs1
; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: xscvdpsxws f1, f1
-; CHECK-P8-NEXT: mfvsrwz r4, f0
-; CHECK-P8-NEXT: mfvsrwz r3, f1
-; CHECK-P8-NEXT: mtvsrd f1, r4
-; CHECK-P8-NEXT: mtvsrd f0, r3
+; CHECK-P8-NEXT: mffprwz r4, f0
+; CHECK-P8-NEXT: mffprwz r3, f1
+; CHECK-P8-NEXT: mtfprd f1, r4
+; CHECK-P8-NEXT: mtfprd f0, r3
; CHECK-P8-NEXT: xxswapd v3, vs1
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: vmrglh v2, v3, v2
; CHECK-P8-NEXT: xxswapd vs0, v2
-; CHECK-P8-NEXT: mfvsrwz r3, f0
+; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: blr
;
; CHECK-P9-LABEL: test2elt:
; CHECK-P9: # %bb.0: # %entry
-; CHECK-P9-NEXT: mtvsrd f0, r3
+; CHECK-P9-NEXT: mtfprd f0, r3
; CHECK-P9-NEXT: xxswapd v2, vs0
; CHECK-P9-NEXT: xscvspdpn f0, vs0
; CHECK-P9-NEXT: xxsldwi vs1, v2, v2, 3
; CHECK-P9-NEXT: xscvspdpn f1, vs1
; CHECK-P9-NEXT: xscvdpsxws f1, f1
; CHECK-P9-NEXT: xscvdpsxws f0, f0
-; CHECK-P9-NEXT: mfvsrwz r3, f1
-; CHECK-P9-NEXT: mtvsrd f1, r3
-; CHECK-P9-NEXT: mfvsrwz r3, f0
-; CHECK-P9-NEXT: mtvsrd f0, r3
+; CHECK-P9-NEXT: mffprwz r3, f1
+; CHECK-P9-NEXT: mtfprd f1, r3
+; CHECK-P9-NEXT: mffprwz r3, f0
+; CHECK-P9-NEXT: mtfprd f0, r3
; CHECK-P9-NEXT: xxswapd v2, vs1
; CHECK-P9-NEXT: xxswapd v3, vs0
; CHECK-P9-NEXT: vmrglh v2, v3, v2
;
; CHECK-BE-LABEL: test2elt:
; CHECK-BE: # %bb.0: # %entry
-; CHECK-BE-NEXT: mtvsrd f0, r3
+; CHECK-BE-NEXT: mtfprd f0, r3
; CHECK-BE-NEXT: xscvspdpn f1, vs0
; CHECK-BE-NEXT: xxsldwi vs0, vs0, vs0, 1
; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: xscvspdpn f0, vs0
; CHECK-BE-NEXT: xscvdpsxws f0, f0
-; CHECK-BE-NEXT: mfvsrwz r3, f1
+; CHECK-BE-NEXT: mffprwz r3, f1
; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: mtvsrd v2, r3
-; CHECK-BE-NEXT: mfvsrwz r3, f0
+; CHECK-BE-NEXT: mffprwz r3, f0
; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: li r3, 0
; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: xscvdpsxws f2, f2
; CHECK-P8-NEXT: xscvdpsxws f3, f3
-; CHECK-P8-NEXT: mfvsrwz r3, f1
-; CHECK-P8-NEXT: mtvsrd f1, r3
-; CHECK-P8-NEXT: mfvsrwz r3, f0
-; CHECK-P8-NEXT: mfvsrwz r4, f2
+; CHECK-P8-NEXT: mffprwz r3, f1
+; CHECK-P8-NEXT: mtfprd f1, r3
+; CHECK-P8-NEXT: mffprwz r3, f0
+; CHECK-P8-NEXT: mffprwz r4, f2
; CHECK-P8-NEXT: xxswapd v4, vs1
-; CHECK-P8-NEXT: mtvsrd f0, r3
-; CHECK-P8-NEXT: mfvsrwz r3, f3
-; CHECK-P8-NEXT: mtvsrd f2, r4
+; CHECK-P8-NEXT: mtfprd f0, r3
+; CHECK-P8-NEXT: mffprwz r3, f3
+; CHECK-P8-NEXT: mtfprd f2, r4
; CHECK-P8-NEXT: xxswapd v2, vs0
-; CHECK-P8-NEXT: mtvsrd f3, r3
+; CHECK-P8-NEXT: mtfprd f3, r3
; CHECK-P8-NEXT: xxswapd v3, vs2
; CHECK-P8-NEXT: xxswapd v5, vs3
; CHECK-P8-NEXT: vmrglh v2, v3, v2
; CHECK-P8-NEXT: vmrglh v3, v4, v5
; CHECK-P8-NEXT: vmrglw v2, v3, v2
; CHECK-P8-NEXT: xxswapd vs0, v2
-; CHECK-P8-NEXT: mfvsrd r3, f0
+; CHECK-P8-NEXT: mffprd r3, f0
; CHECK-P8-NEXT: blr
;
; CHECK-P9-LABEL: test4elt:
; CHECK-P9-NEXT: xxsldwi vs0, v2, v2, 3
; CHECK-P9-NEXT: xscvspdpn f0, vs0
; CHECK-P9-NEXT: xscvdpsxws f0, f0
-; CHECK-P9-NEXT: mfvsrwz r3, f0
-; CHECK-P9-NEXT: mtvsrd f0, r3
+; CHECK-P9-NEXT: mffprwz r3, f0
+; CHECK-P9-NEXT: mtfprd f0, r3
; CHECK-P9-NEXT: xxswapd v3, vs0
; CHECK-P9-NEXT: xxswapd vs0, v2
; CHECK-P9-NEXT: xscvspdpn f0, vs0
; CHECK-P9-NEXT: xscvdpsxws f0, f0
-; CHECK-P9-NEXT: mfvsrwz r3, f0
-; CHECK-P9-NEXT: mtvsrd f0, r3
+; CHECK-P9-NEXT: mffprwz r3, f0
+; CHECK-P9-NEXT: mtfprd f0, r3
; CHECK-P9-NEXT: xxswapd v4, vs0
; CHECK-P9-NEXT: xscvspdpn f0, v2
; CHECK-P9-NEXT: xscvdpsxws f0, f0
-; CHECK-P9-NEXT: mfvsrwz r3, f0
-; CHECK-P9-NEXT: mtvsrd f0, r3
+; CHECK-P9-NEXT: mffprwz r3, f0
+; CHECK-P9-NEXT: mtfprd f0, r3
; CHECK-P9-NEXT: vmrglh v3, v4, v3
; CHECK-P9-NEXT: xxswapd v4, vs0
; CHECK-P9-NEXT: xxsldwi vs0, v2, v2, 1
; CHECK-P9-NEXT: xscvspdpn f0, vs0
; CHECK-P9-NEXT: xscvdpsxws f0, f0
-; CHECK-P9-NEXT: mfvsrwz r3, f0
-; CHECK-P9-NEXT: mtvsrd f0, r3
+; CHECK-P9-NEXT: mffprwz r3, f0
+; CHECK-P9-NEXT: mtfprd f0, r3
; CHECK-P9-NEXT: xxswapd v2, vs0
; CHECK-P9-NEXT: vmrglh v2, v4, v2
; CHECK-P9-NEXT: vmrglw v2, v2, v3
; CHECK-BE-NEXT: xxsldwi vs0, v2, v2, 3
; CHECK-BE-NEXT: xscvspdpn f0, vs0
; CHECK-BE-NEXT: xscvdpsxws f0, f0
-; CHECK-BE-NEXT: mfvsrwz r3, f0
+; CHECK-BE-NEXT: mffprwz r3, f0
; CHECK-BE-NEXT: xxswapd vs0, v2
; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: xscvspdpn f0, vs0
; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: xscvdpsxws f0, f0
-; CHECK-BE-NEXT: mfvsrwz r3, f0
+; CHECK-BE-NEXT: mffprwz r3, f0
; CHECK-BE-NEXT: xscvspdpn f0, v2
; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: xscvdpsxws f0, f0
; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: vmrghh v3, v4, v3
-; CHECK-BE-NEXT: mfvsrwz r3, f0
+; CHECK-BE-NEXT: mffprwz r3, f0
; CHECK-BE-NEXT: xxsldwi vs0, v2, v2, 1
; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: xscvspdpn f0, vs0
; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: xscvdpsxws f0, f0
-; CHECK-BE-NEXT: mfvsrwz r3, f0
+; CHECK-BE-NEXT: mffprwz r3, f0
; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: mtvsrd v2, r3
; CHECK-BE-NEXT: vmrghh v2, v4, v2
; CHECK-P8-NEXT: xscvdpsxws f2, f2
; CHECK-P8-NEXT: xscvdpsxws f3, f3
; CHECK-P8-NEXT: xscvdpsxws f5, f5
-; CHECK-P8-NEXT: mfvsrwz r4, f4
-; CHECK-P8-NEXT: mfvsrwz r6, f1
-; CHECK-P8-NEXT: mfvsrwz r5, f0
-; CHECK-P8-NEXT: mtvsrd f1, r6
-; CHECK-P8-NEXT: mtvsrd f0, r5
+; CHECK-P8-NEXT: mffprwz r4, f4
+; CHECK-P8-NEXT: mffprwz r6, f1
+; CHECK-P8-NEXT: mffprwz r5, f0
+; CHECK-P8-NEXT: mtfprd f1, r6
+; CHECK-P8-NEXT: mtfprd f0, r5
; CHECK-P8-NEXT: xxswapd v4, vs1
; CHECK-P8-NEXT: xxsldwi vs1, v2, v2, 1
; CHECK-P8-NEXT: xxswapd v3, vs0
; CHECK-P8-NEXT: xscvspdpn f0, v2
-; CHECK-P8-NEXT: mtvsrd f4, r4
+; CHECK-P8-NEXT: mtfprd f4, r4
; CHECK-P8-NEXT: xscvspdpn f1, vs1
-; CHECK-P8-NEXT: mfvsrwz r4, f2
+; CHECK-P8-NEXT: mffprwz r4, f2
; CHECK-P8-NEXT: xxswapd v1, vs4
; CHECK-P8-NEXT: vmrglh v2, v4, v3
-; CHECK-P8-NEXT: mtvsrd f2, r4
+; CHECK-P8-NEXT: mtfprd f2, r4
; CHECK-P8-NEXT: xscvdpsxws f0, f0
-; CHECK-P8-NEXT: mfvsrwz r4, f5
+; CHECK-P8-NEXT: mffprwz r4, f5
; CHECK-P8-NEXT: xxswapd v5, vs2
; CHECK-P8-NEXT: xscvdpsxws f1, f1
-; CHECK-P8-NEXT: mfvsrwz r3, f0
-; CHECK-P8-NEXT: mtvsrd f0, r3
-; CHECK-P8-NEXT: mfvsrwz r3, f1
+; CHECK-P8-NEXT: mffprwz r3, f0
+; CHECK-P8-NEXT: mtfprd f0, r3
+; CHECK-P8-NEXT: mffprwz r3, f1
; CHECK-P8-NEXT: xxswapd v3, vs0
-; CHECK-P8-NEXT: mtvsrd f1, r3
-; CHECK-P8-NEXT: mfvsrwz r3, f3
-; CHECK-P8-NEXT: mtvsrd f3, r4
+; CHECK-P8-NEXT: mtfprd f1, r3
+; CHECK-P8-NEXT: mffprwz r3, f3
+; CHECK-P8-NEXT: mtfprd f3, r4
; CHECK-P8-NEXT: xxswapd v4, vs1
-; CHECK-P8-NEXT: mtvsrd f0, r3
+; CHECK-P8-NEXT: mtfprd f0, r3
; CHECK-P8-NEXT: xxswapd v6, vs3
; CHECK-P8-NEXT: xxswapd v0, vs0
; CHECK-P8-NEXT: vmrglh v3, v3, v4
; CHECK-P9-NEXT: xscvspdpn f2, vs2
; CHECK-P9-NEXT: xscvdpsxws f2, f2
; CHECK-P9-NEXT: lxv vs0, 16(r3)
-; CHECK-P9-NEXT: mfvsrwz r3, f2
-; CHECK-P9-NEXT: mtvsrd f2, r3
+; CHECK-P9-NEXT: mffprwz r3, f2
+; CHECK-P9-NEXT: mtfprd f2, r3
; CHECK-P9-NEXT: xxswapd v2, vs2
; CHECK-P9-NEXT: xxswapd vs2, vs1
; CHECK-P9-NEXT: xscvspdpn f2, vs2
; CHECK-P9-NEXT: xscvdpsxws f2, f2
-; CHECK-P9-NEXT: mfvsrwz r3, f2
-; CHECK-P9-NEXT: mtvsrd f2, r3
+; CHECK-P9-NEXT: mffprwz r3, f2
+; CHECK-P9-NEXT: mtfprd f2, r3
; CHECK-P9-NEXT: xxswapd v3, vs2
; CHECK-P9-NEXT: xscvspdpn f2, vs1
; CHECK-P9-NEXT: xxsldwi vs1, vs1, vs1, 1
; CHECK-P9-NEXT: xscvspdpn f1, vs1
; CHECK-P9-NEXT: xscvdpsxws f2, f2
; CHECK-P9-NEXT: xscvdpsxws f1, f1
-; CHECK-P9-NEXT: mfvsrwz r3, f2
-; CHECK-P9-NEXT: mtvsrd f2, r3
-; CHECK-P9-NEXT: mfvsrwz r3, f1
-; CHECK-P9-NEXT: mtvsrd f1, r3
+; CHECK-P9-NEXT: mffprwz r3, f2
+; CHECK-P9-NEXT: mtfprd f2, r3
+; CHECK-P9-NEXT: mffprwz r3, f1
+; CHECK-P9-NEXT: mtfprd f1, r3
; CHECK-P9-NEXT: xxswapd v4, vs1
; CHECK-P9-NEXT: xxsldwi vs1, vs0, vs0, 3
; CHECK-P9-NEXT: xscvspdpn f1, vs1
; CHECK-P9-NEXT: xxswapd v3, vs2
; CHECK-P9-NEXT: vmrglh v3, v3, v4
; CHECK-P9-NEXT: vmrglw v2, v3, v2
-; CHECK-P9-NEXT: mfvsrwz r3, f1
-; CHECK-P9-NEXT: mtvsrd f1, r3
+; CHECK-P9-NEXT: mffprwz r3, f1
+; CHECK-P9-NEXT: mtfprd f1, r3
; CHECK-P9-NEXT: xxswapd v3, vs1
; CHECK-P9-NEXT: xxswapd vs1, vs0
; CHECK-P9-NEXT: xscvspdpn f1, vs1
; CHECK-P9-NEXT: xscvdpsxws f1, f1
-; CHECK-P9-NEXT: mfvsrwz r3, f1
-; CHECK-P9-NEXT: mtvsrd f1, r3
+; CHECK-P9-NEXT: mffprwz r3, f1
+; CHECK-P9-NEXT: mtfprd f1, r3
; CHECK-P9-NEXT: xxswapd v4, vs1
; CHECK-P9-NEXT: xscvspdpn f1, vs0
; CHECK-P9-NEXT: xxsldwi vs0, vs0, vs0, 1
; CHECK-P9-NEXT: xscvspdpn f0, vs0
; CHECK-P9-NEXT: xscvdpsxws f1, f1
; CHECK-P9-NEXT: xscvdpsxws f0, f0
-; CHECK-P9-NEXT: mfvsrwz r3, f1
-; CHECK-P9-NEXT: mtvsrd f1, r3
-; CHECK-P9-NEXT: mfvsrwz r3, f0
-; CHECK-P9-NEXT: mtvsrd f0, r3
+; CHECK-P9-NEXT: mffprwz r3, f1
+; CHECK-P9-NEXT: mtfprd f1, r3
+; CHECK-P9-NEXT: mffprwz r3, f0
+; CHECK-P9-NEXT: mtfprd f0, r3
; CHECK-P9-NEXT: vmrglh v3, v4, v3
; CHECK-P9-NEXT: xxswapd v4, vs1
; CHECK-P9-NEXT: xxswapd v5, vs0
; CHECK-BE-NEXT: xscvspdpn f2, vs2
; CHECK-BE-NEXT: xscvdpsxws f2, f2
; CHECK-BE-NEXT: lxv vs0, 0(r3)
-; CHECK-BE-NEXT: mfvsrwz r3, f2
+; CHECK-BE-NEXT: mffprwz r3, f2
; CHECK-BE-NEXT: xxswapd vs2, vs1
; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: xscvspdpn f2, vs2
; CHECK-BE-NEXT: mtvsrd v2, r3
; CHECK-BE-NEXT: xscvdpsxws f2, f2
-; CHECK-BE-NEXT: mfvsrwz r3, f2
+; CHECK-BE-NEXT: mffprwz r3, f2
; CHECK-BE-NEXT: xscvspdpn f2, vs1
; CHECK-BE-NEXT: xxsldwi vs1, vs1, vs1, 1
; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: vmrghh v2, v3, v2
-; CHECK-BE-NEXT: mfvsrwz r3, f2
+; CHECK-BE-NEXT: mffprwz r3, f2
; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: mtvsrd v3, r3
-; CHECK-BE-NEXT: mfvsrwz r3, f1
+; CHECK-BE-NEXT: mffprwz r3, f1
; CHECK-BE-NEXT: xxsldwi vs1, vs0, vs0, 3
; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: xscvspdpn f1, vs1
; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: xscvdpsxws f1, f1
-; CHECK-BE-NEXT: mfvsrwz r3, f1
+; CHECK-BE-NEXT: mffprwz r3, f1
; CHECK-BE-NEXT: xxswapd vs1, vs0
; CHECK-BE-NEXT: xscvspdpn f1, vs1
; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: vmrghw v2, v3, v2
; CHECK-BE-NEXT: mtvsrd v3, r3
-; CHECK-BE-NEXT: mfvsrwz r3, f1
+; CHECK-BE-NEXT: mffprwz r3, f1
; CHECK-BE-NEXT: xscvspdpn f1, vs0
; CHECK-BE-NEXT: xxsldwi vs0, vs0, vs0, 1
; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: xscvdpsxws f0, f0
; CHECK-BE-NEXT: vmrghh v3, v4, v3
-; CHECK-BE-NEXT: mfvsrwz r3, f1
+; CHECK-BE-NEXT: mffprwz r3, f1
; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: mtvsrd v4, r3
-; CHECK-BE-NEXT: mfvsrwz r3, f0
+; CHECK-BE-NEXT: mffprwz r3, f0
; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: mtvsrd v5, r3
; CHECK-BE-NEXT: vmrghh v4, v4, v5
; CHECK-P8-NEXT: xscvdpsxws f6, f6
; CHECK-P8-NEXT: xscvspdpn f12, vs12
; CHECK-P8-NEXT: xscvdpsxws f5, f5
-; CHECK-P8-NEXT: mfvsrwz r4, f0
+; CHECK-P8-NEXT: mffprwz r4, f0
; CHECK-P8-NEXT: xscvspdpn f11, vs11
; CHECK-P8-NEXT: xscvdpsxws f3, f3
; CHECK-P8-NEXT: xscvspdpn v2, v2
; CHECK-P8-NEXT: xscvdpsxws f8, f8
-; CHECK-P8-NEXT: mtvsrd f0, r4
-; CHECK-P8-NEXT: mfvsrwz r4, f4
+; CHECK-P8-NEXT: mtfprd f0, r4
+; CHECK-P8-NEXT: mffprwz r4, f4
; CHECK-P8-NEXT: xscvdpsxws f7, f7
-; CHECK-P8-NEXT: mfvsrwz r6, f2
+; CHECK-P8-NEXT: mffprwz r6, f2
; CHECK-P8-NEXT: xscvspdpn f13, vs13
; CHECK-P8-NEXT: xscvspdpn v3, v3
; CHECK-P8-NEXT: xscvdpsxws f10, f10
-; CHECK-P8-NEXT: mtvsrd f4, r4
-; CHECK-P8-NEXT: mfvsrwz r4, f1
+; CHECK-P8-NEXT: mtfprd f4, r4
+; CHECK-P8-NEXT: mffprwz r4, f1
; CHECK-P8-NEXT: xscvdpsxws f9, f9
-; CHECK-P8-NEXT: mtvsrd f2, r6
-; CHECK-P8-NEXT: mfvsrwz r6, f6
+; CHECK-P8-NEXT: mtfprd f2, r6
+; CHECK-P8-NEXT: mffprwz r6, f6
; CHECK-P8-NEXT: xscvdpsxws f12, f12
-; CHECK-P8-NEXT: mtvsrd f1, r4
-; CHECK-P8-NEXT: mfvsrwz r4, f5
+; CHECK-P8-NEXT: mtfprd f1, r4
+; CHECK-P8-NEXT: mffprwz r4, f5
; CHECK-P8-NEXT: xscvdpsxws f11, f11
; CHECK-P8-NEXT: xxswapd v4, vs1
-; CHECK-P8-NEXT: mtvsrd f6, r6
-; CHECK-P8-NEXT: mfvsrwz r6, f3
+; CHECK-P8-NEXT: mtfprd f6, r6
+; CHECK-P8-NEXT: mffprwz r6, f3
; CHECK-P8-NEXT: xscvdpsxws v2, v2
; CHECK-P8-NEXT: xxswapd v9, vs6
-; CHECK-P8-NEXT: mtvsrd f5, r4
-; CHECK-P8-NEXT: mfvsrwz r4, f8
-; CHECK-P8-NEXT: mtvsrd f3, r6
+; CHECK-P8-NEXT: mtfprd f5, r4
+; CHECK-P8-NEXT: mffprwz r4, f8
+; CHECK-P8-NEXT: mtfprd f3, r6
; CHECK-P8-NEXT: xxswapd v0, vs5
-; CHECK-P8-NEXT: mfvsrwz r6, f7
+; CHECK-P8-NEXT: mffprwz r6, f7
; CHECK-P8-NEXT: xscvdpsxws f13, f13
; CHECK-P8-NEXT: xxswapd v5, vs3
; CHECK-P8-NEXT: xscvdpsxws v3, v3
-; CHECK-P8-NEXT: mtvsrd f8, r4
-; CHECK-P8-NEXT: mfvsrwz r4, f10
-; CHECK-P8-NEXT: mtvsrd f7, r6
-; CHECK-P8-NEXT: mfvsrwz r6, f9
-; CHECK-P8-NEXT: mtvsrd f10, r4
-; CHECK-P8-NEXT: mfvsrwz r4, f12
-; CHECK-P8-NEXT: mtvsrd f9, r6
+; CHECK-P8-NEXT: mtfprd f8, r4
+; CHECK-P8-NEXT: mffprwz r4, f10
+; CHECK-P8-NEXT: mtfprd f7, r6
+; CHECK-P8-NEXT: mffprwz r6, f9
+; CHECK-P8-NEXT: mtfprd f10, r4
+; CHECK-P8-NEXT: mffprwz r4, f12
+; CHECK-P8-NEXT: mtfprd f9, r6
; CHECK-P8-NEXT: xxswapd v6, vs10
-; CHECK-P8-NEXT: mfvsrwz r6, f11
-; CHECK-P8-NEXT: mtvsrd f12, r4
+; CHECK-P8-NEXT: mffprwz r6, f11
+; CHECK-P8-NEXT: mtfprd f12, r4
; CHECK-P8-NEXT: xxswapd v1, vs9
; CHECK-P8-NEXT: mfvsrwz r4, v2
; CHECK-P8-NEXT: xxswapd v2, vs0
-; CHECK-P8-NEXT: mtvsrd f11, r6
-; CHECK-P8-NEXT: mfvsrwz r6, f13
-; CHECK-P8-NEXT: mtvsrd f0, r4
+; CHECK-P8-NEXT: mtfprd f11, r6
+; CHECK-P8-NEXT: mffprwz r6, f13
+; CHECK-P8-NEXT: mtfprd f0, r4
; CHECK-P8-NEXT: xxswapd v7, vs11
; CHECK-P8-NEXT: mfvsrwz r4, v3
; CHECK-P8-NEXT: vmrglh v3, v5, v4
; CHECK-P8-NEXT: vmrglh v2, v2, v0
; CHECK-P8-NEXT: xxswapd v5, vs8
; CHECK-P8-NEXT: xxswapd v0, vs2
-; CHECK-P8-NEXT: mtvsrd f13, r6
-; CHECK-P8-NEXT: mtvsrd f1, r4
+; CHECK-P8-NEXT: mtfprd f13, r6
+; CHECK-P8-NEXT: mtfprd f1, r4
; CHECK-P8-NEXT: xxswapd v8, vs0
; CHECK-P8-NEXT: vmrglh v4, v5, v4
; CHECK-P8-NEXT: vmrglh v5, v0, v1
; CHECK-P9-NEXT: xscvspdpn f1, vs1
; CHECK-P9-NEXT: xscvdpsxws f4, f4
; CHECK-P9-NEXT: xscvdpsxws f6, f6
-; CHECK-P9-NEXT: mfvsrwz r5, f5
+; CHECK-P9-NEXT: mffprwz r5, f5
; CHECK-P9-NEXT: xscvdpsxws f1, f1
; CHECK-P9-NEXT: xscvdpsxws f7, f7
; CHECK-P9-NEXT: xscvdpsxws f3, f3
-; CHECK-P9-NEXT: mtvsrd f5, r5
-; CHECK-P9-NEXT: mfvsrwz r5, f8
-; CHECK-P9-NEXT: mtvsrd f8, r5
-; CHECK-P9-NEXT: mfvsrwz r5, f2
+; CHECK-P9-NEXT: mtfprd f5, r5
+; CHECK-P9-NEXT: mffprwz r5, f8
+; CHECK-P9-NEXT: mtfprd f8, r5
+; CHECK-P9-NEXT: mffprwz r5, f2
; CHECK-P9-NEXT: lxv vs0, 32(r4)
; CHECK-P9-NEXT: xxsldwi vs9, vs0, vs0, 3
; CHECK-P9-NEXT: xxswapd vs10, vs0
; CHECK-P9-NEXT: xscvspdpn f10, vs10
; CHECK-P9-NEXT: xscvdpsxws f9, f9
; CHECK-P9-NEXT: xscvdpsxws f10, f10
-; CHECK-P9-NEXT: mtvsrd f2, r5
-; CHECK-P9-NEXT: mfvsrwz r5, f4
-; CHECK-P9-NEXT: mtvsrd f4, r5
-; CHECK-P9-NEXT: mfvsrwz r5, f1
-; CHECK-P9-NEXT: mtvsrd f1, r5
-; CHECK-P9-NEXT: mfvsrwz r5, f6
+; CHECK-P9-NEXT: mtfprd f2, r5
+; CHECK-P9-NEXT: mffprwz r5, f4
+; CHECK-P9-NEXT: mtfprd f4, r5
+; CHECK-P9-NEXT: mffprwz r5, f1
+; CHECK-P9-NEXT: mtfprd f1, r5
+; CHECK-P9-NEXT: mffprwz r5, f6
; CHECK-P9-NEXT: xxswapd v2, vs2
; CHECK-P9-NEXT: xxswapd v3, vs4
; CHECK-P9-NEXT: xscvspdpn f2, vs0
; CHECK-P9-NEXT: xxsldwi vs0, vs0, vs0, 1
; CHECK-P9-NEXT: xscvspdpn f0, vs0
; CHECK-P9-NEXT: xscvdpsxws f2, f2
-; CHECK-P9-NEXT: mtvsrd f6, r5
-; CHECK-P9-NEXT: mfvsrwz r5, f7
+; CHECK-P9-NEXT: mtfprd f6, r5
+; CHECK-P9-NEXT: mffprwz r5, f7
; CHECK-P9-NEXT: xxswapd v4, vs1
; CHECK-P9-NEXT: lxv vs1, 48(r4)
; CHECK-P9-NEXT: vmrglh v2, v3, v2
; CHECK-P9-NEXT: xxswapd v3, vs5
-; CHECK-P9-NEXT: mtvsrd f7, r5
-; CHECK-P9-NEXT: mfvsrwz r5, f3
+; CHECK-P9-NEXT: mtfprd f7, r5
+; CHECK-P9-NEXT: mffprwz r5, f3
; CHECK-P9-NEXT: vmrglh v3, v3, v4
; CHECK-P9-NEXT: xxswapd v4, vs6
; CHECK-P9-NEXT: xxswapd v5, vs7
-; CHECK-P9-NEXT: mtvsrd f3, r5
+; CHECK-P9-NEXT: mtfprd f3, r5
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: xxswapd v0, vs3
; CHECK-P9-NEXT: vmrglh v4, v5, v4
; CHECK-P9-NEXT: xxswapd v5, vs8
; CHECK-P9-NEXT: vmrglh v5, v5, v0
-; CHECK-P9-NEXT: mfvsrwz r4, f2
-; CHECK-P9-NEXT: mtvsrd f2, r4
-; CHECK-P9-NEXT: mfvsrwz r4, f0
+; CHECK-P9-NEXT: mffprwz r4, f2
+; CHECK-P9-NEXT: mtfprd f2, r4
+; CHECK-P9-NEXT: mffprwz r4, f0
; CHECK-P9-NEXT: vmrglw v2, v3, v2
-; CHECK-P9-NEXT: mtvsrd f0, r4
+; CHECK-P9-NEXT: mtfprd f0, r4
; CHECK-P9-NEXT: vmrglw v3, v5, v4
; CHECK-P9-NEXT: xxswapd v4, vs2
; CHECK-P9-NEXT: xxmrgld vs2, v3, v2
; CHECK-P9-NEXT: xxsldwi vs0, vs1, vs1, 3
; CHECK-P9-NEXT: xscvspdpn f0, vs0
; CHECK-P9-NEXT: xscvdpsxws f0, f0
-; CHECK-P9-NEXT: mfvsrwz r4, f0
-; CHECK-P9-NEXT: mtvsrd f0, r4
+; CHECK-P9-NEXT: mffprwz r4, f0
+; CHECK-P9-NEXT: mtfprd f0, r4
; CHECK-P9-NEXT: xxswapd v3, vs0
; CHECK-P9-NEXT: xxswapd vs0, vs1
; CHECK-P9-NEXT: xscvspdpn f0, vs0
; CHECK-P9-NEXT: xscvdpsxws f0, f0
-; CHECK-P9-NEXT: mfvsrwz r4, f0
-; CHECK-P9-NEXT: mtvsrd f0, r4
+; CHECK-P9-NEXT: mffprwz r4, f0
+; CHECK-P9-NEXT: mtfprd f0, r4
; CHECK-P9-NEXT: vmrglh v2, v4, v2
; CHECK-P9-NEXT: xxswapd v4, vs0
; CHECK-P9-NEXT: xscvspdpn f0, vs1
; CHECK-P9-NEXT: xscvdpsxws f0, f0
-; CHECK-P9-NEXT: mfvsrwz r4, f0
-; CHECK-P9-NEXT: mtvsrd f0, r4
+; CHECK-P9-NEXT: mffprwz r4, f0
+; CHECK-P9-NEXT: mtfprd f0, r4
; CHECK-P9-NEXT: vmrglh v3, v4, v3
; CHECK-P9-NEXT: xxswapd v4, vs0
; CHECK-P9-NEXT: xxsldwi vs0, vs1, vs1, 1
; CHECK-P9-NEXT: xscvspdpn f0, vs0
; CHECK-P9-NEXT: xscvdpsxws f0, f0
-; CHECK-P9-NEXT: mfvsrwz r5, f9
-; CHECK-P9-NEXT: mtvsrd f9, r5
-; CHECK-P9-NEXT: mfvsrwz r5, f10
-; CHECK-P9-NEXT: mtvsrd f10, r5
+; CHECK-P9-NEXT: mffprwz r5, f9
+; CHECK-P9-NEXT: mtfprd f9, r5
+; CHECK-P9-NEXT: mffprwz r5, f10
+; CHECK-P9-NEXT: mtfprd f10, r5
; CHECK-P9-NEXT: xxswapd v0, vs9
; CHECK-P9-NEXT: xxswapd v1, vs10
; CHECK-P9-NEXT: vmrglh v0, v1, v0
; CHECK-P9-NEXT: vmrglw v2, v2, v0
; CHECK-P9-NEXT: stxv vs2, 0(r3)
-; CHECK-P9-NEXT: mfvsrwz r4, f0
-; CHECK-P9-NEXT: mtvsrd f0, r4
+; CHECK-P9-NEXT: mffprwz r4, f0
+; CHECK-P9-NEXT: mtfprd f0, r4
; CHECK-P9-NEXT: xxswapd v5, vs0
; CHECK-P9-NEXT: vmrglh v4, v4, v5
; CHECK-P9-NEXT: vmrglw v3, v4, v3
; CHECK-BE-NEXT: xscvspdpn f3, vs3
; CHECK-BE-NEXT: xscvdpsxws f2, f2
; CHECK-BE-NEXT: xscvdpsxws f3, f3
-; CHECK-BE-NEXT: mfvsrwz r5, f2
+; CHECK-BE-NEXT: mffprwz r5, f2
; CHECK-BE-NEXT: xscvspdpn f4, vs1
; CHECK-BE-NEXT: xxsldwi vs1, vs1, vs1, 1
; CHECK-BE-NEXT: xscvspdpn f1, vs1
; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: mtvsrd v2, r5
-; CHECK-BE-NEXT: mfvsrwz r5, f3
+; CHECK-BE-NEXT: mffprwz r5, f3
; CHECK-BE-NEXT: xscvdpsxws f3, f4
; CHECK-BE-NEXT: lxv vs0, 0(r4)
; CHECK-BE-NEXT: xxsldwi vs2, vs0, vs0, 3
; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: mtvsrd v3, r5
; CHECK-BE-NEXT: vmrghh v2, v3, v2
-; CHECK-BE-NEXT: mfvsrwz r5, f3
+; CHECK-BE-NEXT: mffprwz r5, f3
; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: mtvsrd v3, r5
-; CHECK-BE-NEXT: mfvsrwz r5, f1
+; CHECK-BE-NEXT: mffprwz r5, f1
; CHECK-BE-NEXT: xxswapd vs1, vs0
; CHECK-BE-NEXT: xscvdpsxws f2, f2
; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: xscvspdpn f1, vs1
; CHECK-BE-NEXT: mtvsrd v4, r5
-; CHECK-BE-NEXT: mfvsrwz r5, f2
+; CHECK-BE-NEXT: mffprwz r5, f2
; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: vmrghh v3, v3, v4
; CHECK-BE-NEXT: mtvsrd v4, r5
; CHECK-BE-NEXT: vmrghw v2, v3, v2
-; CHECK-BE-NEXT: mfvsrwz r5, f1
+; CHECK-BE-NEXT: mffprwz r5, f1
; CHECK-BE-NEXT: xscvspdpn f1, vs0
; CHECK-BE-NEXT: xxsldwi vs0, vs0, vs0, 1
; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: mtvsrd v5, r5
; CHECK-BE-NEXT: xscvdpsxws f0, f0
; CHECK-BE-NEXT: vmrghh v4, v5, v4
-; CHECK-BE-NEXT: mfvsrwz r5, f1
+; CHECK-BE-NEXT: mffprwz r5, f1
; CHECK-BE-NEXT: lxv vs1, 48(r4)
; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: mtvsrd v5, r5
-; CHECK-BE-NEXT: mfvsrwz r5, f0
+; CHECK-BE-NEXT: mffprwz r5, f0
; CHECK-BE-NEXT: lxv vs0, 32(r4)
; CHECK-BE-NEXT: xscvspdpn f5, vs1
; CHECK-BE-NEXT: xxsldwi vs2, vs1, vs1, 3
; CHECK-BE-NEXT: xscvdpsxws f2, f2
; CHECK-BE-NEXT: vmrghw v3, v5, v4
; CHECK-BE-NEXT: xscvdpsxws f3, f3
-; CHECK-BE-NEXT: mfvsrwz r4, f5
+; CHECK-BE-NEXT: mffprwz r4, f5
; CHECK-BE-NEXT: xxmrghd vs4, v3, v2
; CHECK-BE-NEXT: sldi r4, r4, 48
; CHECK-BE-NEXT: mtvsrd v2, r4
-; CHECK-BE-NEXT: mfvsrwz r4, f2
+; CHECK-BE-NEXT: mffprwz r4, f2
; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: stxv vs4, 0(r3)
; CHECK-BE-NEXT: sldi r4, r4, 48
; CHECK-BE-NEXT: mtvsrd v3, r4
-; CHECK-BE-NEXT: mfvsrwz r4, f3
+; CHECK-BE-NEXT: mffprwz r4, f3
; CHECK-BE-NEXT: sldi r4, r4, 48
; CHECK-BE-NEXT: mtvsrd v4, r4
-; CHECK-BE-NEXT: mfvsrwz r4, f1
+; CHECK-BE-NEXT: mffprwz r4, f1
; CHECK-BE-NEXT: xxsldwi vs1, vs0, vs0, 3
; CHECK-BE-NEXT: sldi r4, r4, 48
; CHECK-BE-NEXT: xscvspdpn f1, vs1
; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: vmrghh v3, v4, v3
; CHECK-BE-NEXT: mtvsrd v4, r4
-; CHECK-BE-NEXT: mfvsrwz r4, f1
+; CHECK-BE-NEXT: mffprwz r4, f1
; CHECK-BE-NEXT: xxswapd vs1, vs0
; CHECK-BE-NEXT: xscvspdpn f1, vs1
; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: sldi r4, r4, 48
; CHECK-BE-NEXT: vmrghw v2, v2, v3
; CHECK-BE-NEXT: mtvsrd v3, r4
-; CHECK-BE-NEXT: mfvsrwz r4, f1
+; CHECK-BE-NEXT: mffprwz r4, f1
; CHECK-BE-NEXT: xscvspdpn f1, vs0
; CHECK-BE-NEXT: xxsldwi vs0, vs0, vs0, 1
; CHECK-BE-NEXT: sldi r4, r4, 48
; CHECK-BE-NEXT: mtvsrd v4, r4
; CHECK-BE-NEXT: xscvdpsxws f0, f0
; CHECK-BE-NEXT: vmrghh v3, v4, v3
-; CHECK-BE-NEXT: mfvsrwz r4, f1
+; CHECK-BE-NEXT: mffprwz r4, f1
; CHECK-BE-NEXT: sldi r4, r4, 48
; CHECK-BE-NEXT: mtvsrd v4, r4
-; CHECK-BE-NEXT: mfvsrwz r4, f0
+; CHECK-BE-NEXT: mffprwz r4, f0
; CHECK-BE-NEXT: sldi r4, r4, 48
; CHECK-BE-NEXT: mtvsrd v5, r4
; CHECK-BE-NEXT: vmrghh v4, v4, v5
define i32 @test2elt_signed(i64 %a.coerce) local_unnamed_addr #0 {
; CHECK-P8-LABEL: test2elt_signed:
; CHECK-P8: # %bb.0: # %entry
-; CHECK-P8-NEXT: mtvsrd f0, r3
+; CHECK-P8-NEXT: mtfprd f0, r3
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: xscvspdpn f0, vs0
; CHECK-P8-NEXT: xxsldwi vs1, v2, v2, 3
; CHECK-P8-NEXT: xscvspdpn f1, vs1
; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: xscvdpsxws f1, f1
-; CHECK-P8-NEXT: mfvsrwz r4, f0
-; CHECK-P8-NEXT: mfvsrwz r3, f1
-; CHECK-P8-NEXT: mtvsrd f1, r4
-; CHECK-P8-NEXT: mtvsrd f0, r3
+; CHECK-P8-NEXT: mffprwz r4, f0
+; CHECK-P8-NEXT: mffprwz r3, f1
+; CHECK-P8-NEXT: mtfprd f1, r4
+; CHECK-P8-NEXT: mtfprd f0, r3
; CHECK-P8-NEXT: xxswapd v3, vs1
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: vmrglh v2, v3, v2
; CHECK-P8-NEXT: xxswapd vs0, v2
-; CHECK-P8-NEXT: mfvsrwz r3, f0
+; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: blr
;
; CHECK-P9-LABEL: test2elt_signed:
; CHECK-P9: # %bb.0: # %entry
-; CHECK-P9-NEXT: mtvsrd f0, r3
+; CHECK-P9-NEXT: mtfprd f0, r3
; CHECK-P9-NEXT: xxswapd v2, vs0
; CHECK-P9-NEXT: xscvspdpn f0, vs0
; CHECK-P9-NEXT: xxsldwi vs1, v2, v2, 3
; CHECK-P9-NEXT: xscvspdpn f1, vs1
; CHECK-P9-NEXT: xscvdpsxws f1, f1
; CHECK-P9-NEXT: xscvdpsxws f0, f0
-; CHECK-P9-NEXT: mfvsrwz r3, f1
-; CHECK-P9-NEXT: mtvsrd f1, r3
-; CHECK-P9-NEXT: mfvsrwz r3, f0
-; CHECK-P9-NEXT: mtvsrd f0, r3
+; CHECK-P9-NEXT: mffprwz r3, f1
+; CHECK-P9-NEXT: mtfprd f1, r3
+; CHECK-P9-NEXT: mffprwz r3, f0
+; CHECK-P9-NEXT: mtfprd f0, r3
; CHECK-P9-NEXT: xxswapd v2, vs1
; CHECK-P9-NEXT: xxswapd v3, vs0
; CHECK-P9-NEXT: vmrglh v2, v3, v2
;
; CHECK-BE-LABEL: test2elt_signed:
; CHECK-BE: # %bb.0: # %entry
-; CHECK-BE-NEXT: mtvsrd f0, r3
+; CHECK-BE-NEXT: mtfprd f0, r3
; CHECK-BE-NEXT: xscvspdpn f1, vs0
; CHECK-BE-NEXT: xxsldwi vs0, vs0, vs0, 1
; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: xscvspdpn f0, vs0
; CHECK-BE-NEXT: xscvdpsxws f0, f0
-; CHECK-BE-NEXT: mfvsrwz r3, f1
+; CHECK-BE-NEXT: mffprwz r3, f1
; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: mtvsrd v2, r3
-; CHECK-BE-NEXT: mfvsrwz r3, f0
+; CHECK-BE-NEXT: mffprwz r3, f0
; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: li r3, 0
; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: xscvdpsxws f2, f2
; CHECK-P8-NEXT: xscvdpsxws f3, f3
-; CHECK-P8-NEXT: mfvsrwz r3, f1
-; CHECK-P8-NEXT: mtvsrd f1, r3
-; CHECK-P8-NEXT: mfvsrwz r3, f0
-; CHECK-P8-NEXT: mfvsrwz r4, f2
+; CHECK-P8-NEXT: mffprwz r3, f1
+; CHECK-P8-NEXT: mtfprd f1, r3
+; CHECK-P8-NEXT: mffprwz r3, f0
+; CHECK-P8-NEXT: mffprwz r4, f2
; CHECK-P8-NEXT: xxswapd v4, vs1
-; CHECK-P8-NEXT: mtvsrd f0, r3
-; CHECK-P8-NEXT: mfvsrwz r3, f3
-; CHECK-P8-NEXT: mtvsrd f2, r4
+; CHECK-P8-NEXT: mtfprd f0, r3
+; CHECK-P8-NEXT: mffprwz r3, f3
+; CHECK-P8-NEXT: mtfprd f2, r4
; CHECK-P8-NEXT: xxswapd v2, vs0
-; CHECK-P8-NEXT: mtvsrd f3, r3
+; CHECK-P8-NEXT: mtfprd f3, r3
; CHECK-P8-NEXT: xxswapd v3, vs2
; CHECK-P8-NEXT: xxswapd v5, vs3
; CHECK-P8-NEXT: vmrglh v2, v3, v2
; CHECK-P8-NEXT: vmrglh v3, v4, v5
; CHECK-P8-NEXT: vmrglw v2, v3, v2
; CHECK-P8-NEXT: xxswapd vs0, v2
-; CHECK-P8-NEXT: mfvsrd r3, f0
+; CHECK-P8-NEXT: mffprd r3, f0
; CHECK-P8-NEXT: blr
;
; CHECK-P9-LABEL: test4elt_signed:
; CHECK-P9-NEXT: xxsldwi vs0, v2, v2, 3
; CHECK-P9-NEXT: xscvspdpn f0, vs0
; CHECK-P9-NEXT: xscvdpsxws f0, f0
-; CHECK-P9-NEXT: mfvsrwz r3, f0
-; CHECK-P9-NEXT: mtvsrd f0, r3
+; CHECK-P9-NEXT: mffprwz r3, f0
+; CHECK-P9-NEXT: mtfprd f0, r3
; CHECK-P9-NEXT: xxswapd v3, vs0
; CHECK-P9-NEXT: xxswapd vs0, v2
; CHECK-P9-NEXT: xscvspdpn f0, vs0
; CHECK-P9-NEXT: xscvdpsxws f0, f0
-; CHECK-P9-NEXT: mfvsrwz r3, f0
-; CHECK-P9-NEXT: mtvsrd f0, r3
+; CHECK-P9-NEXT: mffprwz r3, f0
+; CHECK-P9-NEXT: mtfprd f0, r3
; CHECK-P9-NEXT: xxswapd v4, vs0
; CHECK-P9-NEXT: xscvspdpn f0, v2
; CHECK-P9-NEXT: xscvdpsxws f0, f0
-; CHECK-P9-NEXT: mfvsrwz r3, f0
-; CHECK-P9-NEXT: mtvsrd f0, r3
+; CHECK-P9-NEXT: mffprwz r3, f0
+; CHECK-P9-NEXT: mtfprd f0, r3
; CHECK-P9-NEXT: vmrglh v3, v4, v3
; CHECK-P9-NEXT: xxswapd v4, vs0
; CHECK-P9-NEXT: xxsldwi vs0, v2, v2, 1
; CHECK-P9-NEXT: xscvspdpn f0, vs0
; CHECK-P9-NEXT: xscvdpsxws f0, f0
-; CHECK-P9-NEXT: mfvsrwz r3, f0
-; CHECK-P9-NEXT: mtvsrd f0, r3
+; CHECK-P9-NEXT: mffprwz r3, f0
+; CHECK-P9-NEXT: mtfprd f0, r3
; CHECK-P9-NEXT: xxswapd v2, vs0
; CHECK-P9-NEXT: vmrglh v2, v4, v2
; CHECK-P9-NEXT: vmrglw v2, v2, v3
; CHECK-BE-NEXT: xxsldwi vs0, v2, v2, 3
; CHECK-BE-NEXT: xscvspdpn f0, vs0
; CHECK-BE-NEXT: xscvdpsxws f0, f0
-; CHECK-BE-NEXT: mfvsrwz r3, f0
+; CHECK-BE-NEXT: mffprwz r3, f0
; CHECK-BE-NEXT: xxswapd vs0, v2
; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: xscvspdpn f0, vs0
; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: xscvdpsxws f0, f0
-; CHECK-BE-NEXT: mfvsrwz r3, f0
+; CHECK-BE-NEXT: mffprwz r3, f0
; CHECK-BE-NEXT: xscvspdpn f0, v2
; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: xscvdpsxws f0, f0
; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: vmrghh v3, v4, v3
-; CHECK-BE-NEXT: mfvsrwz r3, f0
+; CHECK-BE-NEXT: mffprwz r3, f0
; CHECK-BE-NEXT: xxsldwi vs0, v2, v2, 1
; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: xscvspdpn f0, vs0
; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: xscvdpsxws f0, f0
-; CHECK-BE-NEXT: mfvsrwz r3, f0
+; CHECK-BE-NEXT: mffprwz r3, f0
; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: mtvsrd v2, r3
; CHECK-BE-NEXT: vmrghh v2, v4, v2
; CHECK-P8-NEXT: xscvdpsxws f2, f2
; CHECK-P8-NEXT: xscvdpsxws f3, f3
; CHECK-P8-NEXT: xscvdpsxws f5, f5
-; CHECK-P8-NEXT: mfvsrwz r4, f4
-; CHECK-P8-NEXT: mfvsrwz r6, f1
-; CHECK-P8-NEXT: mfvsrwz r5, f0
-; CHECK-P8-NEXT: mtvsrd f1, r6
-; CHECK-P8-NEXT: mtvsrd f0, r5
+; CHECK-P8-NEXT: mffprwz r4, f4
+; CHECK-P8-NEXT: mffprwz r6, f1
+; CHECK-P8-NEXT: mffprwz r5, f0
+; CHECK-P8-NEXT: mtfprd f1, r6
+; CHECK-P8-NEXT: mtfprd f0, r5
; CHECK-P8-NEXT: xxswapd v4, vs1
; CHECK-P8-NEXT: xxsldwi vs1, v2, v2, 1
; CHECK-P8-NEXT: xxswapd v3, vs0
; CHECK-P8-NEXT: xscvspdpn f0, v2
-; CHECK-P8-NEXT: mtvsrd f4, r4
+; CHECK-P8-NEXT: mtfprd f4, r4
; CHECK-P8-NEXT: xscvspdpn f1, vs1
-; CHECK-P8-NEXT: mfvsrwz r4, f2
+; CHECK-P8-NEXT: mffprwz r4, f2
; CHECK-P8-NEXT: xxswapd v1, vs4
; CHECK-P8-NEXT: vmrglh v2, v4, v3
-; CHECK-P8-NEXT: mtvsrd f2, r4
+; CHECK-P8-NEXT: mtfprd f2, r4
; CHECK-P8-NEXT: xscvdpsxws f0, f0
-; CHECK-P8-NEXT: mfvsrwz r4, f5
+; CHECK-P8-NEXT: mffprwz r4, f5
; CHECK-P8-NEXT: xxswapd v5, vs2
; CHECK-P8-NEXT: xscvdpsxws f1, f1
-; CHECK-P8-NEXT: mfvsrwz r3, f0
-; CHECK-P8-NEXT: mtvsrd f0, r3
-; CHECK-P8-NEXT: mfvsrwz r3, f1
+; CHECK-P8-NEXT: mffprwz r3, f0
+; CHECK-P8-NEXT: mtfprd f0, r3
+; CHECK-P8-NEXT: mffprwz r3, f1
; CHECK-P8-NEXT: xxswapd v3, vs0
-; CHECK-P8-NEXT: mtvsrd f1, r3
-; CHECK-P8-NEXT: mfvsrwz r3, f3
-; CHECK-P8-NEXT: mtvsrd f3, r4
+; CHECK-P8-NEXT: mtfprd f1, r3
+; CHECK-P8-NEXT: mffprwz r3, f3
+; CHECK-P8-NEXT: mtfprd f3, r4
; CHECK-P8-NEXT: xxswapd v4, vs1
-; CHECK-P8-NEXT: mtvsrd f0, r3
+; CHECK-P8-NEXT: mtfprd f0, r3
; CHECK-P8-NEXT: xxswapd v6, vs3
; CHECK-P8-NEXT: xxswapd v0, vs0
; CHECK-P8-NEXT: vmrglh v3, v3, v4
; CHECK-P9-NEXT: xscvspdpn f2, vs2
; CHECK-P9-NEXT: xscvdpsxws f2, f2
; CHECK-P9-NEXT: lxv vs0, 16(r3)
-; CHECK-P9-NEXT: mfvsrwz r3, f2
-; CHECK-P9-NEXT: mtvsrd f2, r3
+; CHECK-P9-NEXT: mffprwz r3, f2
+; CHECK-P9-NEXT: mtfprd f2, r3
; CHECK-P9-NEXT: xxswapd v2, vs2
; CHECK-P9-NEXT: xxswapd vs2, vs1
; CHECK-P9-NEXT: xscvspdpn f2, vs2
; CHECK-P9-NEXT: xscvdpsxws f2, f2
-; CHECK-P9-NEXT: mfvsrwz r3, f2
-; CHECK-P9-NEXT: mtvsrd f2, r3
+; CHECK-P9-NEXT: mffprwz r3, f2
+; CHECK-P9-NEXT: mtfprd f2, r3
; CHECK-P9-NEXT: xxswapd v3, vs2
; CHECK-P9-NEXT: xscvspdpn f2, vs1
; CHECK-P9-NEXT: xxsldwi vs1, vs1, vs1, 1
; CHECK-P9-NEXT: xscvspdpn f1, vs1
; CHECK-P9-NEXT: xscvdpsxws f2, f2
; CHECK-P9-NEXT: xscvdpsxws f1, f1
-; CHECK-P9-NEXT: mfvsrwz r3, f2
-; CHECK-P9-NEXT: mtvsrd f2, r3
-; CHECK-P9-NEXT: mfvsrwz r3, f1
-; CHECK-P9-NEXT: mtvsrd f1, r3
+; CHECK-P9-NEXT: mffprwz r3, f2
+; CHECK-P9-NEXT: mtfprd f2, r3
+; CHECK-P9-NEXT: mffprwz r3, f1
+; CHECK-P9-NEXT: mtfprd f1, r3
; CHECK-P9-NEXT: xxswapd v4, vs1
; CHECK-P9-NEXT: xxsldwi vs1, vs0, vs0, 3
; CHECK-P9-NEXT: xscvspdpn f1, vs1
; CHECK-P9-NEXT: xxswapd v3, vs2
; CHECK-P9-NEXT: vmrglh v3, v3, v4
; CHECK-P9-NEXT: vmrglw v2, v3, v2
-; CHECK-P9-NEXT: mfvsrwz r3, f1
-; CHECK-P9-NEXT: mtvsrd f1, r3
+; CHECK-P9-NEXT: mffprwz r3, f1
+; CHECK-P9-NEXT: mtfprd f1, r3
; CHECK-P9-NEXT: xxswapd v3, vs1
; CHECK-P9-NEXT: xxswapd vs1, vs0
; CHECK-P9-NEXT: xscvspdpn f1, vs1
; CHECK-P9-NEXT: xscvdpsxws f1, f1
-; CHECK-P9-NEXT: mfvsrwz r3, f1
-; CHECK-P9-NEXT: mtvsrd f1, r3
+; CHECK-P9-NEXT: mffprwz r3, f1
+; CHECK-P9-NEXT: mtfprd f1, r3
; CHECK-P9-NEXT: xxswapd v4, vs1
; CHECK-P9-NEXT: xscvspdpn f1, vs0
; CHECK-P9-NEXT: xxsldwi vs0, vs0, vs0, 1
; CHECK-P9-NEXT: xscvspdpn f0, vs0
; CHECK-P9-NEXT: xscvdpsxws f1, f1
; CHECK-P9-NEXT: xscvdpsxws f0, f0
-; CHECK-P9-NEXT: mfvsrwz r3, f1
-; CHECK-P9-NEXT: mtvsrd f1, r3
-; CHECK-P9-NEXT: mfvsrwz r3, f0
-; CHECK-P9-NEXT: mtvsrd f0, r3
+; CHECK-P9-NEXT: mffprwz r3, f1
+; CHECK-P9-NEXT: mtfprd f1, r3
+; CHECK-P9-NEXT: mffprwz r3, f0
+; CHECK-P9-NEXT: mtfprd f0, r3
; CHECK-P9-NEXT: vmrglh v3, v4, v3
; CHECK-P9-NEXT: xxswapd v4, vs1
; CHECK-P9-NEXT: xxswapd v5, vs0
; CHECK-BE-NEXT: xscvspdpn f2, vs2
; CHECK-BE-NEXT: xscvdpsxws f2, f2
; CHECK-BE-NEXT: lxv vs0, 0(r3)
-; CHECK-BE-NEXT: mfvsrwz r3, f2
+; CHECK-BE-NEXT: mffprwz r3, f2
; CHECK-BE-NEXT: xxswapd vs2, vs1
; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: xscvspdpn f2, vs2
; CHECK-BE-NEXT: mtvsrd v2, r3
; CHECK-BE-NEXT: xscvdpsxws f2, f2
-; CHECK-BE-NEXT: mfvsrwz r3, f2
+; CHECK-BE-NEXT: mffprwz r3, f2
; CHECK-BE-NEXT: xscvspdpn f2, vs1
; CHECK-BE-NEXT: xxsldwi vs1, vs1, vs1, 1
; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: vmrghh v2, v3, v2
-; CHECK-BE-NEXT: mfvsrwz r3, f2
+; CHECK-BE-NEXT: mffprwz r3, f2
; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: mtvsrd v3, r3
-; CHECK-BE-NEXT: mfvsrwz r3, f1
+; CHECK-BE-NEXT: mffprwz r3, f1
; CHECK-BE-NEXT: xxsldwi vs1, vs0, vs0, 3
; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: xscvspdpn f1, vs1
; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: xscvdpsxws f1, f1
-; CHECK-BE-NEXT: mfvsrwz r3, f1
+; CHECK-BE-NEXT: mffprwz r3, f1
; CHECK-BE-NEXT: xxswapd vs1, vs0
; CHECK-BE-NEXT: xscvspdpn f1, vs1
; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: vmrghw v2, v3, v2
; CHECK-BE-NEXT: mtvsrd v3, r3
-; CHECK-BE-NEXT: mfvsrwz r3, f1
+; CHECK-BE-NEXT: mffprwz r3, f1
; CHECK-BE-NEXT: xscvspdpn f1, vs0
; CHECK-BE-NEXT: xxsldwi vs0, vs0, vs0, 1
; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: xscvdpsxws f0, f0
; CHECK-BE-NEXT: vmrghh v3, v4, v3
-; CHECK-BE-NEXT: mfvsrwz r3, f1
+; CHECK-BE-NEXT: mffprwz r3, f1
; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: mtvsrd v4, r3
-; CHECK-BE-NEXT: mfvsrwz r3, f0
+; CHECK-BE-NEXT: mffprwz r3, f0
; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: mtvsrd v5, r3
; CHECK-BE-NEXT: vmrghh v4, v4, v5
; CHECK-P8-NEXT: xscvdpsxws f6, f6
; CHECK-P8-NEXT: xscvspdpn f12, vs12
; CHECK-P8-NEXT: xscvdpsxws f5, f5
-; CHECK-P8-NEXT: mfvsrwz r4, f0
+; CHECK-P8-NEXT: mffprwz r4, f0
; CHECK-P8-NEXT: xscvspdpn f11, vs11
; CHECK-P8-NEXT: xscvdpsxws f3, f3
; CHECK-P8-NEXT: xscvspdpn v2, v2
; CHECK-P8-NEXT: xscvdpsxws f8, f8
-; CHECK-P8-NEXT: mtvsrd f0, r4
-; CHECK-P8-NEXT: mfvsrwz r4, f4
+; CHECK-P8-NEXT: mtfprd f0, r4
+; CHECK-P8-NEXT: mffprwz r4, f4
; CHECK-P8-NEXT: xscvdpsxws f7, f7
-; CHECK-P8-NEXT: mfvsrwz r6, f2
+; CHECK-P8-NEXT: mffprwz r6, f2
; CHECK-P8-NEXT: xscvspdpn f13, vs13
; CHECK-P8-NEXT: xscvspdpn v3, v3
; CHECK-P8-NEXT: xscvdpsxws f10, f10
-; CHECK-P8-NEXT: mtvsrd f4, r4
-; CHECK-P8-NEXT: mfvsrwz r4, f1
+; CHECK-P8-NEXT: mtfprd f4, r4
+; CHECK-P8-NEXT: mffprwz r4, f1
; CHECK-P8-NEXT: xscvdpsxws f9, f9
-; CHECK-P8-NEXT: mtvsrd f2, r6
-; CHECK-P8-NEXT: mfvsrwz r6, f6
+; CHECK-P8-NEXT: mtfprd f2, r6
+; CHECK-P8-NEXT: mffprwz r6, f6
; CHECK-P8-NEXT: xscvdpsxws f12, f12
-; CHECK-P8-NEXT: mtvsrd f1, r4
-; CHECK-P8-NEXT: mfvsrwz r4, f5
+; CHECK-P8-NEXT: mtfprd f1, r4
+; CHECK-P8-NEXT: mffprwz r4, f5
; CHECK-P8-NEXT: xscvdpsxws f11, f11
; CHECK-P8-NEXT: xxswapd v4, vs1
-; CHECK-P8-NEXT: mtvsrd f6, r6
-; CHECK-P8-NEXT: mfvsrwz r6, f3
+; CHECK-P8-NEXT: mtfprd f6, r6
+; CHECK-P8-NEXT: mffprwz r6, f3
; CHECK-P8-NEXT: xscvdpsxws v2, v2
; CHECK-P8-NEXT: xxswapd v9, vs6
-; CHECK-P8-NEXT: mtvsrd f5, r4
-; CHECK-P8-NEXT: mfvsrwz r4, f8
-; CHECK-P8-NEXT: mtvsrd f3, r6
+; CHECK-P8-NEXT: mtfprd f5, r4
+; CHECK-P8-NEXT: mffprwz r4, f8
+; CHECK-P8-NEXT: mtfprd f3, r6
; CHECK-P8-NEXT: xxswapd v0, vs5
-; CHECK-P8-NEXT: mfvsrwz r6, f7
+; CHECK-P8-NEXT: mffprwz r6, f7
; CHECK-P8-NEXT: xscvdpsxws f13, f13
; CHECK-P8-NEXT: xxswapd v5, vs3
; CHECK-P8-NEXT: xscvdpsxws v3, v3
-; CHECK-P8-NEXT: mtvsrd f8, r4
-; CHECK-P8-NEXT: mfvsrwz r4, f10
-; CHECK-P8-NEXT: mtvsrd f7, r6
-; CHECK-P8-NEXT: mfvsrwz r6, f9
-; CHECK-P8-NEXT: mtvsrd f10, r4
-; CHECK-P8-NEXT: mfvsrwz r4, f12
-; CHECK-P8-NEXT: mtvsrd f9, r6
+; CHECK-P8-NEXT: mtfprd f8, r4
+; CHECK-P8-NEXT: mffprwz r4, f10
+; CHECK-P8-NEXT: mtfprd f7, r6
+; CHECK-P8-NEXT: mffprwz r6, f9
+; CHECK-P8-NEXT: mtfprd f10, r4
+; CHECK-P8-NEXT: mffprwz r4, f12
+; CHECK-P8-NEXT: mtfprd f9, r6
; CHECK-P8-NEXT: xxswapd v6, vs10
-; CHECK-P8-NEXT: mfvsrwz r6, f11
-; CHECK-P8-NEXT: mtvsrd f12, r4
+; CHECK-P8-NEXT: mffprwz r6, f11
+; CHECK-P8-NEXT: mtfprd f12, r4
; CHECK-P8-NEXT: xxswapd v1, vs9
; CHECK-P8-NEXT: mfvsrwz r4, v2
; CHECK-P8-NEXT: xxswapd v2, vs0
-; CHECK-P8-NEXT: mtvsrd f11, r6
-; CHECK-P8-NEXT: mfvsrwz r6, f13
-; CHECK-P8-NEXT: mtvsrd f0, r4
+; CHECK-P8-NEXT: mtfprd f11, r6
+; CHECK-P8-NEXT: mffprwz r6, f13
+; CHECK-P8-NEXT: mtfprd f0, r4
; CHECK-P8-NEXT: xxswapd v7, vs11
; CHECK-P8-NEXT: mfvsrwz r4, v3
; CHECK-P8-NEXT: vmrglh v3, v5, v4
; CHECK-P8-NEXT: vmrglh v2, v2, v0
; CHECK-P8-NEXT: xxswapd v5, vs8
; CHECK-P8-NEXT: xxswapd v0, vs2
-; CHECK-P8-NEXT: mtvsrd f13, r6
-; CHECK-P8-NEXT: mtvsrd f1, r4
+; CHECK-P8-NEXT: mtfprd f13, r6
+; CHECK-P8-NEXT: mtfprd f1, r4
; CHECK-P8-NEXT: xxswapd v8, vs0
; CHECK-P8-NEXT: vmrglh v4, v5, v4
; CHECK-P8-NEXT: vmrglh v5, v0, v1
; CHECK-P9-NEXT: xscvspdpn f1, vs1
; CHECK-P9-NEXT: xscvdpsxws f4, f4
; CHECK-P9-NEXT: xscvdpsxws f6, f6
-; CHECK-P9-NEXT: mfvsrwz r5, f5
+; CHECK-P9-NEXT: mffprwz r5, f5
; CHECK-P9-NEXT: xscvdpsxws f1, f1
; CHECK-P9-NEXT: xscvdpsxws f7, f7
; CHECK-P9-NEXT: xscvdpsxws f3, f3
-; CHECK-P9-NEXT: mtvsrd f5, r5
-; CHECK-P9-NEXT: mfvsrwz r5, f8
-; CHECK-P9-NEXT: mtvsrd f8, r5
-; CHECK-P9-NEXT: mfvsrwz r5, f2
+; CHECK-P9-NEXT: mtfprd f5, r5
+; CHECK-P9-NEXT: mffprwz r5, f8
+; CHECK-P9-NEXT: mtfprd f8, r5
+; CHECK-P9-NEXT: mffprwz r5, f2
; CHECK-P9-NEXT: lxv vs0, 32(r4)
; CHECK-P9-NEXT: xxsldwi vs9, vs0, vs0, 3
; CHECK-P9-NEXT: xxswapd vs10, vs0
; CHECK-P9-NEXT: xscvspdpn f10, vs10
; CHECK-P9-NEXT: xscvdpsxws f9, f9
; CHECK-P9-NEXT: xscvdpsxws f10, f10
-; CHECK-P9-NEXT: mtvsrd f2, r5
-; CHECK-P9-NEXT: mfvsrwz r5, f4
-; CHECK-P9-NEXT: mtvsrd f4, r5
-; CHECK-P9-NEXT: mfvsrwz r5, f1
-; CHECK-P9-NEXT: mtvsrd f1, r5
-; CHECK-P9-NEXT: mfvsrwz r5, f6
+; CHECK-P9-NEXT: mtfprd f2, r5
+; CHECK-P9-NEXT: mffprwz r5, f4
+; CHECK-P9-NEXT: mtfprd f4, r5
+; CHECK-P9-NEXT: mffprwz r5, f1
+; CHECK-P9-NEXT: mtfprd f1, r5
+; CHECK-P9-NEXT: mffprwz r5, f6
; CHECK-P9-NEXT: xxswapd v2, vs2
; CHECK-P9-NEXT: xxswapd v3, vs4
; CHECK-P9-NEXT: xscvspdpn f2, vs0
; CHECK-P9-NEXT: xxsldwi vs0, vs0, vs0, 1
; CHECK-P9-NEXT: xscvspdpn f0, vs0
; CHECK-P9-NEXT: xscvdpsxws f2, f2
-; CHECK-P9-NEXT: mtvsrd f6, r5
-; CHECK-P9-NEXT: mfvsrwz r5, f7
+; CHECK-P9-NEXT: mtfprd f6, r5
+; CHECK-P9-NEXT: mffprwz r5, f7
; CHECK-P9-NEXT: xxswapd v4, vs1
; CHECK-P9-NEXT: lxv vs1, 48(r4)
; CHECK-P9-NEXT: vmrglh v2, v3, v2
; CHECK-P9-NEXT: xxswapd v3, vs5
-; CHECK-P9-NEXT: mtvsrd f7, r5
-; CHECK-P9-NEXT: mfvsrwz r5, f3
+; CHECK-P9-NEXT: mtfprd f7, r5
+; CHECK-P9-NEXT: mffprwz r5, f3
; CHECK-P9-NEXT: vmrglh v3, v3, v4
; CHECK-P9-NEXT: xxswapd v4, vs6
; CHECK-P9-NEXT: xxswapd v5, vs7
-; CHECK-P9-NEXT: mtvsrd f3, r5
+; CHECK-P9-NEXT: mtfprd f3, r5
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: xxswapd v0, vs3
; CHECK-P9-NEXT: vmrglh v4, v5, v4
; CHECK-P9-NEXT: xxswapd v5, vs8
; CHECK-P9-NEXT: vmrglh v5, v5, v0
-; CHECK-P9-NEXT: mfvsrwz r4, f2
-; CHECK-P9-NEXT: mtvsrd f2, r4
-; CHECK-P9-NEXT: mfvsrwz r4, f0
+; CHECK-P9-NEXT: mffprwz r4, f2
+; CHECK-P9-NEXT: mtfprd f2, r4
+; CHECK-P9-NEXT: mffprwz r4, f0
; CHECK-P9-NEXT: vmrglw v2, v3, v2
-; CHECK-P9-NEXT: mtvsrd f0, r4
+; CHECK-P9-NEXT: mtfprd f0, r4
; CHECK-P9-NEXT: vmrglw v3, v5, v4
; CHECK-P9-NEXT: xxswapd v4, vs2
; CHECK-P9-NEXT: xxmrgld vs2, v3, v2
; CHECK-P9-NEXT: xxsldwi vs0, vs1, vs1, 3
; CHECK-P9-NEXT: xscvspdpn f0, vs0
; CHECK-P9-NEXT: xscvdpsxws f0, f0
-; CHECK-P9-NEXT: mfvsrwz r4, f0
-; CHECK-P9-NEXT: mtvsrd f0, r4
+; CHECK-P9-NEXT: mffprwz r4, f0
+; CHECK-P9-NEXT: mtfprd f0, r4
; CHECK-P9-NEXT: xxswapd v3, vs0
; CHECK-P9-NEXT: xxswapd vs0, vs1
; CHECK-P9-NEXT: xscvspdpn f0, vs0
; CHECK-P9-NEXT: xscvdpsxws f0, f0
-; CHECK-P9-NEXT: mfvsrwz r4, f0
-; CHECK-P9-NEXT: mtvsrd f0, r4
+; CHECK-P9-NEXT: mffprwz r4, f0
+; CHECK-P9-NEXT: mtfprd f0, r4
; CHECK-P9-NEXT: vmrglh v2, v4, v2
; CHECK-P9-NEXT: xxswapd v4, vs0
; CHECK-P9-NEXT: xscvspdpn f0, vs1
; CHECK-P9-NEXT: xscvdpsxws f0, f0
-; CHECK-P9-NEXT: mfvsrwz r4, f0
-; CHECK-P9-NEXT: mtvsrd f0, r4
+; CHECK-P9-NEXT: mffprwz r4, f0
+; CHECK-P9-NEXT: mtfprd f0, r4
; CHECK-P9-NEXT: vmrglh v3, v4, v3
; CHECK-P9-NEXT: xxswapd v4, vs0
; CHECK-P9-NEXT: xxsldwi vs0, vs1, vs1, 1
; CHECK-P9-NEXT: xscvspdpn f0, vs0
; CHECK-P9-NEXT: xscvdpsxws f0, f0
-; CHECK-P9-NEXT: mfvsrwz r5, f9
-; CHECK-P9-NEXT: mtvsrd f9, r5
-; CHECK-P9-NEXT: mfvsrwz r5, f10
-; CHECK-P9-NEXT: mtvsrd f10, r5
+; CHECK-P9-NEXT: mffprwz r5, f9
+; CHECK-P9-NEXT: mtfprd f9, r5
+; CHECK-P9-NEXT: mffprwz r5, f10
+; CHECK-P9-NEXT: mtfprd f10, r5
; CHECK-P9-NEXT: xxswapd v0, vs9
; CHECK-P9-NEXT: xxswapd v1, vs10
; CHECK-P9-NEXT: vmrglh v0, v1, v0
; CHECK-P9-NEXT: vmrglw v2, v2, v0
; CHECK-P9-NEXT: stxv vs2, 0(r3)
-; CHECK-P9-NEXT: mfvsrwz r4, f0
-; CHECK-P9-NEXT: mtvsrd f0, r4
+; CHECK-P9-NEXT: mffprwz r4, f0
+; CHECK-P9-NEXT: mtfprd f0, r4
; CHECK-P9-NEXT: xxswapd v5, vs0
; CHECK-P9-NEXT: vmrglh v4, v4, v5
; CHECK-P9-NEXT: vmrglw v3, v4, v3
; CHECK-BE-NEXT: xscvspdpn f3, vs3
; CHECK-BE-NEXT: xscvdpsxws f2, f2
; CHECK-BE-NEXT: xscvdpsxws f3, f3
-; CHECK-BE-NEXT: mfvsrwz r5, f2
+; CHECK-BE-NEXT: mffprwz r5, f2
; CHECK-BE-NEXT: xscvspdpn f4, vs1
; CHECK-BE-NEXT: xxsldwi vs1, vs1, vs1, 1
; CHECK-BE-NEXT: xscvspdpn f1, vs1
; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: mtvsrd v2, r5
-; CHECK-BE-NEXT: mfvsrwz r5, f3
+; CHECK-BE-NEXT: mffprwz r5, f3
; CHECK-BE-NEXT: xscvdpsxws f3, f4
; CHECK-BE-NEXT: lxv vs0, 0(r4)
; CHECK-BE-NEXT: xxsldwi vs2, vs0, vs0, 3
; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: mtvsrd v3, r5
; CHECK-BE-NEXT: vmrghh v2, v3, v2
-; CHECK-BE-NEXT: mfvsrwz r5, f3
+; CHECK-BE-NEXT: mffprwz r5, f3
; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: mtvsrd v3, r5
-; CHECK-BE-NEXT: mfvsrwz r5, f1
+; CHECK-BE-NEXT: mffprwz r5, f1
; CHECK-BE-NEXT: xxswapd vs1, vs0
; CHECK-BE-NEXT: xscvdpsxws f2, f2
; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: xscvspdpn f1, vs1
; CHECK-BE-NEXT: mtvsrd v4, r5
-; CHECK-BE-NEXT: mfvsrwz r5, f2
+; CHECK-BE-NEXT: mffprwz r5, f2
; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: vmrghh v3, v3, v4
; CHECK-BE-NEXT: mtvsrd v4, r5
; CHECK-BE-NEXT: vmrghw v2, v3, v2
-; CHECK-BE-NEXT: mfvsrwz r5, f1
+; CHECK-BE-NEXT: mffprwz r5, f1
; CHECK-BE-NEXT: xscvspdpn f1, vs0
; CHECK-BE-NEXT: xxsldwi vs0, vs0, vs0, 1
; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: mtvsrd v5, r5
; CHECK-BE-NEXT: xscvdpsxws f0, f0
; CHECK-BE-NEXT: vmrghh v4, v5, v4
-; CHECK-BE-NEXT: mfvsrwz r5, f1
+; CHECK-BE-NEXT: mffprwz r5, f1
; CHECK-BE-NEXT: lxv vs1, 48(r4)
; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: mtvsrd v5, r5
-; CHECK-BE-NEXT: mfvsrwz r5, f0
+; CHECK-BE-NEXT: mffprwz r5, f0
; CHECK-BE-NEXT: lxv vs0, 32(r4)
; CHECK-BE-NEXT: xscvspdpn f5, vs1
; CHECK-BE-NEXT: xxsldwi vs2, vs1, vs1, 3
; CHECK-BE-NEXT: xscvdpsxws f2, f2
; CHECK-BE-NEXT: vmrghw v3, v5, v4
; CHECK-BE-NEXT: xscvdpsxws f3, f3
-; CHECK-BE-NEXT: mfvsrwz r4, f5
+; CHECK-BE-NEXT: mffprwz r4, f5
; CHECK-BE-NEXT: xxmrghd vs4, v3, v2
; CHECK-BE-NEXT: sldi r4, r4, 48
; CHECK-BE-NEXT: mtvsrd v2, r4
-; CHECK-BE-NEXT: mfvsrwz r4, f2
+; CHECK-BE-NEXT: mffprwz r4, f2
; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: stxv vs4, 0(r3)
; CHECK-BE-NEXT: sldi r4, r4, 48
; CHECK-BE-NEXT: mtvsrd v3, r4
-; CHECK-BE-NEXT: mfvsrwz r4, f3
+; CHECK-BE-NEXT: mffprwz r4, f3
; CHECK-BE-NEXT: sldi r4, r4, 48
; CHECK-BE-NEXT: mtvsrd v4, r4
-; CHECK-BE-NEXT: mfvsrwz r4, f1
+; CHECK-BE-NEXT: mffprwz r4, f1
; CHECK-BE-NEXT: xxsldwi vs1, vs0, vs0, 3
; CHECK-BE-NEXT: sldi r4, r4, 48
; CHECK-BE-NEXT: xscvspdpn f1, vs1
; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: vmrghh v3, v4, v3
; CHECK-BE-NEXT: mtvsrd v4, r4
-; CHECK-BE-NEXT: mfvsrwz r4, f1
+; CHECK-BE-NEXT: mffprwz r4, f1
; CHECK-BE-NEXT: xxswapd vs1, vs0
; CHECK-BE-NEXT: xscvspdpn f1, vs1
; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: sldi r4, r4, 48
; CHECK-BE-NEXT: vmrghw v2, v2, v3
; CHECK-BE-NEXT: mtvsrd v3, r4
-; CHECK-BE-NEXT: mfvsrwz r4, f1
+; CHECK-BE-NEXT: mffprwz r4, f1
; CHECK-BE-NEXT: xscvspdpn f1, vs0
; CHECK-BE-NEXT: xxsldwi vs0, vs0, vs0, 1
; CHECK-BE-NEXT: sldi r4, r4, 48
; CHECK-BE-NEXT: mtvsrd v4, r4
; CHECK-BE-NEXT: xscvdpsxws f0, f0
; CHECK-BE-NEXT: vmrghh v3, v4, v3
-; CHECK-BE-NEXT: mfvsrwz r4, f1
+; CHECK-BE-NEXT: mffprwz r4, f1
; CHECK-BE-NEXT: sldi r4, r4, 48
; CHECK-BE-NEXT: mtvsrd v4, r4
-; CHECK-BE-NEXT: mfvsrwz r4, f0
+; CHECK-BE-NEXT: mffprwz r4, f0
; CHECK-BE-NEXT: sldi r4, r4, 48
; CHECK-BE-NEXT: mtvsrd v5, r4
; CHECK-BE-NEXT: vmrghh v4, v4, v5
define <2 x i64> @test2elt(i64 %a.coerce) local_unnamed_addr #0 {
; CHECK-P8-LABEL: test2elt:
; CHECK-P8: # %bb.0: # %entry
-; CHECK-P8-NEXT: mtvsrd f0, r3
+; CHECK-P8-NEXT: mtfprd f0, r3
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: xxmrglw vs0, v2, v2
; CHECK-P8-NEXT: xvcvspdp vs0, vs0
;
; CHECK-P9-LABEL: test2elt:
; CHECK-P9: # %bb.0: # %entry
-; CHECK-P9-NEXT: mtvsrd f0, r3
+; CHECK-P9-NEXT: mtfprd f0, r3
; CHECK-P9-NEXT: xxswapd v2, vs0
; CHECK-P9-NEXT: xxmrglw vs0, v2, v2
; CHECK-P9-NEXT: xvcvspdp vs0, vs0
;
; CHECK-BE-LABEL: test2elt:
; CHECK-BE: # %bb.0: # %entry
-; CHECK-BE-NEXT: mtvsrd f0, r3
+; CHECK-BE-NEXT: mtfprd f0, r3
; CHECK-BE-NEXT: xxmrghw vs0, vs0, vs0
; CHECK-BE-NEXT: xvcvspdp vs0, vs0
; CHECK-BE-NEXT: xvcvdpuxds v2, vs0
define <2 x i64> @test2elt_signed(i64 %a.coerce) local_unnamed_addr #0 {
; CHECK-P8-LABEL: test2elt_signed:
; CHECK-P8: # %bb.0: # %entry
-; CHECK-P8-NEXT: mtvsrd f0, r3
+; CHECK-P8-NEXT: mtfprd f0, r3
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: xxmrglw vs0, v2, v2
; CHECK-P8-NEXT: xvcvspdp vs0, vs0
;
; CHECK-P9-LABEL: test2elt_signed:
; CHECK-P9: # %bb.0: # %entry
-; CHECK-P9-NEXT: mtvsrd f0, r3
+; CHECK-P9-NEXT: mtfprd f0, r3
; CHECK-P9-NEXT: xxswapd v2, vs0
; CHECK-P9-NEXT: xxmrglw vs0, v2, v2
; CHECK-P9-NEXT: xvcvspdp vs0, vs0
;
; CHECK-BE-LABEL: test2elt_signed:
; CHECK-BE: # %bb.0: # %entry
-; CHECK-BE-NEXT: mtvsrd f0, r3
+; CHECK-BE-NEXT: mtfprd f0, r3
; CHECK-BE-NEXT: xxmrghw vs0, vs0, vs0
; CHECK-BE-NEXT: xvcvspdp vs0, vs0
; CHECK-BE-NEXT: xvcvdpuxds v2, vs0
define i16 @test2elt(i64 %a.coerce) local_unnamed_addr #0 {
; CHECK-P8-LABEL: test2elt:
; CHECK-P8: # %bb.0: # %entry
-; CHECK-P8-NEXT: mtvsrd f0, r3
+; CHECK-P8-NEXT: mtfprd f0, r3
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: xscvspdpn f0, vs0
; CHECK-P8-NEXT: xxsldwi vs1, v2, v2, 3
; CHECK-P8-NEXT: xscvspdpn f1, vs1
; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: xscvdpsxws f1, f1
-; CHECK-P8-NEXT: mfvsrwz r4, f0
-; CHECK-P8-NEXT: mfvsrwz r3, f1
-; CHECK-P8-NEXT: mtvsrd f1, r4
-; CHECK-P8-NEXT: mtvsrd f0, r3
+; CHECK-P8-NEXT: mffprwz r4, f0
+; CHECK-P8-NEXT: mffprwz r3, f1
+; CHECK-P8-NEXT: mtfprd f1, r4
+; CHECK-P8-NEXT: mtfprd f0, r3
; CHECK-P8-NEXT: xxswapd v3, vs1
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: vmrglb v2, v3, v2
; CHECK-P8-NEXT: xxswapd vs0, v2
-; CHECK-P8-NEXT: mfvsrd r3, f0
+; CHECK-P8-NEXT: mffprd r3, f0
; CHECK-P8-NEXT: clrldi r3, r3, 48
; CHECK-P8-NEXT: sth r3, -2(r1)
; CHECK-P8-NEXT: lhz r3, -2(r1)
;
; CHECK-P9-LABEL: test2elt:
; CHECK-P9: # %bb.0: # %entry
-; CHECK-P9-NEXT: mtvsrd f0, r3
+; CHECK-P9-NEXT: mtfprd f0, r3
; CHECK-P9-NEXT: xxswapd v2, vs0
; CHECK-P9-NEXT: xscvspdpn f0, vs0
; CHECK-P9-NEXT: xxsldwi vs1, v2, v2, 3
; CHECK-P9-NEXT: xscvspdpn f1, vs1
; CHECK-P9-NEXT: xscvdpsxws f1, f1
; CHECK-P9-NEXT: xscvdpsxws f0, f0
-; CHECK-P9-NEXT: mfvsrwz r3, f1
-; CHECK-P9-NEXT: mtvsrd f1, r3
-; CHECK-P9-NEXT: mfvsrwz r3, f0
-; CHECK-P9-NEXT: mtvsrd f0, r3
+; CHECK-P9-NEXT: mffprwz r3, f1
+; CHECK-P9-NEXT: mtfprd f1, r3
+; CHECK-P9-NEXT: mffprwz r3, f0
+; CHECK-P9-NEXT: mtfprd f0, r3
; CHECK-P9-NEXT: xxswapd v2, vs1
; CHECK-P9-NEXT: xxswapd v3, vs0
; CHECK-P9-NEXT: vmrglb v2, v3, v2
;
; CHECK-BE-LABEL: test2elt:
; CHECK-BE: # %bb.0: # %entry
-; CHECK-BE-NEXT: mtvsrd f0, r3
+; CHECK-BE-NEXT: mtfprd f0, r3
; CHECK-BE-NEXT: xscvspdpn f1, vs0
; CHECK-BE-NEXT: xxsldwi vs0, vs0, vs0, 1
; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: xscvspdpn f0, vs0
; CHECK-BE-NEXT: xscvdpsxws f0, f0
-; CHECK-BE-NEXT: mfvsrwz r3, f1
+; CHECK-BE-NEXT: mffprwz r3, f1
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v2, r3
-; CHECK-BE-NEXT: mfvsrwz r3, f0
+; CHECK-BE-NEXT: mffprwz r3, f0
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: addi r3, r1, -2
; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: xscvdpsxws f2, f2
; CHECK-P8-NEXT: xscvdpsxws f3, f3
-; CHECK-P8-NEXT: mfvsrwz r3, f1
-; CHECK-P8-NEXT: mtvsrd f1, r3
-; CHECK-P8-NEXT: mfvsrwz r3, f0
-; CHECK-P8-NEXT: mfvsrwz r4, f2
+; CHECK-P8-NEXT: mffprwz r3, f1
+; CHECK-P8-NEXT: mtfprd f1, r3
+; CHECK-P8-NEXT: mffprwz r3, f0
+; CHECK-P8-NEXT: mffprwz r4, f2
; CHECK-P8-NEXT: xxswapd v4, vs1
-; CHECK-P8-NEXT: mtvsrd f0, r3
-; CHECK-P8-NEXT: mfvsrwz r3, f3
-; CHECK-P8-NEXT: mtvsrd f2, r4
+; CHECK-P8-NEXT: mtfprd f0, r3
+; CHECK-P8-NEXT: mffprwz r3, f3
+; CHECK-P8-NEXT: mtfprd f2, r4
; CHECK-P8-NEXT: xxswapd v2, vs0
-; CHECK-P8-NEXT: mtvsrd f3, r3
+; CHECK-P8-NEXT: mtfprd f3, r3
; CHECK-P8-NEXT: xxswapd v3, vs2
; CHECK-P8-NEXT: xxswapd v5, vs3
; CHECK-P8-NEXT: vmrglb v2, v3, v2
; CHECK-P8-NEXT: vmrglb v3, v4, v5
; CHECK-P8-NEXT: vmrglh v2, v3, v2
; CHECK-P8-NEXT: xxswapd vs0, v2
-; CHECK-P8-NEXT: mfvsrwz r3, f0
+; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: blr
;
; CHECK-P9-LABEL: test4elt:
; CHECK-P9-NEXT: xxsldwi vs0, v2, v2, 3
; CHECK-P9-NEXT: xscvspdpn f0, vs0
; CHECK-P9-NEXT: xscvdpsxws f0, f0
-; CHECK-P9-NEXT: mfvsrwz r3, f0
-; CHECK-P9-NEXT: mtvsrd f0, r3
+; CHECK-P9-NEXT: mffprwz r3, f0
+; CHECK-P9-NEXT: mtfprd f0, r3
; CHECK-P9-NEXT: xxswapd v3, vs0
; CHECK-P9-NEXT: xxswapd vs0, v2
; CHECK-P9-NEXT: xscvspdpn f0, vs0
; CHECK-P9-NEXT: xscvdpsxws f0, f0
-; CHECK-P9-NEXT: mfvsrwz r3, f0
-; CHECK-P9-NEXT: mtvsrd f0, r3
+; CHECK-P9-NEXT: mffprwz r3, f0
+; CHECK-P9-NEXT: mtfprd f0, r3
; CHECK-P9-NEXT: xxswapd v4, vs0
; CHECK-P9-NEXT: xscvspdpn f0, v2
; CHECK-P9-NEXT: xscvdpsxws f0, f0
-; CHECK-P9-NEXT: mfvsrwz r3, f0
-; CHECK-P9-NEXT: mtvsrd f0, r3
+; CHECK-P9-NEXT: mffprwz r3, f0
+; CHECK-P9-NEXT: mtfprd f0, r3
; CHECK-P9-NEXT: vmrglb v3, v4, v3
; CHECK-P9-NEXT: xxswapd v4, vs0
; CHECK-P9-NEXT: xxsldwi vs0, v2, v2, 1
; CHECK-P9-NEXT: xscvspdpn f0, vs0
; CHECK-P9-NEXT: xscvdpsxws f0, f0
-; CHECK-P9-NEXT: mfvsrwz r3, f0
-; CHECK-P9-NEXT: mtvsrd f0, r3
+; CHECK-P9-NEXT: mffprwz r3, f0
+; CHECK-P9-NEXT: mtfprd f0, r3
; CHECK-P9-NEXT: li r3, 0
; CHECK-P9-NEXT: xxswapd v2, vs0
; CHECK-P9-NEXT: vmrglb v2, v4, v2
; CHECK-BE-NEXT: xxsldwi vs0, v2, v2, 3
; CHECK-BE-NEXT: xscvspdpn f0, vs0
; CHECK-BE-NEXT: xscvdpsxws f0, f0
-; CHECK-BE-NEXT: mfvsrwz r3, f0
+; CHECK-BE-NEXT: mffprwz r3, f0
; CHECK-BE-NEXT: xxswapd vs0, v2
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvspdpn f0, vs0
; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: xscvdpsxws f0, f0
-; CHECK-BE-NEXT: mfvsrwz r3, f0
+; CHECK-BE-NEXT: mffprwz r3, f0
; CHECK-BE-NEXT: xscvspdpn f0, v2
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvdpsxws f0, f0
; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: vmrghb v3, v4, v3
-; CHECK-BE-NEXT: mfvsrwz r3, f0
+; CHECK-BE-NEXT: mffprwz r3, f0
; CHECK-BE-NEXT: xxsldwi vs0, v2, v2, 1
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvspdpn f0, vs0
; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: xscvdpsxws f0, f0
-; CHECK-BE-NEXT: mfvsrwz r3, f0
+; CHECK-BE-NEXT: mffprwz r3, f0
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v2, r3
; CHECK-BE-NEXT: li r3, 0
; CHECK-P8-NEXT: xscvdpsxws f2, f2
; CHECK-P8-NEXT: xscvdpsxws f3, f3
; CHECK-P8-NEXT: xscvdpsxws f5, f5
-; CHECK-P8-NEXT: mfvsrwz r4, f4
-; CHECK-P8-NEXT: mfvsrwz r6, f1
-; CHECK-P8-NEXT: mfvsrwz r5, f0
-; CHECK-P8-NEXT: mtvsrd f1, r6
-; CHECK-P8-NEXT: mtvsrd f0, r5
+; CHECK-P8-NEXT: mffprwz r4, f4
+; CHECK-P8-NEXT: mffprwz r6, f1
+; CHECK-P8-NEXT: mffprwz r5, f0
+; CHECK-P8-NEXT: mtfprd f1, r6
+; CHECK-P8-NEXT: mtfprd f0, r5
; CHECK-P8-NEXT: xxswapd v4, vs1
; CHECK-P8-NEXT: xxsldwi vs1, v2, v2, 1
; CHECK-P8-NEXT: xxswapd v3, vs0
; CHECK-P8-NEXT: xscvspdpn f0, v2
-; CHECK-P8-NEXT: mtvsrd f4, r4
+; CHECK-P8-NEXT: mtfprd f4, r4
; CHECK-P8-NEXT: xscvspdpn f1, vs1
-; CHECK-P8-NEXT: mfvsrwz r4, f2
+; CHECK-P8-NEXT: mffprwz r4, f2
; CHECK-P8-NEXT: xxswapd v1, vs4
; CHECK-P8-NEXT: vmrglb v2, v4, v3
-; CHECK-P8-NEXT: mtvsrd f2, r4
+; CHECK-P8-NEXT: mtfprd f2, r4
; CHECK-P8-NEXT: xscvdpsxws f0, f0
-; CHECK-P8-NEXT: mfvsrwz r4, f5
+; CHECK-P8-NEXT: mffprwz r4, f5
; CHECK-P8-NEXT: xxswapd v5, vs2
; CHECK-P8-NEXT: xscvdpsxws f1, f1
-; CHECK-P8-NEXT: mfvsrwz r3, f0
-; CHECK-P8-NEXT: mtvsrd f0, r3
-; CHECK-P8-NEXT: mfvsrwz r3, f1
+; CHECK-P8-NEXT: mffprwz r3, f0
+; CHECK-P8-NEXT: mtfprd f0, r3
+; CHECK-P8-NEXT: mffprwz r3, f1
; CHECK-P8-NEXT: xxswapd v3, vs0
-; CHECK-P8-NEXT: mtvsrd f1, r3
-; CHECK-P8-NEXT: mfvsrwz r3, f3
-; CHECK-P8-NEXT: mtvsrd f3, r4
+; CHECK-P8-NEXT: mtfprd f1, r3
+; CHECK-P8-NEXT: mffprwz r3, f3
+; CHECK-P8-NEXT: mtfprd f3, r4
; CHECK-P8-NEXT: xxswapd v4, vs1
-; CHECK-P8-NEXT: mtvsrd f0, r3
+; CHECK-P8-NEXT: mtfprd f0, r3
; CHECK-P8-NEXT: xxswapd v6, vs3
; CHECK-P8-NEXT: xxswapd v0, vs0
; CHECK-P8-NEXT: vmrglb v3, v3, v4
; CHECK-P8-NEXT: vmrglh v3, v5, v4
; CHECK-P8-NEXT: vmrglw v2, v3, v2
; CHECK-P8-NEXT: xxswapd vs0, v2
-; CHECK-P8-NEXT: mfvsrd r3, f0
+; CHECK-P8-NEXT: mffprd r3, f0
; CHECK-P8-NEXT: blr
;
; CHECK-P9-LABEL: test8elt:
; CHECK-P9-NEXT: xscvspdpn f2, vs2
; CHECK-P9-NEXT: xscvdpsxws f2, f2
; CHECK-P9-NEXT: lxv vs0, 16(r3)
-; CHECK-P9-NEXT: mfvsrwz r3, f2
-; CHECK-P9-NEXT: mtvsrd f2, r3
+; CHECK-P9-NEXT: mffprwz r3, f2
+; CHECK-P9-NEXT: mtfprd f2, r3
; CHECK-P9-NEXT: xxswapd v2, vs2
; CHECK-P9-NEXT: xxswapd vs2, vs1
; CHECK-P9-NEXT: xscvspdpn f2, vs2
; CHECK-P9-NEXT: xscvdpsxws f2, f2
-; CHECK-P9-NEXT: mfvsrwz r3, f2
-; CHECK-P9-NEXT: mtvsrd f2, r3
+; CHECK-P9-NEXT: mffprwz r3, f2
+; CHECK-P9-NEXT: mtfprd f2, r3
; CHECK-P9-NEXT: xxswapd v3, vs2
; CHECK-P9-NEXT: xscvspdpn f2, vs1
; CHECK-P9-NEXT: xxsldwi vs1, vs1, vs1, 1
; CHECK-P9-NEXT: xscvspdpn f1, vs1
; CHECK-P9-NEXT: xscvdpsxws f2, f2
; CHECK-P9-NEXT: xscvdpsxws f1, f1
-; CHECK-P9-NEXT: mfvsrwz r3, f2
-; CHECK-P9-NEXT: mtvsrd f2, r3
-; CHECK-P9-NEXT: mfvsrwz r3, f1
-; CHECK-P9-NEXT: mtvsrd f1, r3
+; CHECK-P9-NEXT: mffprwz r3, f2
+; CHECK-P9-NEXT: mtfprd f2, r3
+; CHECK-P9-NEXT: mffprwz r3, f1
+; CHECK-P9-NEXT: mtfprd f1, r3
; CHECK-P9-NEXT: xxswapd v4, vs1
; CHECK-P9-NEXT: xxsldwi vs1, vs0, vs0, 3
; CHECK-P9-NEXT: xscvspdpn f1, vs1
; CHECK-P9-NEXT: xxswapd v3, vs2
; CHECK-P9-NEXT: vmrglb v3, v3, v4
; CHECK-P9-NEXT: vmrglh v2, v3, v2
-; CHECK-P9-NEXT: mfvsrwz r3, f1
-; CHECK-P9-NEXT: mtvsrd f1, r3
+; CHECK-P9-NEXT: mffprwz r3, f1
+; CHECK-P9-NEXT: mtfprd f1, r3
; CHECK-P9-NEXT: xxswapd v3, vs1
; CHECK-P9-NEXT: xxswapd vs1, vs0
; CHECK-P9-NEXT: xscvspdpn f1, vs1
; CHECK-P9-NEXT: xscvdpsxws f1, f1
-; CHECK-P9-NEXT: mfvsrwz r3, f1
-; CHECK-P9-NEXT: mtvsrd f1, r3
+; CHECK-P9-NEXT: mffprwz r3, f1
+; CHECK-P9-NEXT: mtfprd f1, r3
; CHECK-P9-NEXT: xxswapd v4, vs1
; CHECK-P9-NEXT: xscvspdpn f1, vs0
; CHECK-P9-NEXT: xxsldwi vs0, vs0, vs0, 1
; CHECK-P9-NEXT: xscvspdpn f0, vs0
; CHECK-P9-NEXT: xscvdpsxws f1, f1
; CHECK-P9-NEXT: xscvdpsxws f0, f0
-; CHECK-P9-NEXT: mfvsrwz r3, f1
-; CHECK-P9-NEXT: mtvsrd f1, r3
-; CHECK-P9-NEXT: mfvsrwz r3, f0
-; CHECK-P9-NEXT: mtvsrd f0, r3
+; CHECK-P9-NEXT: mffprwz r3, f1
+; CHECK-P9-NEXT: mtfprd f1, r3
+; CHECK-P9-NEXT: mffprwz r3, f0
+; CHECK-P9-NEXT: mtfprd f0, r3
; CHECK-P9-NEXT: vmrglb v3, v4, v3
; CHECK-P9-NEXT: xxswapd v4, vs1
; CHECK-P9-NEXT: xxswapd v5, vs0
; CHECK-BE-NEXT: xscvspdpn f2, vs2
; CHECK-BE-NEXT: xscvdpsxws f2, f2
; CHECK-BE-NEXT: lxv vs0, 0(r3)
-; CHECK-BE-NEXT: mfvsrwz r3, f2
+; CHECK-BE-NEXT: mffprwz r3, f2
; CHECK-BE-NEXT: xxswapd vs2, vs1
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvspdpn f2, vs2
; CHECK-BE-NEXT: mtvsrd v2, r3
; CHECK-BE-NEXT: xscvdpsxws f2, f2
-; CHECK-BE-NEXT: mfvsrwz r3, f2
+; CHECK-BE-NEXT: mffprwz r3, f2
; CHECK-BE-NEXT: xscvspdpn f2, vs1
; CHECK-BE-NEXT: xxsldwi vs1, vs1, vs1, 1
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: vmrghb v2, v3, v2
-; CHECK-BE-NEXT: mfvsrwz r3, f2
+; CHECK-BE-NEXT: mffprwz r3, f2
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v3, r3
-; CHECK-BE-NEXT: mfvsrwz r3, f1
+; CHECK-BE-NEXT: mffprwz r3, f1
; CHECK-BE-NEXT: xxsldwi vs1, vs0, vs0, 3
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvspdpn f1, vs1
; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: xscvdpsxws f1, f1
-; CHECK-BE-NEXT: mfvsrwz r3, f1
+; CHECK-BE-NEXT: mffprwz r3, f1
; CHECK-BE-NEXT: xxswapd vs1, vs0
; CHECK-BE-NEXT: xscvspdpn f1, vs1
; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: vmrghh v2, v3, v2
; CHECK-BE-NEXT: mtvsrd v3, r3
-; CHECK-BE-NEXT: mfvsrwz r3, f1
+; CHECK-BE-NEXT: mffprwz r3, f1
; CHECK-BE-NEXT: xscvspdpn f1, vs0
; CHECK-BE-NEXT: xxsldwi vs0, vs0, vs0, 1
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: xscvdpsxws f0, f0
; CHECK-BE-NEXT: vmrghb v3, v4, v3
-; CHECK-BE-NEXT: mfvsrwz r3, f1
+; CHECK-BE-NEXT: mffprwz r3, f1
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v4, r3
-; CHECK-BE-NEXT: mfvsrwz r3, f0
+; CHECK-BE-NEXT: mffprwz r3, f0
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v5, r3
; CHECK-BE-NEXT: vmrghb v4, v4, v5
; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: xscvspdpn f6, vs6
; CHECK-P8-NEXT: xscvdpsxws f1, f1
-; CHECK-P8-NEXT: mfvsrwz r4, f2
+; CHECK-P8-NEXT: mffprwz r4, f2
; CHECK-P8-NEXT: xscvspdpn f7, vs7
-; CHECK-P8-NEXT: mtvsrd f2, r4
-; CHECK-P8-NEXT: mfvsrwz r4, f4
+; CHECK-P8-NEXT: mtfprd f2, r4
+; CHECK-P8-NEXT: mffprwz r4, f4
; CHECK-P8-NEXT: xscvdpsxws f3, f3
; CHECK-P8-NEXT: xscvspdpn f8, vs8
-; CHECK-P8-NEXT: mtvsrd f4, r4
-; CHECK-P8-NEXT: mfvsrwz r4, f0
+; CHECK-P8-NEXT: mtfprd f4, r4
+; CHECK-P8-NEXT: mffprwz r4, f0
; CHECK-P8-NEXT: xscvdpsxws f0, f5
; CHECK-P8-NEXT: xxswapd v0, vs4
; CHECK-P8-NEXT: xscvspdpn f9, vs9
-; CHECK-P8-NEXT: mtvsrd f5, r4
-; CHECK-P8-NEXT: mfvsrwz r4, f1
+; CHECK-P8-NEXT: mtfprd f5, r4
+; CHECK-P8-NEXT: mffprwz r4, f1
; CHECK-P8-NEXT: xscvdpsxws f1, f6
; CHECK-P8-NEXT: xxswapd v3, vs5
-; CHECK-P8-NEXT: mtvsrd f6, r4
-; CHECK-P8-NEXT: mfvsrwz r4, f3
+; CHECK-P8-NEXT: mtfprd f6, r4
+; CHECK-P8-NEXT: mffprwz r4, f3
; CHECK-P8-NEXT: xscvdpsxws f3, f7
; CHECK-P8-NEXT: xxswapd v4, vs6
-; CHECK-P8-NEXT: mtvsrd f7, r4
-; CHECK-P8-NEXT: mfvsrwz r4, f0
+; CHECK-P8-NEXT: mtfprd f7, r4
+; CHECK-P8-NEXT: mffprwz r4, f0
; CHECK-P8-NEXT: xscvdpsxws f0, f8
; CHECK-P8-NEXT: xxswapd v5, vs7
-; CHECK-P8-NEXT: mtvsrd f8, r4
-; CHECK-P8-NEXT: mfvsrwz r4, f1
+; CHECK-P8-NEXT: mtfprd f8, r4
+; CHECK-P8-NEXT: mffprwz r4, f1
; CHECK-P8-NEXT: xscvdpsxws f1, f9
; CHECK-P8-NEXT: xxswapd v1, vs8
-; CHECK-P8-NEXT: mtvsrd f9, r4
-; CHECK-P8-NEXT: mfvsrwz r4, f3
+; CHECK-P8-NEXT: mtfprd f9, r4
+; CHECK-P8-NEXT: mffprwz r4, f3
; CHECK-P8-NEXT: vmrglb v3, v4, v3
; CHECK-P8-NEXT: xxswapd v4, vs2
-; CHECK-P8-NEXT: mtvsrd f3, r4
+; CHECK-P8-NEXT: mtfprd f3, r4
; CHECK-P8-NEXT: xxswapd v6, vs9
-; CHECK-P8-NEXT: mfvsrwz r4, f0
+; CHECK-P8-NEXT: mffprwz r4, f0
; CHECK-P8-NEXT: xscvspdpn f0, v2
; CHECK-P8-NEXT: xxswapd v7, vs3
-; CHECK-P8-NEXT: mtvsrd f5, r4
-; CHECK-P8-NEXT: mfvsrwz r4, f1
+; CHECK-P8-NEXT: mtfprd f5, r4
+; CHECK-P8-NEXT: mffprwz r4, f1
; CHECK-P8-NEXT: vmrglb v4, v4, v5
; CHECK-P8-NEXT: xxswapd v5, vs5
-; CHECK-P8-NEXT: mtvsrd f1, r4
+; CHECK-P8-NEXT: mtfprd f1, r4
; CHECK-P8-NEXT: li r4, 48
; CHECK-P8-NEXT: lvx v9, r3, r4
; CHECK-P8-NEXT: vmrglb v1, v6, v1
; CHECK-P8-NEXT: xscvdpsxws f2, f2
; CHECK-P8-NEXT: xscvdpsxws f3, f3
; CHECK-P8-NEXT: xscvdpsxws f5, f5
-; CHECK-P8-NEXT: mfvsrwz r3, f0
-; CHECK-P8-NEXT: mfvsrwz r4, f4
-; CHECK-P8-NEXT: mtvsrd f0, r3
-; CHECK-P8-NEXT: mtvsrd f4, r4
-; CHECK-P8-NEXT: mfvsrwz r3, f1
-; CHECK-P8-NEXT: mfvsrwz r4, f2
+; CHECK-P8-NEXT: mffprwz r3, f0
+; CHECK-P8-NEXT: mffprwz r4, f4
+; CHECK-P8-NEXT: mtfprd f0, r3
+; CHECK-P8-NEXT: mtfprd f4, r4
+; CHECK-P8-NEXT: mffprwz r3, f1
+; CHECK-P8-NEXT: mffprwz r4, f2
; CHECK-P8-NEXT: xxswapd v9, vs4
-; CHECK-P8-NEXT: mtvsrd f1, r3
-; CHECK-P8-NEXT: mfvsrwz r3, f3
-; CHECK-P8-NEXT: mtvsrd f2, r4
+; CHECK-P8-NEXT: mtfprd f1, r3
+; CHECK-P8-NEXT: mffprwz r3, f3
+; CHECK-P8-NEXT: mtfprd f2, r4
; CHECK-P8-NEXT: xxswapd v6, vs1
-; CHECK-P8-NEXT: mfvsrwz r4, f5
+; CHECK-P8-NEXT: mffprwz r4, f5
; CHECK-P8-NEXT: vmrglb v2, v0, v7
; CHECK-P8-NEXT: xxswapd v0, vs0
-; CHECK-P8-NEXT: mtvsrd f0, r3
+; CHECK-P8-NEXT: mtfprd f0, r3
; CHECK-P8-NEXT: xxswapd v7, vs2
-; CHECK-P8-NEXT: mtvsrd f3, r4
+; CHECK-P8-NEXT: mtfprd f3, r4
; CHECK-P8-NEXT: vmrglb v5, v8, v5
; CHECK-P8-NEXT: xxswapd v8, vs0
; CHECK-P8-NEXT: xxswapd v10, vs3
; CHECK-P9-NEXT: lxv vs0, 48(r3)
; CHECK-P9-NEXT: lxv vs1, 32(r3)
; CHECK-P9-NEXT: lxv vs4, 16(r3)
-; CHECK-P9-NEXT: mfvsrwz r3, f3
-; CHECK-P9-NEXT: mtvsrd f3, r3
+; CHECK-P9-NEXT: mffprwz r3, f3
+; CHECK-P9-NEXT: mtfprd f3, r3
; CHECK-P9-NEXT: xxswapd v2, vs3
; CHECK-P9-NEXT: xxswapd vs3, vs2
; CHECK-P9-NEXT: xscvspdpn f3, vs3
; CHECK-P9-NEXT: xscvdpsxws f3, f3
-; CHECK-P9-NEXT: mfvsrwz r3, f3
-; CHECK-P9-NEXT: mtvsrd f3, r3
+; CHECK-P9-NEXT: mffprwz r3, f3
+; CHECK-P9-NEXT: mtfprd f3, r3
; CHECK-P9-NEXT: xxswapd v3, vs3
; CHECK-P9-NEXT: xscvspdpn f3, vs2
; CHECK-P9-NEXT: xxsldwi vs2, vs2, vs2, 1
; CHECK-P9-NEXT: xscvspdpn f2, vs2
; CHECK-P9-NEXT: xscvdpsxws f3, f3
; CHECK-P9-NEXT: xscvdpsxws f2, f2
-; CHECK-P9-NEXT: mfvsrwz r3, f3
-; CHECK-P9-NEXT: mtvsrd f3, r3
-; CHECK-P9-NEXT: mfvsrwz r3, f2
-; CHECK-P9-NEXT: mtvsrd f2, r3
+; CHECK-P9-NEXT: mffprwz r3, f3
+; CHECK-P9-NEXT: mtfprd f3, r3
+; CHECK-P9-NEXT: mffprwz r3, f2
+; CHECK-P9-NEXT: mtfprd f2, r3
; CHECK-P9-NEXT: xxswapd v4, vs2
; CHECK-P9-NEXT: xxsldwi vs2, vs4, vs4, 3
; CHECK-P9-NEXT: xscvspdpn f2, vs2
; CHECK-P9-NEXT: xxswapd v3, vs3
; CHECK-P9-NEXT: vmrglb v3, v3, v4
; CHECK-P9-NEXT: vmrglh v2, v3, v2
-; CHECK-P9-NEXT: mfvsrwz r3, f2
-; CHECK-P9-NEXT: mtvsrd f2, r3
+; CHECK-P9-NEXT: mffprwz r3, f2
+; CHECK-P9-NEXT: mtfprd f2, r3
; CHECK-P9-NEXT: xxswapd v3, vs2
; CHECK-P9-NEXT: xxswapd vs2, vs4
; CHECK-P9-NEXT: xscvspdpn f2, vs2
; CHECK-P9-NEXT: xscvdpsxws f2, f2
-; CHECK-P9-NEXT: mfvsrwz r3, f2
-; CHECK-P9-NEXT: mtvsrd f2, r3
+; CHECK-P9-NEXT: mffprwz r3, f2
+; CHECK-P9-NEXT: mtfprd f2, r3
; CHECK-P9-NEXT: xxswapd v4, vs2
; CHECK-P9-NEXT: xscvspdpn f2, vs4
; CHECK-P9-NEXT: xscvdpsxws f2, f2
-; CHECK-P9-NEXT: mfvsrwz r3, f2
-; CHECK-P9-NEXT: mtvsrd f2, r3
+; CHECK-P9-NEXT: mffprwz r3, f2
+; CHECK-P9-NEXT: mtfprd f2, r3
; CHECK-P9-NEXT: vmrglb v3, v4, v3
; CHECK-P9-NEXT: xxswapd v4, vs2
; CHECK-P9-NEXT: xxsldwi vs2, vs4, vs4, 1
; CHECK-P9-NEXT: xscvspdpn f2, vs2
; CHECK-P9-NEXT: xscvdpsxws f2, f2
-; CHECK-P9-NEXT: mfvsrwz r3, f2
-; CHECK-P9-NEXT: mtvsrd f2, r3
+; CHECK-P9-NEXT: mffprwz r3, f2
+; CHECK-P9-NEXT: mtfprd f2, r3
; CHECK-P9-NEXT: xxswapd v5, vs2
; CHECK-P9-NEXT: xxsldwi vs2, vs1, vs1, 3
; CHECK-P9-NEXT: xscvspdpn f2, vs2
; CHECK-P9-NEXT: vmrglb v4, v4, v5
; CHECK-P9-NEXT: vmrglh v3, v4, v3
; CHECK-P9-NEXT: vmrglw v2, v3, v2
-; CHECK-P9-NEXT: mfvsrwz r3, f2
-; CHECK-P9-NEXT: mtvsrd f2, r3
+; CHECK-P9-NEXT: mffprwz r3, f2
+; CHECK-P9-NEXT: mtfprd f2, r3
; CHECK-P9-NEXT: xxswapd v3, vs2
; CHECK-P9-NEXT: xxswapd vs2, vs1
; CHECK-P9-NEXT: xscvspdpn f2, vs2
; CHECK-P9-NEXT: xscvdpsxws f2, f2
-; CHECK-P9-NEXT: mfvsrwz r3, f2
-; CHECK-P9-NEXT: mtvsrd f2, r3
+; CHECK-P9-NEXT: mffprwz r3, f2
+; CHECK-P9-NEXT: mtfprd f2, r3
; CHECK-P9-NEXT: xxswapd v4, vs2
; CHECK-P9-NEXT: xscvspdpn f2, vs1
; CHECK-P9-NEXT: xxsldwi vs1, vs1, vs1, 1
; CHECK-P9-NEXT: xscvspdpn f1, vs1
; CHECK-P9-NEXT: xscvdpsxws f2, f2
; CHECK-P9-NEXT: xscvdpsxws f1, f1
-; CHECK-P9-NEXT: mfvsrwz r3, f2
-; CHECK-P9-NEXT: mtvsrd f2, r3
-; CHECK-P9-NEXT: mfvsrwz r3, f1
-; CHECK-P9-NEXT: mtvsrd f1, r3
+; CHECK-P9-NEXT: mffprwz r3, f2
+; CHECK-P9-NEXT: mtfprd f2, r3
+; CHECK-P9-NEXT: mffprwz r3, f1
+; CHECK-P9-NEXT: mtfprd f1, r3
; CHECK-P9-NEXT: xxswapd v5, vs1
; CHECK-P9-NEXT: xxsldwi vs1, vs0, vs0, 3
; CHECK-P9-NEXT: xscvspdpn f1, vs1
; CHECK-P9-NEXT: xxswapd v4, vs2
; CHECK-P9-NEXT: vmrglb v4, v4, v5
; CHECK-P9-NEXT: vmrglh v3, v4, v3
-; CHECK-P9-NEXT: mfvsrwz r3, f1
-; CHECK-P9-NEXT: mtvsrd f1, r3
+; CHECK-P9-NEXT: mffprwz r3, f1
+; CHECK-P9-NEXT: mtfprd f1, r3
; CHECK-P9-NEXT: xxswapd v4, vs1
; CHECK-P9-NEXT: xxswapd vs1, vs0
; CHECK-P9-NEXT: xscvspdpn f1, vs1
; CHECK-P9-NEXT: xscvdpsxws f1, f1
-; CHECK-P9-NEXT: mfvsrwz r3, f1
-; CHECK-P9-NEXT: mtvsrd f1, r3
+; CHECK-P9-NEXT: mffprwz r3, f1
+; CHECK-P9-NEXT: mtfprd f1, r3
; CHECK-P9-NEXT: xxswapd v5, vs1
; CHECK-P9-NEXT: xscvspdpn f1, vs0
; CHECK-P9-NEXT: xxsldwi vs0, vs0, vs0, 1
; CHECK-P9-NEXT: xscvspdpn f0, vs0
; CHECK-P9-NEXT: xscvdpsxws f1, f1
; CHECK-P9-NEXT: xscvdpsxws f0, f0
-; CHECK-P9-NEXT: mfvsrwz r3, f1
-; CHECK-P9-NEXT: mtvsrd f1, r3
-; CHECK-P9-NEXT: mfvsrwz r3, f0
-; CHECK-P9-NEXT: mtvsrd f0, r3
+; CHECK-P9-NEXT: mffprwz r3, f1
+; CHECK-P9-NEXT: mtfprd f1, r3
+; CHECK-P9-NEXT: mffprwz r3, f0
+; CHECK-P9-NEXT: mtfprd f0, r3
; CHECK-P9-NEXT: vmrglb v4, v5, v4
; CHECK-P9-NEXT: xxswapd v5, vs1
; CHECK-P9-NEXT: xxswapd v0, vs0
; CHECK-BE-NEXT: lxv vs0, 0(r3)
; CHECK-BE-NEXT: lxv vs1, 16(r3)
; CHECK-BE-NEXT: lxv vs2, 32(r3)
-; CHECK-BE-NEXT: mfvsrwz r3, f4
+; CHECK-BE-NEXT: mffprwz r3, f4
; CHECK-BE-NEXT: xxswapd vs4, vs3
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvspdpn f4, vs4
; CHECK-BE-NEXT: mtvsrd v2, r3
; CHECK-BE-NEXT: xscvdpsxws f4, f4
-; CHECK-BE-NEXT: mfvsrwz r3, f4
+; CHECK-BE-NEXT: mffprwz r3, f4
; CHECK-BE-NEXT: xscvspdpn f4, vs3
; CHECK-BE-NEXT: xxsldwi vs3, vs3, vs3, 1
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: xscvdpsxws f3, f3
; CHECK-BE-NEXT: vmrghb v2, v3, v2
-; CHECK-BE-NEXT: mfvsrwz r3, f4
+; CHECK-BE-NEXT: mffprwz r3, f4
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v3, r3
-; CHECK-BE-NEXT: mfvsrwz r3, f3
+; CHECK-BE-NEXT: mffprwz r3, f3
; CHECK-BE-NEXT: xxsldwi vs3, vs2, vs2, 3
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvspdpn f3, vs3
; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: xscvdpsxws f3, f3
-; CHECK-BE-NEXT: mfvsrwz r3, f3
+; CHECK-BE-NEXT: mffprwz r3, f3
; CHECK-BE-NEXT: xxswapd vs3, vs2
; CHECK-BE-NEXT: xscvspdpn f3, vs3
; CHECK-BE-NEXT: xscvdpsxws f3, f3
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: vmrghh v2, v3, v2
; CHECK-BE-NEXT: mtvsrd v3, r3
-; CHECK-BE-NEXT: mfvsrwz r3, f3
+; CHECK-BE-NEXT: mffprwz r3, f3
; CHECK-BE-NEXT: xscvspdpn f3, vs2
; CHECK-BE-NEXT: xxsldwi vs2, vs2, vs2, 1
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: xscvdpsxws f2, f2
; CHECK-BE-NEXT: vmrghb v3, v4, v3
-; CHECK-BE-NEXT: mfvsrwz r3, f3
+; CHECK-BE-NEXT: mffprwz r3, f3
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v4, r3
-; CHECK-BE-NEXT: mfvsrwz r3, f2
+; CHECK-BE-NEXT: mffprwz r3, f2
; CHECK-BE-NEXT: xxsldwi vs2, vs1, vs1, 3
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvspdpn f2, vs2
; CHECK-BE-NEXT: mtvsrd v5, r3
; CHECK-BE-NEXT: xscvdpsxws f2, f2
-; CHECK-BE-NEXT: mfvsrwz r3, f2
+; CHECK-BE-NEXT: mffprwz r3, f2
; CHECK-BE-NEXT: xxswapd vs2, vs1
; CHECK-BE-NEXT: xscvspdpn f2, vs2
; CHECK-BE-NEXT: xscvdpsxws f2, f2
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: vmrghw v2, v3, v2
; CHECK-BE-NEXT: mtvsrd v3, r3
-; CHECK-BE-NEXT: mfvsrwz r3, f2
+; CHECK-BE-NEXT: mffprwz r3, f2
; CHECK-BE-NEXT: xscvspdpn f2, vs1
; CHECK-BE-NEXT: xxsldwi vs1, vs1, vs1, 1
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: vmrghb v3, v4, v3
-; CHECK-BE-NEXT: mfvsrwz r3, f2
+; CHECK-BE-NEXT: mffprwz r3, f2
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v4, r3
-; CHECK-BE-NEXT: mfvsrwz r3, f1
+; CHECK-BE-NEXT: mffprwz r3, f1
; CHECK-BE-NEXT: xxsldwi vs1, vs0, vs0, 3
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvspdpn f1, vs1
; CHECK-BE-NEXT: mtvsrd v5, r3
; CHECK-BE-NEXT: xscvdpsxws f1, f1
-; CHECK-BE-NEXT: mfvsrwz r3, f1
+; CHECK-BE-NEXT: mffprwz r3, f1
; CHECK-BE-NEXT: xxswapd vs1, vs0
; CHECK-BE-NEXT: xscvspdpn f1, vs1
; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: vmrghh v3, v4, v3
; CHECK-BE-NEXT: mtvsrd v4, r3
-; CHECK-BE-NEXT: mfvsrwz r3, f1
+; CHECK-BE-NEXT: mffprwz r3, f1
; CHECK-BE-NEXT: xscvspdpn f1, vs0
; CHECK-BE-NEXT: xxsldwi vs0, vs0, vs0, 1
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v5, r3
; CHECK-BE-NEXT: xscvdpsxws f0, f0
; CHECK-BE-NEXT: vmrghb v4, v5, v4
-; CHECK-BE-NEXT: mfvsrwz r3, f1
+; CHECK-BE-NEXT: mffprwz r3, f1
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v5, r3
-; CHECK-BE-NEXT: mfvsrwz r3, f0
+; CHECK-BE-NEXT: mffprwz r3, f0
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v0, r3
; CHECK-BE-NEXT: vmrghb v5, v5, v0
define i16 @test2elt_signed(i64 %a.coerce) local_unnamed_addr #0 {
; CHECK-P8-LABEL: test2elt_signed:
; CHECK-P8: # %bb.0: # %entry
-; CHECK-P8-NEXT: mtvsrd f0, r3
+; CHECK-P8-NEXT: mtfprd f0, r3
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: xscvspdpn f0, vs0
; CHECK-P8-NEXT: xxsldwi vs1, v2, v2, 3
; CHECK-P8-NEXT: xscvspdpn f1, vs1
; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: xscvdpsxws f1, f1
-; CHECK-P8-NEXT: mfvsrwz r4, f0
-; CHECK-P8-NEXT: mfvsrwz r3, f1
-; CHECK-P8-NEXT: mtvsrd f1, r4
-; CHECK-P8-NEXT: mtvsrd f0, r3
+; CHECK-P8-NEXT: mffprwz r4, f0
+; CHECK-P8-NEXT: mffprwz r3, f1
+; CHECK-P8-NEXT: mtfprd f1, r4
+; CHECK-P8-NEXT: mtfprd f0, r3
; CHECK-P8-NEXT: xxswapd v3, vs1
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: vmrglb v2, v3, v2
; CHECK-P8-NEXT: xxswapd vs0, v2
-; CHECK-P8-NEXT: mfvsrd r3, f0
+; CHECK-P8-NEXT: mffprd r3, f0
; CHECK-P8-NEXT: clrldi r3, r3, 48
; CHECK-P8-NEXT: sth r3, -2(r1)
; CHECK-P8-NEXT: lhz r3, -2(r1)
;
; CHECK-P9-LABEL: test2elt_signed:
; CHECK-P9: # %bb.0: # %entry
-; CHECK-P9-NEXT: mtvsrd f0, r3
+; CHECK-P9-NEXT: mtfprd f0, r3
; CHECK-P9-NEXT: xxswapd v2, vs0
; CHECK-P9-NEXT: xscvspdpn f0, vs0
; CHECK-P9-NEXT: xxsldwi vs1, v2, v2, 3
; CHECK-P9-NEXT: xscvspdpn f1, vs1
; CHECK-P9-NEXT: xscvdpsxws f1, f1
; CHECK-P9-NEXT: xscvdpsxws f0, f0
-; CHECK-P9-NEXT: mfvsrwz r3, f1
-; CHECK-P9-NEXT: mtvsrd f1, r3
-; CHECK-P9-NEXT: mfvsrwz r3, f0
-; CHECK-P9-NEXT: mtvsrd f0, r3
+; CHECK-P9-NEXT: mffprwz r3, f1
+; CHECK-P9-NEXT: mtfprd f1, r3
+; CHECK-P9-NEXT: mffprwz r3, f0
+; CHECK-P9-NEXT: mtfprd f0, r3
; CHECK-P9-NEXT: xxswapd v2, vs1
; CHECK-P9-NEXT: xxswapd v3, vs0
; CHECK-P9-NEXT: vmrglb v2, v3, v2
;
; CHECK-BE-LABEL: test2elt_signed:
; CHECK-BE: # %bb.0: # %entry
-; CHECK-BE-NEXT: mtvsrd f0, r3
+; CHECK-BE-NEXT: mtfprd f0, r3
; CHECK-BE-NEXT: xscvspdpn f1, vs0
; CHECK-BE-NEXT: xxsldwi vs0, vs0, vs0, 1
; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: xscvspdpn f0, vs0
; CHECK-BE-NEXT: xscvdpsxws f0, f0
-; CHECK-BE-NEXT: mfvsrwz r3, f1
+; CHECK-BE-NEXT: mffprwz r3, f1
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v2, r3
-; CHECK-BE-NEXT: mfvsrwz r3, f0
+; CHECK-BE-NEXT: mffprwz r3, f0
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: addi r3, r1, -2
; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: xscvdpsxws f2, f2
; CHECK-P8-NEXT: xscvdpsxws f3, f3
-; CHECK-P8-NEXT: mfvsrwz r3, f1
-; CHECK-P8-NEXT: mtvsrd f1, r3
-; CHECK-P8-NEXT: mfvsrwz r3, f0
-; CHECK-P8-NEXT: mfvsrwz r4, f2
+; CHECK-P8-NEXT: mffprwz r3, f1
+; CHECK-P8-NEXT: mtfprd f1, r3
+; CHECK-P8-NEXT: mffprwz r3, f0
+; CHECK-P8-NEXT: mffprwz r4, f2
; CHECK-P8-NEXT: xxswapd v4, vs1
-; CHECK-P8-NEXT: mtvsrd f0, r3
-; CHECK-P8-NEXT: mfvsrwz r3, f3
-; CHECK-P8-NEXT: mtvsrd f2, r4
+; CHECK-P8-NEXT: mtfprd f0, r3
+; CHECK-P8-NEXT: mffprwz r3, f3
+; CHECK-P8-NEXT: mtfprd f2, r4
; CHECK-P8-NEXT: xxswapd v2, vs0
-; CHECK-P8-NEXT: mtvsrd f3, r3
+; CHECK-P8-NEXT: mtfprd f3, r3
; CHECK-P8-NEXT: xxswapd v3, vs2
; CHECK-P8-NEXT: xxswapd v5, vs3
; CHECK-P8-NEXT: vmrglb v2, v3, v2
; CHECK-P8-NEXT: vmrglb v3, v4, v5
; CHECK-P8-NEXT: vmrglh v2, v3, v2
; CHECK-P8-NEXT: xxswapd vs0, v2
-; CHECK-P8-NEXT: mfvsrwz r3, f0
+; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: blr
;
; CHECK-P9-LABEL: test4elt_signed:
; CHECK-P9-NEXT: xxsldwi vs0, v2, v2, 3
; CHECK-P9-NEXT: xscvspdpn f0, vs0
; CHECK-P9-NEXT: xscvdpsxws f0, f0
-; CHECK-P9-NEXT: mfvsrwz r3, f0
-; CHECK-P9-NEXT: mtvsrd f0, r3
+; CHECK-P9-NEXT: mffprwz r3, f0
+; CHECK-P9-NEXT: mtfprd f0, r3
; CHECK-P9-NEXT: xxswapd v3, vs0
; CHECK-P9-NEXT: xxswapd vs0, v2
; CHECK-P9-NEXT: xscvspdpn f0, vs0
; CHECK-P9-NEXT: xscvdpsxws f0, f0
-; CHECK-P9-NEXT: mfvsrwz r3, f0
-; CHECK-P9-NEXT: mtvsrd f0, r3
+; CHECK-P9-NEXT: mffprwz r3, f0
+; CHECK-P9-NEXT: mtfprd f0, r3
; CHECK-P9-NEXT: xxswapd v4, vs0
; CHECK-P9-NEXT: xscvspdpn f0, v2
; CHECK-P9-NEXT: xscvdpsxws f0, f0
-; CHECK-P9-NEXT: mfvsrwz r3, f0
-; CHECK-P9-NEXT: mtvsrd f0, r3
+; CHECK-P9-NEXT: mffprwz r3, f0
+; CHECK-P9-NEXT: mtfprd f0, r3
; CHECK-P9-NEXT: vmrglb v3, v4, v3
; CHECK-P9-NEXT: xxswapd v4, vs0
; CHECK-P9-NEXT: xxsldwi vs0, v2, v2, 1
; CHECK-P9-NEXT: xscvspdpn f0, vs0
; CHECK-P9-NEXT: xscvdpsxws f0, f0
-; CHECK-P9-NEXT: mfvsrwz r3, f0
-; CHECK-P9-NEXT: mtvsrd f0, r3
+; CHECK-P9-NEXT: mffprwz r3, f0
+; CHECK-P9-NEXT: mtfprd f0, r3
; CHECK-P9-NEXT: li r3, 0
; CHECK-P9-NEXT: xxswapd v2, vs0
; CHECK-P9-NEXT: vmrglb v2, v4, v2
; CHECK-BE-NEXT: xxsldwi vs0, v2, v2, 3
; CHECK-BE-NEXT: xscvspdpn f0, vs0
; CHECK-BE-NEXT: xscvdpsxws f0, f0
-; CHECK-BE-NEXT: mfvsrwz r3, f0
+; CHECK-BE-NEXT: mffprwz r3, f0
; CHECK-BE-NEXT: xxswapd vs0, v2
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvspdpn f0, vs0
; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: xscvdpsxws f0, f0
-; CHECK-BE-NEXT: mfvsrwz r3, f0
+; CHECK-BE-NEXT: mffprwz r3, f0
; CHECK-BE-NEXT: xscvspdpn f0, v2
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvdpsxws f0, f0
; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: vmrghb v3, v4, v3
-; CHECK-BE-NEXT: mfvsrwz r3, f0
+; CHECK-BE-NEXT: mffprwz r3, f0
; CHECK-BE-NEXT: xxsldwi vs0, v2, v2, 1
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvspdpn f0, vs0
; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: xscvdpsxws f0, f0
-; CHECK-BE-NEXT: mfvsrwz r3, f0
+; CHECK-BE-NEXT: mffprwz r3, f0
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v2, r3
; CHECK-BE-NEXT: li r3, 0
; CHECK-P8-NEXT: xscvdpsxws f2, f2
; CHECK-P8-NEXT: xscvdpsxws f3, f3
; CHECK-P8-NEXT: xscvdpsxws f5, f5
-; CHECK-P8-NEXT: mfvsrwz r4, f4
-; CHECK-P8-NEXT: mfvsrwz r6, f1
-; CHECK-P8-NEXT: mfvsrwz r5, f0
-; CHECK-P8-NEXT: mtvsrd f1, r6
-; CHECK-P8-NEXT: mtvsrd f0, r5
+; CHECK-P8-NEXT: mffprwz r4, f4
+; CHECK-P8-NEXT: mffprwz r6, f1
+; CHECK-P8-NEXT: mffprwz r5, f0
+; CHECK-P8-NEXT: mtfprd f1, r6
+; CHECK-P8-NEXT: mtfprd f0, r5
; CHECK-P8-NEXT: xxswapd v4, vs1
; CHECK-P8-NEXT: xxsldwi vs1, v2, v2, 1
; CHECK-P8-NEXT: xxswapd v3, vs0
; CHECK-P8-NEXT: xscvspdpn f0, v2
-; CHECK-P8-NEXT: mtvsrd f4, r4
+; CHECK-P8-NEXT: mtfprd f4, r4
; CHECK-P8-NEXT: xscvspdpn f1, vs1
-; CHECK-P8-NEXT: mfvsrwz r4, f2
+; CHECK-P8-NEXT: mffprwz r4, f2
; CHECK-P8-NEXT: xxswapd v1, vs4
; CHECK-P8-NEXT: vmrglb v2, v4, v3
-; CHECK-P8-NEXT: mtvsrd f2, r4
+; CHECK-P8-NEXT: mtfprd f2, r4
; CHECK-P8-NEXT: xscvdpsxws f0, f0
-; CHECK-P8-NEXT: mfvsrwz r4, f5
+; CHECK-P8-NEXT: mffprwz r4, f5
; CHECK-P8-NEXT: xxswapd v5, vs2
; CHECK-P8-NEXT: xscvdpsxws f1, f1
-; CHECK-P8-NEXT: mfvsrwz r3, f0
-; CHECK-P8-NEXT: mtvsrd f0, r3
-; CHECK-P8-NEXT: mfvsrwz r3, f1
+; CHECK-P8-NEXT: mffprwz r3, f0
+; CHECK-P8-NEXT: mtfprd f0, r3
+; CHECK-P8-NEXT: mffprwz r3, f1
; CHECK-P8-NEXT: xxswapd v3, vs0
-; CHECK-P8-NEXT: mtvsrd f1, r3
-; CHECK-P8-NEXT: mfvsrwz r3, f3
-; CHECK-P8-NEXT: mtvsrd f3, r4
+; CHECK-P8-NEXT: mtfprd f1, r3
+; CHECK-P8-NEXT: mffprwz r3, f3
+; CHECK-P8-NEXT: mtfprd f3, r4
; CHECK-P8-NEXT: xxswapd v4, vs1
-; CHECK-P8-NEXT: mtvsrd f0, r3
+; CHECK-P8-NEXT: mtfprd f0, r3
; CHECK-P8-NEXT: xxswapd v6, vs3
; CHECK-P8-NEXT: xxswapd v0, vs0
; CHECK-P8-NEXT: vmrglb v3, v3, v4
; CHECK-P8-NEXT: vmrglh v3, v5, v4
; CHECK-P8-NEXT: vmrglw v2, v3, v2
; CHECK-P8-NEXT: xxswapd vs0, v2
-; CHECK-P8-NEXT: mfvsrd r3, f0
+; CHECK-P8-NEXT: mffprd r3, f0
; CHECK-P8-NEXT: blr
;
; CHECK-P9-LABEL: test8elt_signed:
; CHECK-P9-NEXT: xscvspdpn f2, vs2
; CHECK-P9-NEXT: xscvdpsxws f2, f2
; CHECK-P9-NEXT: lxv vs0, 16(r3)
-; CHECK-P9-NEXT: mfvsrwz r3, f2
-; CHECK-P9-NEXT: mtvsrd f2, r3
+; CHECK-P9-NEXT: mffprwz r3, f2
+; CHECK-P9-NEXT: mtfprd f2, r3
; CHECK-P9-NEXT: xxswapd v2, vs2
; CHECK-P9-NEXT: xxswapd vs2, vs1
; CHECK-P9-NEXT: xscvspdpn f2, vs2
; CHECK-P9-NEXT: xscvdpsxws f2, f2
-; CHECK-P9-NEXT: mfvsrwz r3, f2
-; CHECK-P9-NEXT: mtvsrd f2, r3
+; CHECK-P9-NEXT: mffprwz r3, f2
+; CHECK-P9-NEXT: mtfprd f2, r3
; CHECK-P9-NEXT: xxswapd v3, vs2
; CHECK-P9-NEXT: xscvspdpn f2, vs1
; CHECK-P9-NEXT: xxsldwi vs1, vs1, vs1, 1
; CHECK-P9-NEXT: xscvspdpn f1, vs1
; CHECK-P9-NEXT: xscvdpsxws f2, f2
; CHECK-P9-NEXT: xscvdpsxws f1, f1
-; CHECK-P9-NEXT: mfvsrwz r3, f2
-; CHECK-P9-NEXT: mtvsrd f2, r3
-; CHECK-P9-NEXT: mfvsrwz r3, f1
-; CHECK-P9-NEXT: mtvsrd f1, r3
+; CHECK-P9-NEXT: mffprwz r3, f2
+; CHECK-P9-NEXT: mtfprd f2, r3
+; CHECK-P9-NEXT: mffprwz r3, f1
+; CHECK-P9-NEXT: mtfprd f1, r3
; CHECK-P9-NEXT: xxswapd v4, vs1
; CHECK-P9-NEXT: xxsldwi vs1, vs0, vs0, 3
; CHECK-P9-NEXT: xscvspdpn f1, vs1
; CHECK-P9-NEXT: xxswapd v3, vs2
; CHECK-P9-NEXT: vmrglb v3, v3, v4
; CHECK-P9-NEXT: vmrglh v2, v3, v2
-; CHECK-P9-NEXT: mfvsrwz r3, f1
-; CHECK-P9-NEXT: mtvsrd f1, r3
+; CHECK-P9-NEXT: mffprwz r3, f1
+; CHECK-P9-NEXT: mtfprd f1, r3
; CHECK-P9-NEXT: xxswapd v3, vs1
; CHECK-P9-NEXT: xxswapd vs1, vs0
; CHECK-P9-NEXT: xscvspdpn f1, vs1
; CHECK-P9-NEXT: xscvdpsxws f1, f1
-; CHECK-P9-NEXT: mfvsrwz r3, f1
-; CHECK-P9-NEXT: mtvsrd f1, r3
+; CHECK-P9-NEXT: mffprwz r3, f1
+; CHECK-P9-NEXT: mtfprd f1, r3
; CHECK-P9-NEXT: xxswapd v4, vs1
; CHECK-P9-NEXT: xscvspdpn f1, vs0
; CHECK-P9-NEXT: xxsldwi vs0, vs0, vs0, 1
; CHECK-P9-NEXT: xscvspdpn f0, vs0
; CHECK-P9-NEXT: xscvdpsxws f1, f1
; CHECK-P9-NEXT: xscvdpsxws f0, f0
-; CHECK-P9-NEXT: mfvsrwz r3, f1
-; CHECK-P9-NEXT: mtvsrd f1, r3
-; CHECK-P9-NEXT: mfvsrwz r3, f0
-; CHECK-P9-NEXT: mtvsrd f0, r3
+; CHECK-P9-NEXT: mffprwz r3, f1
+; CHECK-P9-NEXT: mtfprd f1, r3
+; CHECK-P9-NEXT: mffprwz r3, f0
+; CHECK-P9-NEXT: mtfprd f0, r3
; CHECK-P9-NEXT: vmrglb v3, v4, v3
; CHECK-P9-NEXT: xxswapd v4, vs1
; CHECK-P9-NEXT: xxswapd v5, vs0
; CHECK-BE-NEXT: xscvspdpn f2, vs2
; CHECK-BE-NEXT: xscvdpsxws f2, f2
; CHECK-BE-NEXT: lxv vs0, 0(r3)
-; CHECK-BE-NEXT: mfvsrwz r3, f2
+; CHECK-BE-NEXT: mffprwz r3, f2
; CHECK-BE-NEXT: xxswapd vs2, vs1
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvspdpn f2, vs2
; CHECK-BE-NEXT: mtvsrd v2, r3
; CHECK-BE-NEXT: xscvdpsxws f2, f2
-; CHECK-BE-NEXT: mfvsrwz r3, f2
+; CHECK-BE-NEXT: mffprwz r3, f2
; CHECK-BE-NEXT: xscvspdpn f2, vs1
; CHECK-BE-NEXT: xxsldwi vs1, vs1, vs1, 1
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: vmrghb v2, v3, v2
-; CHECK-BE-NEXT: mfvsrwz r3, f2
+; CHECK-BE-NEXT: mffprwz r3, f2
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v3, r3
-; CHECK-BE-NEXT: mfvsrwz r3, f1
+; CHECK-BE-NEXT: mffprwz r3, f1
; CHECK-BE-NEXT: xxsldwi vs1, vs0, vs0, 3
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvspdpn f1, vs1
; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: xscvdpsxws f1, f1
-; CHECK-BE-NEXT: mfvsrwz r3, f1
+; CHECK-BE-NEXT: mffprwz r3, f1
; CHECK-BE-NEXT: xxswapd vs1, vs0
; CHECK-BE-NEXT: xscvspdpn f1, vs1
; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: vmrghh v2, v3, v2
; CHECK-BE-NEXT: mtvsrd v3, r3
-; CHECK-BE-NEXT: mfvsrwz r3, f1
+; CHECK-BE-NEXT: mffprwz r3, f1
; CHECK-BE-NEXT: xscvspdpn f1, vs0
; CHECK-BE-NEXT: xxsldwi vs0, vs0, vs0, 1
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: xscvdpsxws f0, f0
; CHECK-BE-NEXT: vmrghb v3, v4, v3
-; CHECK-BE-NEXT: mfvsrwz r3, f1
+; CHECK-BE-NEXT: mffprwz r3, f1
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v4, r3
-; CHECK-BE-NEXT: mfvsrwz r3, f0
+; CHECK-BE-NEXT: mffprwz r3, f0
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v5, r3
; CHECK-BE-NEXT: vmrghb v4, v4, v5
; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: xscvspdpn f6, vs6
; CHECK-P8-NEXT: xscvdpsxws f1, f1
-; CHECK-P8-NEXT: mfvsrwz r4, f2
+; CHECK-P8-NEXT: mffprwz r4, f2
; CHECK-P8-NEXT: xscvspdpn f7, vs7
-; CHECK-P8-NEXT: mtvsrd f2, r4
-; CHECK-P8-NEXT: mfvsrwz r4, f4
+; CHECK-P8-NEXT: mtfprd f2, r4
+; CHECK-P8-NEXT: mffprwz r4, f4
; CHECK-P8-NEXT: xscvdpsxws f3, f3
; CHECK-P8-NEXT: xscvspdpn f8, vs8
-; CHECK-P8-NEXT: mtvsrd f4, r4
-; CHECK-P8-NEXT: mfvsrwz r4, f0
+; CHECK-P8-NEXT: mtfprd f4, r4
+; CHECK-P8-NEXT: mffprwz r4, f0
; CHECK-P8-NEXT: xscvdpsxws f0, f5
; CHECK-P8-NEXT: xxswapd v0, vs4
; CHECK-P8-NEXT: xscvspdpn f9, vs9
-; CHECK-P8-NEXT: mtvsrd f5, r4
-; CHECK-P8-NEXT: mfvsrwz r4, f1
+; CHECK-P8-NEXT: mtfprd f5, r4
+; CHECK-P8-NEXT: mffprwz r4, f1
; CHECK-P8-NEXT: xscvdpsxws f1, f6
; CHECK-P8-NEXT: xxswapd v3, vs5
-; CHECK-P8-NEXT: mtvsrd f6, r4
-; CHECK-P8-NEXT: mfvsrwz r4, f3
+; CHECK-P8-NEXT: mtfprd f6, r4
+; CHECK-P8-NEXT: mffprwz r4, f3
; CHECK-P8-NEXT: xscvdpsxws f3, f7
; CHECK-P8-NEXT: xxswapd v4, vs6
-; CHECK-P8-NEXT: mtvsrd f7, r4
-; CHECK-P8-NEXT: mfvsrwz r4, f0
+; CHECK-P8-NEXT: mtfprd f7, r4
+; CHECK-P8-NEXT: mffprwz r4, f0
; CHECK-P8-NEXT: xscvdpsxws f0, f8
; CHECK-P8-NEXT: xxswapd v5, vs7
-; CHECK-P8-NEXT: mtvsrd f8, r4
-; CHECK-P8-NEXT: mfvsrwz r4, f1
+; CHECK-P8-NEXT: mtfprd f8, r4
+; CHECK-P8-NEXT: mffprwz r4, f1
; CHECK-P8-NEXT: xscvdpsxws f1, f9
; CHECK-P8-NEXT: xxswapd v1, vs8
-; CHECK-P8-NEXT: mtvsrd f9, r4
-; CHECK-P8-NEXT: mfvsrwz r4, f3
+; CHECK-P8-NEXT: mtfprd f9, r4
+; CHECK-P8-NEXT: mffprwz r4, f3
; CHECK-P8-NEXT: vmrglb v3, v4, v3
; CHECK-P8-NEXT: xxswapd v4, vs2
-; CHECK-P8-NEXT: mtvsrd f3, r4
+; CHECK-P8-NEXT: mtfprd f3, r4
; CHECK-P8-NEXT: xxswapd v6, vs9
-; CHECK-P8-NEXT: mfvsrwz r4, f0
+; CHECK-P8-NEXT: mffprwz r4, f0
; CHECK-P8-NEXT: xscvspdpn f0, v2
; CHECK-P8-NEXT: xxswapd v7, vs3
-; CHECK-P8-NEXT: mtvsrd f5, r4
-; CHECK-P8-NEXT: mfvsrwz r4, f1
+; CHECK-P8-NEXT: mtfprd f5, r4
+; CHECK-P8-NEXT: mffprwz r4, f1
; CHECK-P8-NEXT: vmrglb v4, v4, v5
; CHECK-P8-NEXT: xxswapd v5, vs5
-; CHECK-P8-NEXT: mtvsrd f1, r4
+; CHECK-P8-NEXT: mtfprd f1, r4
; CHECK-P8-NEXT: li r4, 48
; CHECK-P8-NEXT: lvx v9, r3, r4
; CHECK-P8-NEXT: vmrglb v1, v6, v1
; CHECK-P8-NEXT: xscvdpsxws f2, f2
; CHECK-P8-NEXT: xscvdpsxws f3, f3
; CHECK-P8-NEXT: xscvdpsxws f5, f5
-; CHECK-P8-NEXT: mfvsrwz r3, f0
-; CHECK-P8-NEXT: mfvsrwz r4, f4
-; CHECK-P8-NEXT: mtvsrd f0, r3
-; CHECK-P8-NEXT: mtvsrd f4, r4
-; CHECK-P8-NEXT: mfvsrwz r3, f1
-; CHECK-P8-NEXT: mfvsrwz r4, f2
+; CHECK-P8-NEXT: mffprwz r3, f0
+; CHECK-P8-NEXT: mffprwz r4, f4
+; CHECK-P8-NEXT: mtfprd f0, r3
+; CHECK-P8-NEXT: mtfprd f4, r4
+; CHECK-P8-NEXT: mffprwz r3, f1
+; CHECK-P8-NEXT: mffprwz r4, f2
; CHECK-P8-NEXT: xxswapd v9, vs4
-; CHECK-P8-NEXT: mtvsrd f1, r3
-; CHECK-P8-NEXT: mfvsrwz r3, f3
-; CHECK-P8-NEXT: mtvsrd f2, r4
+; CHECK-P8-NEXT: mtfprd f1, r3
+; CHECK-P8-NEXT: mffprwz r3, f3
+; CHECK-P8-NEXT: mtfprd f2, r4
; CHECK-P8-NEXT: xxswapd v6, vs1
-; CHECK-P8-NEXT: mfvsrwz r4, f5
+; CHECK-P8-NEXT: mffprwz r4, f5
; CHECK-P8-NEXT: vmrglb v2, v0, v7
; CHECK-P8-NEXT: xxswapd v0, vs0
-; CHECK-P8-NEXT: mtvsrd f0, r3
+; CHECK-P8-NEXT: mtfprd f0, r3
; CHECK-P8-NEXT: xxswapd v7, vs2
-; CHECK-P8-NEXT: mtvsrd f3, r4
+; CHECK-P8-NEXT: mtfprd f3, r4
; CHECK-P8-NEXT: vmrglb v5, v8, v5
; CHECK-P8-NEXT: xxswapd v8, vs0
; CHECK-P8-NEXT: xxswapd v10, vs3
; CHECK-P9-NEXT: lxv vs0, 48(r3)
; CHECK-P9-NEXT: lxv vs1, 32(r3)
; CHECK-P9-NEXT: lxv vs4, 16(r3)
-; CHECK-P9-NEXT: mfvsrwz r3, f3
-; CHECK-P9-NEXT: mtvsrd f3, r3
+; CHECK-P9-NEXT: mffprwz r3, f3
+; CHECK-P9-NEXT: mtfprd f3, r3
; CHECK-P9-NEXT: xxswapd v2, vs3
; CHECK-P9-NEXT: xxswapd vs3, vs2
; CHECK-P9-NEXT: xscvspdpn f3, vs3
; CHECK-P9-NEXT: xscvdpsxws f3, f3
-; CHECK-P9-NEXT: mfvsrwz r3, f3
-; CHECK-P9-NEXT: mtvsrd f3, r3
+; CHECK-P9-NEXT: mffprwz r3, f3
+; CHECK-P9-NEXT: mtfprd f3, r3
; CHECK-P9-NEXT: xxswapd v3, vs3
; CHECK-P9-NEXT: xscvspdpn f3, vs2
; CHECK-P9-NEXT: xxsldwi vs2, vs2, vs2, 1
; CHECK-P9-NEXT: xscvspdpn f2, vs2
; CHECK-P9-NEXT: xscvdpsxws f3, f3
; CHECK-P9-NEXT: xscvdpsxws f2, f2
-; CHECK-P9-NEXT: mfvsrwz r3, f3
-; CHECK-P9-NEXT: mtvsrd f3, r3
-; CHECK-P9-NEXT: mfvsrwz r3, f2
-; CHECK-P9-NEXT: mtvsrd f2, r3
+; CHECK-P9-NEXT: mffprwz r3, f3
+; CHECK-P9-NEXT: mtfprd f3, r3
+; CHECK-P9-NEXT: mffprwz r3, f2
+; CHECK-P9-NEXT: mtfprd f2, r3
; CHECK-P9-NEXT: xxswapd v4, vs2
; CHECK-P9-NEXT: xxsldwi vs2, vs4, vs4, 3
; CHECK-P9-NEXT: xscvspdpn f2, vs2
; CHECK-P9-NEXT: xxswapd v3, vs3
; CHECK-P9-NEXT: vmrglb v3, v3, v4
; CHECK-P9-NEXT: vmrglh v2, v3, v2
-; CHECK-P9-NEXT: mfvsrwz r3, f2
-; CHECK-P9-NEXT: mtvsrd f2, r3
+; CHECK-P9-NEXT: mffprwz r3, f2
+; CHECK-P9-NEXT: mtfprd f2, r3
; CHECK-P9-NEXT: xxswapd v3, vs2
; CHECK-P9-NEXT: xxswapd vs2, vs4
; CHECK-P9-NEXT: xscvspdpn f2, vs2
; CHECK-P9-NEXT: xscvdpsxws f2, f2
-; CHECK-P9-NEXT: mfvsrwz r3, f2
-; CHECK-P9-NEXT: mtvsrd f2, r3
+; CHECK-P9-NEXT: mffprwz r3, f2
+; CHECK-P9-NEXT: mtfprd f2, r3
; CHECK-P9-NEXT: xxswapd v4, vs2
; CHECK-P9-NEXT: xscvspdpn f2, vs4
; CHECK-P9-NEXT: xscvdpsxws f2, f2
-; CHECK-P9-NEXT: mfvsrwz r3, f2
-; CHECK-P9-NEXT: mtvsrd f2, r3
+; CHECK-P9-NEXT: mffprwz r3, f2
+; CHECK-P9-NEXT: mtfprd f2, r3
; CHECK-P9-NEXT: vmrglb v3, v4, v3
; CHECK-P9-NEXT: xxswapd v4, vs2
; CHECK-P9-NEXT: xxsldwi vs2, vs4, vs4, 1
; CHECK-P9-NEXT: xscvspdpn f2, vs2
; CHECK-P9-NEXT: xscvdpsxws f2, f2
-; CHECK-P9-NEXT: mfvsrwz r3, f2
-; CHECK-P9-NEXT: mtvsrd f2, r3
+; CHECK-P9-NEXT: mffprwz r3, f2
+; CHECK-P9-NEXT: mtfprd f2, r3
; CHECK-P9-NEXT: xxswapd v5, vs2
; CHECK-P9-NEXT: xxsldwi vs2, vs1, vs1, 3
; CHECK-P9-NEXT: xscvspdpn f2, vs2
; CHECK-P9-NEXT: vmrglb v4, v4, v5
; CHECK-P9-NEXT: vmrglh v3, v4, v3
; CHECK-P9-NEXT: vmrglw v2, v3, v2
-; CHECK-P9-NEXT: mfvsrwz r3, f2
-; CHECK-P9-NEXT: mtvsrd f2, r3
+; CHECK-P9-NEXT: mffprwz r3, f2
+; CHECK-P9-NEXT: mtfprd f2, r3
; CHECK-P9-NEXT: xxswapd v3, vs2
; CHECK-P9-NEXT: xxswapd vs2, vs1
; CHECK-P9-NEXT: xscvspdpn f2, vs2
; CHECK-P9-NEXT: xscvdpsxws f2, f2
-; CHECK-P9-NEXT: mfvsrwz r3, f2
-; CHECK-P9-NEXT: mtvsrd f2, r3
+; CHECK-P9-NEXT: mffprwz r3, f2
+; CHECK-P9-NEXT: mtfprd f2, r3
; CHECK-P9-NEXT: xxswapd v4, vs2
; CHECK-P9-NEXT: xscvspdpn f2, vs1
; CHECK-P9-NEXT: xxsldwi vs1, vs1, vs1, 1
; CHECK-P9-NEXT: xscvspdpn f1, vs1
; CHECK-P9-NEXT: xscvdpsxws f2, f2
; CHECK-P9-NEXT: xscvdpsxws f1, f1
-; CHECK-P9-NEXT: mfvsrwz r3, f2
-; CHECK-P9-NEXT: mtvsrd f2, r3
-; CHECK-P9-NEXT: mfvsrwz r3, f1
-; CHECK-P9-NEXT: mtvsrd f1, r3
+; CHECK-P9-NEXT: mffprwz r3, f2
+; CHECK-P9-NEXT: mtfprd f2, r3
+; CHECK-P9-NEXT: mffprwz r3, f1
+; CHECK-P9-NEXT: mtfprd f1, r3
; CHECK-P9-NEXT: xxswapd v5, vs1
; CHECK-P9-NEXT: xxsldwi vs1, vs0, vs0, 3
; CHECK-P9-NEXT: xscvspdpn f1, vs1
; CHECK-P9-NEXT: xxswapd v4, vs2
; CHECK-P9-NEXT: vmrglb v4, v4, v5
; CHECK-P9-NEXT: vmrglh v3, v4, v3
-; CHECK-P9-NEXT: mfvsrwz r3, f1
-; CHECK-P9-NEXT: mtvsrd f1, r3
+; CHECK-P9-NEXT: mffprwz r3, f1
+; CHECK-P9-NEXT: mtfprd f1, r3
; CHECK-P9-NEXT: xxswapd v4, vs1
; CHECK-P9-NEXT: xxswapd vs1, vs0
; CHECK-P9-NEXT: xscvspdpn f1, vs1
; CHECK-P9-NEXT: xscvdpsxws f1, f1
-; CHECK-P9-NEXT: mfvsrwz r3, f1
-; CHECK-P9-NEXT: mtvsrd f1, r3
+; CHECK-P9-NEXT: mffprwz r3, f1
+; CHECK-P9-NEXT: mtfprd f1, r3
; CHECK-P9-NEXT: xxswapd v5, vs1
; CHECK-P9-NEXT: xscvspdpn f1, vs0
; CHECK-P9-NEXT: xxsldwi vs0, vs0, vs0, 1
; CHECK-P9-NEXT: xscvspdpn f0, vs0
; CHECK-P9-NEXT: xscvdpsxws f1, f1
; CHECK-P9-NEXT: xscvdpsxws f0, f0
-; CHECK-P9-NEXT: mfvsrwz r3, f1
-; CHECK-P9-NEXT: mtvsrd f1, r3
-; CHECK-P9-NEXT: mfvsrwz r3, f0
-; CHECK-P9-NEXT: mtvsrd f0, r3
+; CHECK-P9-NEXT: mffprwz r3, f1
+; CHECK-P9-NEXT: mtfprd f1, r3
+; CHECK-P9-NEXT: mffprwz r3, f0
+; CHECK-P9-NEXT: mtfprd f0, r3
; CHECK-P9-NEXT: vmrglb v4, v5, v4
; CHECK-P9-NEXT: xxswapd v5, vs1
; CHECK-P9-NEXT: xxswapd v0, vs0
; CHECK-BE-NEXT: lxv vs0, 0(r3)
; CHECK-BE-NEXT: lxv vs1, 16(r3)
; CHECK-BE-NEXT: lxv vs2, 32(r3)
-; CHECK-BE-NEXT: mfvsrwz r3, f4
+; CHECK-BE-NEXT: mffprwz r3, f4
; CHECK-BE-NEXT: xxswapd vs4, vs3
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvspdpn f4, vs4
; CHECK-BE-NEXT: mtvsrd v2, r3
; CHECK-BE-NEXT: xscvdpsxws f4, f4
-; CHECK-BE-NEXT: mfvsrwz r3, f4
+; CHECK-BE-NEXT: mffprwz r3, f4
; CHECK-BE-NEXT: xscvspdpn f4, vs3
; CHECK-BE-NEXT: xxsldwi vs3, vs3, vs3, 1
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: xscvdpsxws f3, f3
; CHECK-BE-NEXT: vmrghb v2, v3, v2
-; CHECK-BE-NEXT: mfvsrwz r3, f4
+; CHECK-BE-NEXT: mffprwz r3, f4
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v3, r3
-; CHECK-BE-NEXT: mfvsrwz r3, f3
+; CHECK-BE-NEXT: mffprwz r3, f3
; CHECK-BE-NEXT: xxsldwi vs3, vs2, vs2, 3
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvspdpn f3, vs3
; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: xscvdpsxws f3, f3
-; CHECK-BE-NEXT: mfvsrwz r3, f3
+; CHECK-BE-NEXT: mffprwz r3, f3
; CHECK-BE-NEXT: xxswapd vs3, vs2
; CHECK-BE-NEXT: xscvspdpn f3, vs3
; CHECK-BE-NEXT: xscvdpsxws f3, f3
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: vmrghh v2, v3, v2
; CHECK-BE-NEXT: mtvsrd v3, r3
-; CHECK-BE-NEXT: mfvsrwz r3, f3
+; CHECK-BE-NEXT: mffprwz r3, f3
; CHECK-BE-NEXT: xscvspdpn f3, vs2
; CHECK-BE-NEXT: xxsldwi vs2, vs2, vs2, 1
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: xscvdpsxws f2, f2
; CHECK-BE-NEXT: vmrghb v3, v4, v3
-; CHECK-BE-NEXT: mfvsrwz r3, f3
+; CHECK-BE-NEXT: mffprwz r3, f3
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v4, r3
-; CHECK-BE-NEXT: mfvsrwz r3, f2
+; CHECK-BE-NEXT: mffprwz r3, f2
; CHECK-BE-NEXT: xxsldwi vs2, vs1, vs1, 3
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvspdpn f2, vs2
; CHECK-BE-NEXT: mtvsrd v5, r3
; CHECK-BE-NEXT: xscvdpsxws f2, f2
-; CHECK-BE-NEXT: mfvsrwz r3, f2
+; CHECK-BE-NEXT: mffprwz r3, f2
; CHECK-BE-NEXT: xxswapd vs2, vs1
; CHECK-BE-NEXT: xscvspdpn f2, vs2
; CHECK-BE-NEXT: xscvdpsxws f2, f2
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: vmrghw v2, v3, v2
; CHECK-BE-NEXT: mtvsrd v3, r3
-; CHECK-BE-NEXT: mfvsrwz r3, f2
+; CHECK-BE-NEXT: mffprwz r3, f2
; CHECK-BE-NEXT: xscvspdpn f2, vs1
; CHECK-BE-NEXT: xxsldwi vs1, vs1, vs1, 1
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: vmrghb v3, v4, v3
-; CHECK-BE-NEXT: mfvsrwz r3, f2
+; CHECK-BE-NEXT: mffprwz r3, f2
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v4, r3
-; CHECK-BE-NEXT: mfvsrwz r3, f1
+; CHECK-BE-NEXT: mffprwz r3, f1
; CHECK-BE-NEXT: xxsldwi vs1, vs0, vs0, 3
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvspdpn f1, vs1
; CHECK-BE-NEXT: mtvsrd v5, r3
; CHECK-BE-NEXT: xscvdpsxws f1, f1
-; CHECK-BE-NEXT: mfvsrwz r3, f1
+; CHECK-BE-NEXT: mffprwz r3, f1
; CHECK-BE-NEXT: xxswapd vs1, vs0
; CHECK-BE-NEXT: xscvspdpn f1, vs1
; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: vmrghh v3, v4, v3
; CHECK-BE-NEXT: mtvsrd v4, r3
-; CHECK-BE-NEXT: mfvsrwz r3, f1
+; CHECK-BE-NEXT: mffprwz r3, f1
; CHECK-BE-NEXT: xscvspdpn f1, vs0
; CHECK-BE-NEXT: xxsldwi vs0, vs0, vs0, 1
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v5, r3
; CHECK-BE-NEXT: xscvdpsxws f0, f0
; CHECK-BE-NEXT: vmrghb v4, v5, v4
-; CHECK-BE-NEXT: mfvsrwz r3, f1
+; CHECK-BE-NEXT: mffprwz r3, f1
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v5, r3
-; CHECK-BE-NEXT: mfvsrwz r3, f0
+; CHECK-BE-NEXT: mffprwz r3, f0
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v0, r3
; CHECK-BE-NEXT: vmrghb v5, v5, v0
; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: xscvdpsxws f1, v2
; CHECK-P8-NEXT: xscvdpsxws f0, f0
-; CHECK-P8-NEXT: mfvsrwz r3, f1
-; CHECK-P8-NEXT: mfvsrwz r4, f0
-; CHECK-P8-NEXT: mtvsrd f0, r3
-; CHECK-P8-NEXT: mtvsrd f1, r4
+; CHECK-P8-NEXT: mffprwz r3, f1
+; CHECK-P8-NEXT: mffprwz r4, f0
+; CHECK-P8-NEXT: mtfprd f0, r3
+; CHECK-P8-NEXT: mtfprd f1, r4
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: xxswapd v3, vs1
; CHECK-P8-NEXT: vmrglh v2, v2, v3
; CHECK-P8-NEXT: xxswapd vs0, v2
-; CHECK-P8-NEXT: mfvsrwz r3, f0
+; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: blr
;
; CHECK-P9-LABEL: test2elt:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: xscvdpsxws f0, v2
-; CHECK-P9-NEXT: mfvsrwz r3, f0
-; CHECK-P9-NEXT: mtvsrd f0, r3
+; CHECK-P9-NEXT: mffprwz r3, f0
+; CHECK-P9-NEXT: mtfprd f0, r3
; CHECK-P9-NEXT: xxswapd v3, vs0
; CHECK-P9-NEXT: xxswapd vs0, v2
; CHECK-P9-NEXT: xscvdpsxws f0, f0
-; CHECK-P9-NEXT: mfvsrwz r3, f0
-; CHECK-P9-NEXT: mtvsrd f0, r3
+; CHECK-P9-NEXT: mffprwz r3, f0
+; CHECK-P9-NEXT: mtfprd f0, r3
; CHECK-P9-NEXT: li r3, 0
; CHECK-P9-NEXT: xxswapd v2, vs0
; CHECK-P9-NEXT: vmrglh v2, v3, v2
; CHECK-BE-LABEL: test2elt:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: xscvdpsxws f0, v2
-; CHECK-BE-NEXT: mfvsrwz r3, f0
+; CHECK-BE-NEXT: mffprwz r3, f0
; CHECK-BE-NEXT: xxswapd vs0, v2
; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: xscvdpsxws f0, f0
; CHECK-BE-NEXT: mtvsrd v3, r3
-; CHECK-BE-NEXT: mfvsrwz r3, f0
+; CHECK-BE-NEXT: mffprwz r3, f0
; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: mtvsrd v2, r3
; CHECK-BE-NEXT: li r3, 0
; CHECK-P8-NEXT: xxswapd vs1, vs1
; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: xscvdpsxws f1, f1
-; CHECK-P8-NEXT: mfvsrwz r3, f2
-; CHECK-P8-NEXT: mfvsrwz r4, f3
-; CHECK-P8-NEXT: mtvsrd f2, r3
-; CHECK-P8-NEXT: mtvsrd f3, r4
-; CHECK-P8-NEXT: mfvsrwz r3, f0
+; CHECK-P8-NEXT: mffprwz r3, f2
+; CHECK-P8-NEXT: mffprwz r4, f3
+; CHECK-P8-NEXT: mtfprd f2, r3
+; CHECK-P8-NEXT: mtfprd f3, r4
+; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: xxswapd v2, vs2
-; CHECK-P8-NEXT: mfvsrwz r4, f1
+; CHECK-P8-NEXT: mffprwz r4, f1
; CHECK-P8-NEXT: xxswapd v4, vs3
-; CHECK-P8-NEXT: mtvsrd f0, r3
-; CHECK-P8-NEXT: mtvsrd f1, r4
+; CHECK-P8-NEXT: mtfprd f0, r3
+; CHECK-P8-NEXT: mtfprd f1, r4
; CHECK-P8-NEXT: xxswapd v3, vs0
; CHECK-P8-NEXT: xxswapd v5, vs1
; CHECK-P8-NEXT: vmrglh v2, v3, v2
; CHECK-P8-NEXT: vmrglh v3, v5, v4
; CHECK-P8-NEXT: vmrglw v2, v3, v2
; CHECK-P8-NEXT: xxswapd vs0, v2
-; CHECK-P8-NEXT: mfvsrd r3, f0
+; CHECK-P8-NEXT: mffprd r3, f0
; CHECK-P8-NEXT: blr
;
; CHECK-P9-LABEL: test4elt:
; CHECK-P9-NEXT: xxswapd vs1, vs1
; CHECK-P9-NEXT: xscvdpsxws f1, f1
; CHECK-P9-NEXT: lxv vs0, 16(r3)
-; CHECK-P9-NEXT: mfvsrwz r3, f2
-; CHECK-P9-NEXT: mtvsrd f2, r3
-; CHECK-P9-NEXT: mfvsrwz r3, f1
+; CHECK-P9-NEXT: mffprwz r3, f2
+; CHECK-P9-NEXT: mtfprd f2, r3
+; CHECK-P9-NEXT: mffprwz r3, f1
; CHECK-P9-NEXT: xxswapd v2, vs2
-; CHECK-P9-NEXT: mtvsrd f1, r3
+; CHECK-P9-NEXT: mtfprd f1, r3
; CHECK-P9-NEXT: xxswapd v3, vs1
; CHECK-P9-NEXT: xscvdpsxws f1, f0
; CHECK-P9-NEXT: xxswapd vs0, vs0
; CHECK-P9-NEXT: xscvdpsxws f0, f0
-; CHECK-P9-NEXT: mfvsrwz r3, f1
-; CHECK-P9-NEXT: mtvsrd f1, r3
-; CHECK-P9-NEXT: mfvsrwz r3, f0
-; CHECK-P9-NEXT: mtvsrd f0, r3
+; CHECK-P9-NEXT: mffprwz r3, f1
+; CHECK-P9-NEXT: mtfprd f1, r3
+; CHECK-P9-NEXT: mffprwz r3, f0
+; CHECK-P9-NEXT: mtfprd f0, r3
; CHECK-P9-NEXT: vmrglh v2, v2, v3
; CHECK-P9-NEXT: xxswapd v3, vs1
; CHECK-P9-NEXT: xxswapd v4, vs0
; CHECK-BE-NEXT: xxswapd vs1, vs1
; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: lxv vs0, 0(r3)
-; CHECK-BE-NEXT: mfvsrwz r3, f2
+; CHECK-BE-NEXT: mffprwz r3, f2
; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: mtvsrd v2, r3
-; CHECK-BE-NEXT: mfvsrwz r3, f1
+; CHECK-BE-NEXT: mffprwz r3, f1
; CHECK-BE-NEXT: xscvdpsxws f1, f0
; CHECK-BE-NEXT: xxswapd vs0, vs0
; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: xscvdpsxws f0, f0
; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: vmrghh v2, v2, v3
-; CHECK-BE-NEXT: mfvsrwz r3, f1
+; CHECK-BE-NEXT: mffprwz r3, f1
; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: mtvsrd v3, r3
-; CHECK-BE-NEXT: mfvsrwz r3, f0
+; CHECK-BE-NEXT: mffprwz r3, f0
; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: vmrghh v3, v3, v4
; CHECK-P8-NEXT: xxswapd vs3, vs3
; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: xscvdpsxws f1, f1
-; CHECK-P8-NEXT: mfvsrwz r3, f4
+; CHECK-P8-NEXT: mffprwz r3, f4
; CHECK-P8-NEXT: xscvdpsxws f2, f2
; CHECK-P8-NEXT: xscvdpsxws f3, f3
-; CHECK-P8-NEXT: mfvsrwz r4, f5
-; CHECK-P8-NEXT: mtvsrd f4, r3
-; CHECK-P8-NEXT: mfvsrwz r3, f6
-; CHECK-P8-NEXT: mtvsrd f5, r4
+; CHECK-P8-NEXT: mffprwz r4, f5
+; CHECK-P8-NEXT: mtfprd f4, r3
+; CHECK-P8-NEXT: mffprwz r3, f6
+; CHECK-P8-NEXT: mtfprd f5, r4
; CHECK-P8-NEXT: xxswapd v2, vs4
-; CHECK-P8-NEXT: mfvsrwz r4, f7
-; CHECK-P8-NEXT: mtvsrd f6, r3
+; CHECK-P8-NEXT: mffprwz r4, f7
+; CHECK-P8-NEXT: mtfprd f6, r3
; CHECK-P8-NEXT: xxswapd v3, vs5
-; CHECK-P8-NEXT: mfvsrwz r3, f0
-; CHECK-P8-NEXT: mtvsrd f7, r4
+; CHECK-P8-NEXT: mffprwz r3, f0
+; CHECK-P8-NEXT: mtfprd f7, r4
; CHECK-P8-NEXT: xxswapd v4, vs6
-; CHECK-P8-NEXT: mfvsrwz r4, f1
-; CHECK-P8-NEXT: mtvsrd f0, r3
+; CHECK-P8-NEXT: mffprwz r4, f1
+; CHECK-P8-NEXT: mtfprd f0, r3
; CHECK-P8-NEXT: xxswapd v1, vs7
-; CHECK-P8-NEXT: mfvsrwz r3, f2
-; CHECK-P8-NEXT: mtvsrd f1, r4
+; CHECK-P8-NEXT: mffprwz r3, f2
+; CHECK-P8-NEXT: mtfprd f1, r4
; CHECK-P8-NEXT: xxswapd v5, vs0
-; CHECK-P8-NEXT: mfvsrwz r4, f3
-; CHECK-P8-NEXT: mtvsrd f2, r3
+; CHECK-P8-NEXT: mffprwz r4, f3
+; CHECK-P8-NEXT: mtfprd f2, r3
; CHECK-P8-NEXT: xxswapd v0, vs1
-; CHECK-P8-NEXT: mtvsrd f0, r4
+; CHECK-P8-NEXT: mtfprd f0, r4
; CHECK-P8-NEXT: xxswapd v6, vs2
; CHECK-P8-NEXT: vmrglh v2, v5, v2
; CHECK-P8-NEXT: xxswapd v5, vs0
; CHECK-P9-NEXT: lxv vs0, 48(r3)
; CHECK-P9-NEXT: lxv vs1, 32(r3)
; CHECK-P9-NEXT: lxv vs2, 16(r3)
-; CHECK-P9-NEXT: mfvsrwz r3, f4
-; CHECK-P9-NEXT: mtvsrd f4, r3
-; CHECK-P9-NEXT: mfvsrwz r3, f3
+; CHECK-P9-NEXT: mffprwz r3, f4
+; CHECK-P9-NEXT: mtfprd f4, r3
+; CHECK-P9-NEXT: mffprwz r3, f3
; CHECK-P9-NEXT: xxswapd v2, vs4
-; CHECK-P9-NEXT: mtvsrd f3, r3
+; CHECK-P9-NEXT: mtfprd f3, r3
; CHECK-P9-NEXT: xxswapd v3, vs3
; CHECK-P9-NEXT: xscvdpsxws f3, f2
; CHECK-P9-NEXT: xxswapd vs2, vs2
; CHECK-P9-NEXT: xscvdpsxws f2, f2
-; CHECK-P9-NEXT: mfvsrwz r3, f3
-; CHECK-P9-NEXT: mtvsrd f3, r3
-; CHECK-P9-NEXT: mfvsrwz r3, f2
-; CHECK-P9-NEXT: mtvsrd f2, r3
+; CHECK-P9-NEXT: mffprwz r3, f3
+; CHECK-P9-NEXT: mtfprd f3, r3
+; CHECK-P9-NEXT: mffprwz r3, f2
+; CHECK-P9-NEXT: mtfprd f2, r3
; CHECK-P9-NEXT: xxswapd v4, vs2
; CHECK-P9-NEXT: xscvdpsxws f2, f1
; CHECK-P9-NEXT: xxswapd vs1, vs1
; CHECK-P9-NEXT: xscvdpsxws f1, f1
-; CHECK-P9-NEXT: mfvsrwz r3, f2
-; CHECK-P9-NEXT: mtvsrd f2, r3
-; CHECK-P9-NEXT: mfvsrwz r3, f1
+; CHECK-P9-NEXT: mffprwz r3, f2
+; CHECK-P9-NEXT: mtfprd f2, r3
+; CHECK-P9-NEXT: mffprwz r3, f1
; CHECK-P9-NEXT: vmrglh v2, v2, v3
; CHECK-P9-NEXT: xxswapd v3, vs3
; CHECK-P9-NEXT: vmrglh v3, v3, v4
; CHECK-P9-NEXT: vmrglw v2, v3, v2
; CHECK-P9-NEXT: xxswapd v3, vs2
-; CHECK-P9-NEXT: mtvsrd f1, r3
+; CHECK-P9-NEXT: mtfprd f1, r3
; CHECK-P9-NEXT: xxswapd v4, vs1
; CHECK-P9-NEXT: xscvdpsxws f1, f0
; CHECK-P9-NEXT: xxswapd vs0, vs0
; CHECK-P9-NEXT: xscvdpsxws f0, f0
-; CHECK-P9-NEXT: mfvsrwz r3, f1
-; CHECK-P9-NEXT: mtvsrd f1, r3
-; CHECK-P9-NEXT: mfvsrwz r3, f0
-; CHECK-P9-NEXT: mtvsrd f0, r3
+; CHECK-P9-NEXT: mffprwz r3, f1
+; CHECK-P9-NEXT: mtfprd f1, r3
+; CHECK-P9-NEXT: mffprwz r3, f0
+; CHECK-P9-NEXT: mtfprd f0, r3
; CHECK-P9-NEXT: vmrglh v3, v3, v4
; CHECK-P9-NEXT: xxswapd v4, vs1
; CHECK-P9-NEXT: xxswapd v5, vs0
; CHECK-BE-NEXT: lxv vs2, 32(r3)
; CHECK-BE-NEXT: lxv vs0, 0(r3)
; CHECK-BE-NEXT: lxv vs1, 16(r3)
-; CHECK-BE-NEXT: mfvsrwz r3, f4
+; CHECK-BE-NEXT: mffprwz r3, f4
; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: mtvsrd v2, r3
-; CHECK-BE-NEXT: mfvsrwz r3, f3
+; CHECK-BE-NEXT: mffprwz r3, f3
; CHECK-BE-NEXT: xscvdpsxws f3, f2
; CHECK-BE-NEXT: xxswapd vs2, vs2
; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: xscvdpsxws f2, f2
; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: vmrghh v2, v2, v3
-; CHECK-BE-NEXT: mfvsrwz r3, f3
+; CHECK-BE-NEXT: mffprwz r3, f3
; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: mtvsrd v3, r3
-; CHECK-BE-NEXT: mfvsrwz r3, f2
+; CHECK-BE-NEXT: mffprwz r3, f2
; CHECK-BE-NEXT: xscvdpsxws f2, f1
; CHECK-BE-NEXT: xxswapd vs1, vs1
; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: vmrghh v3, v3, v4
-; CHECK-BE-NEXT: mfvsrwz r3, f2
+; CHECK-BE-NEXT: mffprwz r3, f2
; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: vmrghw v2, v3, v2
; CHECK-BE-NEXT: mtvsrd v3, r3
-; CHECK-BE-NEXT: mfvsrwz r3, f1
+; CHECK-BE-NEXT: mffprwz r3, f1
; CHECK-BE-NEXT: xscvdpsxws f1, f0
; CHECK-BE-NEXT: xxswapd vs0, vs0
; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: xscvdpsxws f0, f0
; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: vmrghh v3, v3, v4
-; CHECK-BE-NEXT: mfvsrwz r3, f1
+; CHECK-BE-NEXT: mffprwz r3, f1
; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: mtvsrd v4, r3
-; CHECK-BE-NEXT: mfvsrwz r3, f0
+; CHECK-BE-NEXT: mffprwz r3, f0
; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: mtvsrd v5, r3
; CHECK-BE-NEXT: vmrghh v4, v4, v5
; CHECK-P8-NEXT: xxswapd vs7, vs7
; CHECK-P8-NEXT: xscvdpsxws v2, f9
; CHECK-P8-NEXT: xxswapd vs9, vs9
-; CHECK-P8-NEXT: mfvsrwz r4, f4
+; CHECK-P8-NEXT: mffprwz r4, f4
; CHECK-P8-NEXT: xscvdpsxws v3, f11
; CHECK-P8-NEXT: xxswapd vs11, vs11
; CHECK-P8-NEXT: xscvdpsxws f0, f0
-; CHECK-P8-NEXT: mfvsrwz r6, f6
-; CHECK-P8-NEXT: mtvsrd f4, r4
-; CHECK-P8-NEXT: mfvsrwz r4, f8
+; CHECK-P8-NEXT: mffprwz r6, f6
+; CHECK-P8-NEXT: mtfprd f4, r4
+; CHECK-P8-NEXT: mffprwz r4, f8
; CHECK-P8-NEXT: xscvdpsxws f1, f1
; CHECK-P8-NEXT: xxswapd v4, vs4
; CHECK-P8-NEXT: xscvdpsxws f2, f2
-; CHECK-P8-NEXT: mtvsrd f6, r6
-; CHECK-P8-NEXT: mfvsrwz r6, f10
-; CHECK-P8-NEXT: mtvsrd f8, r4
+; CHECK-P8-NEXT: mtfprd f6, r6
+; CHECK-P8-NEXT: mffprwz r6, f10
+; CHECK-P8-NEXT: mtfprd f8, r4
; CHECK-P8-NEXT: xxswapd v5, vs6
-; CHECK-P8-NEXT: mfvsrwz r4, f12
+; CHECK-P8-NEXT: mffprwz r4, f12
; CHECK-P8-NEXT: xscvdpsxws f5, f5
; CHECK-P8-NEXT: xxswapd v0, vs8
-; CHECK-P8-NEXT: mtvsrd f10, r6
-; CHECK-P8-NEXT: mfvsrwz r6, f13
-; CHECK-P8-NEXT: mtvsrd f12, r4
+; CHECK-P8-NEXT: mtfprd f10, r6
+; CHECK-P8-NEXT: mffprwz r6, f13
+; CHECK-P8-NEXT: mtfprd f12, r4
; CHECK-P8-NEXT: xxswapd v1, vs10
; CHECK-P8-NEXT: mfvsrwz r4, v2
; CHECK-P8-NEXT: xscvdpsxws f3, f3
; CHECK-P8-NEXT: xxswapd v6, vs12
; CHECK-P8-NEXT: xscvdpsxws f9, f9
-; CHECK-P8-NEXT: mtvsrd f13, r6
+; CHECK-P8-NEXT: mtfprd f13, r6
; CHECK-P8-NEXT: mfvsrwz r6, v3
; CHECK-P8-NEXT: mtvsrd v2, r4
; CHECK-P8-NEXT: xxswapd v7, vs13
-; CHECK-P8-NEXT: mfvsrwz r4, f0
+; CHECK-P8-NEXT: mffprwz r4, f0
; CHECK-P8-NEXT: xscvdpsxws f7, f7
; CHECK-P8-NEXT: xxswapd v2, v2
; CHECK-P8-NEXT: xscvdpsxws f11, f11
; CHECK-P8-NEXT: mtvsrd v3, r6
-; CHECK-P8-NEXT: mfvsrwz r6, f1
-; CHECK-P8-NEXT: mtvsrd f0, r4
+; CHECK-P8-NEXT: mffprwz r6, f1
+; CHECK-P8-NEXT: mtfprd f0, r4
; CHECK-P8-NEXT: xxswapd v3, v3
-; CHECK-P8-NEXT: mfvsrwz r4, f2
-; CHECK-P8-NEXT: mtvsrd f1, r6
+; CHECK-P8-NEXT: mffprwz r4, f2
+; CHECK-P8-NEXT: mtfprd f1, r6
; CHECK-P8-NEXT: xxswapd v8, vs0
-; CHECK-P8-NEXT: mtvsrd f2, r4
-; CHECK-P8-NEXT: mfvsrwz r4, f5
+; CHECK-P8-NEXT: mtfprd f2, r4
+; CHECK-P8-NEXT: mffprwz r4, f5
; CHECK-P8-NEXT: xxswapd v9, vs1
-; CHECK-P8-NEXT: mfvsrwz r6, f3
+; CHECK-P8-NEXT: mffprwz r6, f3
; CHECK-P8-NEXT: xxswapd v10, vs2
-; CHECK-P8-NEXT: mtvsrd f5, r4
-; CHECK-P8-NEXT: mfvsrwz r4, f9
-; CHECK-P8-NEXT: mtvsrd f3, r6
-; CHECK-P8-NEXT: mfvsrwz r6, f7
-; CHECK-P8-NEXT: mtvsrd f9, r4
-; CHECK-P8-NEXT: mfvsrwz r4, f11
+; CHECK-P8-NEXT: mtfprd f5, r4
+; CHECK-P8-NEXT: mffprwz r4, f9
+; CHECK-P8-NEXT: mtfprd f3, r6
+; CHECK-P8-NEXT: mffprwz r6, f7
+; CHECK-P8-NEXT: mtfprd f9, r4
+; CHECK-P8-NEXT: mffprwz r4, f11
; CHECK-P8-NEXT: vmrglh v4, v8, v4
; CHECK-P8-NEXT: xxswapd v8, vs3
; CHECK-P8-NEXT: vmrglh v5, v9, v5
; CHECK-P8-NEXT: xxswapd v9, vs5
-; CHECK-P8-NEXT: mtvsrd f7, r6
-; CHECK-P8-NEXT: mtvsrd f0, r4
+; CHECK-P8-NEXT: mtfprd f7, r6
+; CHECK-P8-NEXT: mtfprd f0, r4
; CHECK-P8-NEXT: vmrglh v0, v10, v0
; CHECK-P8-NEXT: xxswapd v10, vs7
; CHECK-P8-NEXT: vmrglh v1, v8, v1
; CHECK-P9-NEXT: xscvdpsxws f8, f1
; CHECK-P9-NEXT: xxswapd vs4, vs4
; CHECK-P9-NEXT: xscvdpsxws f4, f4
-; CHECK-P9-NEXT: mfvsrwz r5, f5
+; CHECK-P9-NEXT: mffprwz r5, f5
; CHECK-P9-NEXT: xscvdpsxws f9, f0
; CHECK-P9-NEXT: xxswapd vs3, vs3
; CHECK-P9-NEXT: xscvdpsxws f3, f3
-; CHECK-P9-NEXT: mtvsrd f5, r5
-; CHECK-P9-NEXT: mfvsrwz r5, f6
+; CHECK-P9-NEXT: mtfprd f5, r5
+; CHECK-P9-NEXT: mffprwz r5, f6
; CHECK-P9-NEXT: xxswapd vs2, vs2
; CHECK-P9-NEXT: xscvdpsxws f2, f2
-; CHECK-P9-NEXT: mtvsrd f6, r5
-; CHECK-P9-NEXT: mfvsrwz r5, f7
-; CHECK-P9-NEXT: mtvsrd f7, r5
-; CHECK-P9-NEXT: mfvsrwz r5, f8
-; CHECK-P9-NEXT: mtvsrd f8, r5
-; CHECK-P9-NEXT: mfvsrwz r5, f9
-; CHECK-P9-NEXT: mtvsrd f9, r5
-; CHECK-P9-NEXT: mfvsrwz r5, f4
-; CHECK-P9-NEXT: mtvsrd f4, r5
-; CHECK-P9-NEXT: mfvsrwz r5, f3
+; CHECK-P9-NEXT: mtfprd f6, r5
+; CHECK-P9-NEXT: mffprwz r5, f7
+; CHECK-P9-NEXT: mtfprd f7, r5
+; CHECK-P9-NEXT: mffprwz r5, f8
+; CHECK-P9-NEXT: mtfprd f8, r5
+; CHECK-P9-NEXT: mffprwz r5, f9
+; CHECK-P9-NEXT: mtfprd f9, r5
+; CHECK-P9-NEXT: mffprwz r5, f4
+; CHECK-P9-NEXT: mtfprd f4, r5
+; CHECK-P9-NEXT: mffprwz r5, f3
; CHECK-P9-NEXT: xxswapd vs1, vs1
; CHECK-P9-NEXT: xscvdpsxws f1, f1
; CHECK-P9-NEXT: xxswapd v2, vs5
; CHECK-P9-NEXT: xxswapd v5, vs8
; CHECK-P9-NEXT: xxswapd v0, vs9
-; CHECK-P9-NEXT: mtvsrd f3, r5
-; CHECK-P9-NEXT: mfvsrwz r5, f2
-; CHECK-P9-NEXT: mtvsrd f2, r5
+; CHECK-P9-NEXT: mtfprd f3, r5
+; CHECK-P9-NEXT: mffprwz r5, f2
+; CHECK-P9-NEXT: mtfprd f2, r5
; CHECK-P9-NEXT: xxswapd vs0, vs0
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: xxswapd v1, vs2
; CHECK-P9-NEXT: xxswapd v4, vs3
; CHECK-P9-NEXT: xscvdpsxws f3, f2
; CHECK-P9-NEXT: xxswapd vs2, vs2
-; CHECK-P9-NEXT: mfvsrwz r5, f1
+; CHECK-P9-NEXT: mffprwz r5, f1
; CHECK-P9-NEXT: vmrglh v3, v3, v4
; CHECK-P9-NEXT: xxswapd v4, vs7
-; CHECK-P9-NEXT: mtvsrd f1, r5
-; CHECK-P9-NEXT: mfvsrwz r5, f0
+; CHECK-P9-NEXT: mtfprd f1, r5
+; CHECK-P9-NEXT: mffprwz r5, f0
; CHECK-P9-NEXT: vmrglh v4, v4, v1
; CHECK-P9-NEXT: xxswapd v1, vs1
-; CHECK-P9-NEXT: mtvsrd f0, r5
+; CHECK-P9-NEXT: mtfprd f0, r5
; CHECK-P9-NEXT: vmrglh v5, v5, v1
; CHECK-P9-NEXT: xscvdpsxws f2, f2
; CHECK-P9-NEXT: xxswapd v1, vs0
; CHECK-P9-NEXT: lxv vs0, 112(r4)
; CHECK-P9-NEXT: lxv vs1, 96(r4)
-; CHECK-P9-NEXT: mfvsrwz r4, f3
-; CHECK-P9-NEXT: mtvsrd f3, r4
-; CHECK-P9-NEXT: mfvsrwz r4, f2
+; CHECK-P9-NEXT: mffprwz r4, f3
+; CHECK-P9-NEXT: mtfprd f3, r4
+; CHECK-P9-NEXT: mffprwz r4, f2
; CHECK-P9-NEXT: vmrglw v2, v3, v2
; CHECK-P9-NEXT: vmrglw v3, v5, v4
; CHECK-P9-NEXT: xxmrgld vs4, v3, v2
; CHECK-P9-NEXT: xxswapd v2, vs3
; CHECK-P9-NEXT: vmrglh v0, v0, v1
-; CHECK-P9-NEXT: mtvsrd f2, r4
+; CHECK-P9-NEXT: mtfprd f2, r4
; CHECK-P9-NEXT: xxswapd v3, vs2
; CHECK-P9-NEXT: xscvdpsxws f2, f1
; CHECK-P9-NEXT: xxswapd vs1, vs1
; CHECK-P9-NEXT: xscvdpsxws f1, f1
-; CHECK-P9-NEXT: mfvsrwz r4, f2
-; CHECK-P9-NEXT: mtvsrd f2, r4
-; CHECK-P9-NEXT: mfvsrwz r4, f1
-; CHECK-P9-NEXT: mtvsrd f1, r4
+; CHECK-P9-NEXT: mffprwz r4, f2
+; CHECK-P9-NEXT: mtfprd f2, r4
+; CHECK-P9-NEXT: mffprwz r4, f1
+; CHECK-P9-NEXT: mtfprd f1, r4
; CHECK-P9-NEXT: xxswapd v4, vs1
; CHECK-P9-NEXT: xscvdpsxws f1, f0
; CHECK-P9-NEXT: xxswapd vs0, vs0
; CHECK-P9-NEXT: xscvdpsxws f0, f0
-; CHECK-P9-NEXT: mfvsrwz r4, f1
-; CHECK-P9-NEXT: mtvsrd f1, r4
-; CHECK-P9-NEXT: mfvsrwz r4, f0
+; CHECK-P9-NEXT: mffprwz r4, f1
+; CHECK-P9-NEXT: mtfprd f1, r4
+; CHECK-P9-NEXT: mffprwz r4, f0
; CHECK-P9-NEXT: vmrglh v2, v2, v3
; CHECK-P9-NEXT: xxswapd v3, vs2
; CHECK-P9-NEXT: vmrglh v3, v3, v4
; CHECK-P9-NEXT: xxswapd v4, vs1
; CHECK-P9-NEXT: vmrglw v2, v2, v0
-; CHECK-P9-NEXT: mtvsrd f0, r4
+; CHECK-P9-NEXT: mtfprd f0, r4
; CHECK-P9-NEXT: xxswapd v5, vs0
; CHECK-P9-NEXT: vmrglh v4, v4, v5
; CHECK-P9-NEXT: vmrglw v3, v4, v3
; CHECK-BE-NEXT: xscvdpsxws f6, f3
; CHECK-BE-NEXT: xxswapd vs3, vs3
; CHECK-BE-NEXT: xscvdpsxws f4, f4
-; CHECK-BE-NEXT: mfvsrwz r5, f5
+; CHECK-BE-NEXT: mffprwz r5, f5
; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: lxv vs2, 16(r4)
; CHECK-BE-NEXT: xscvdpsxws f3, f3
; CHECK-BE-NEXT: xxswapd vs2, vs2
; CHECK-BE-NEXT: xscvdpsxws f2, f2
; CHECK-BE-NEXT: mtvsrd v2, r5
-; CHECK-BE-NEXT: mfvsrwz r5, f4
+; CHECK-BE-NEXT: mffprwz r5, f4
; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: lxv vs1, 0(r4)
; CHECK-BE-NEXT: xscvdpsxws f4, f1
; CHECK-BE-NEXT: xxswapd vs1, vs1
; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: mtvsrd v3, r5
-; CHECK-BE-NEXT: mfvsrwz r5, f6
+; CHECK-BE-NEXT: mffprwz r5, f6
; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: lxv vs0, 112(r4)
; CHECK-BE-NEXT: vmrghh v2, v2, v3
; CHECK-BE-NEXT: mtvsrd v3, r5
-; CHECK-BE-NEXT: mfvsrwz r5, f3
+; CHECK-BE-NEXT: mffprwz r5, f3
; CHECK-BE-NEXT: xscvdpsxws f3, f0
; CHECK-BE-NEXT: xxswapd vs0, vs0
; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: xscvdpsxws f0, f0
; CHECK-BE-NEXT: mtvsrd v4, r5
-; CHECK-BE-NEXT: mfvsrwz r5, f7
+; CHECK-BE-NEXT: mffprwz r5, f7
; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: vmrghh v3, v3, v4
; CHECK-BE-NEXT: mtvsrd v4, r5
-; CHECK-BE-NEXT: mfvsrwz r5, f4
+; CHECK-BE-NEXT: mffprwz r5, f4
; CHECK-BE-NEXT: vmrghw v2, v3, v2
; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: mtvsrd v5, r5
-; CHECK-BE-NEXT: mfvsrwz r5, f3
+; CHECK-BE-NEXT: mffprwz r5, f3
; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: mtvsrd v0, r5
-; CHECK-BE-NEXT: mfvsrwz r5, f2
+; CHECK-BE-NEXT: mffprwz r5, f2
; CHECK-BE-NEXT: lxv vs2, 96(r4)
; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: mtvsrd v1, r5
-; CHECK-BE-NEXT: mfvsrwz r5, f1
+; CHECK-BE-NEXT: mffprwz r5, f1
; CHECK-BE-NEXT: lxv vs1, 80(r4)
; CHECK-BE-NEXT: xscvdpsxws f3, f2
; CHECK-BE-NEXT: xxswapd vs2, vs2
; CHECK-BE-NEXT: mtvsrd v1, r5
; CHECK-BE-NEXT: xscvdpsxws f2, f2
; CHECK-BE-NEXT: vmrghh v5, v5, v1
-; CHECK-BE-NEXT: mfvsrwz r5, f0
+; CHECK-BE-NEXT: mffprwz r5, f0
; CHECK-BE-NEXT: lxv vs0, 64(r4)
-; CHECK-BE-NEXT: mfvsrwz r4, f3
+; CHECK-BE-NEXT: mffprwz r4, f3
; CHECK-BE-NEXT: sldi r4, r4, 48
; CHECK-BE-NEXT: vmrghw v3, v5, v4
; CHECK-BE-NEXT: xxmrghd vs3, v3, v2
; CHECK-BE-NEXT: mtvsrd v2, r4
-; CHECK-BE-NEXT: mfvsrwz r4, f2
+; CHECK-BE-NEXT: mffprwz r4, f2
; CHECK-BE-NEXT: xscvdpsxws f2, f1
; CHECK-BE-NEXT: xxswapd vs1, vs1
; CHECK-BE-NEXT: sldi r4, r4, 48
; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: mtvsrd v3, r4
; CHECK-BE-NEXT: vmrghh v2, v2, v3
-; CHECK-BE-NEXT: mfvsrwz r4, f2
+; CHECK-BE-NEXT: mffprwz r4, f2
; CHECK-BE-NEXT: sldi r4, r4, 48
; CHECK-BE-NEXT: mtvsrd v3, r4
-; CHECK-BE-NEXT: mfvsrwz r4, f1
+; CHECK-BE-NEXT: mffprwz r4, f1
; CHECK-BE-NEXT: xscvdpsxws f1, f0
; CHECK-BE-NEXT: xxswapd vs0, vs0
; CHECK-BE-NEXT: sldi r4, r4, 48
; CHECK-BE-NEXT: xscvdpsxws f0, f0
; CHECK-BE-NEXT: mtvsrd v4, r4
; CHECK-BE-NEXT: vmrghh v3, v3, v4
-; CHECK-BE-NEXT: mfvsrwz r4, f1
+; CHECK-BE-NEXT: mffprwz r4, f1
; CHECK-BE-NEXT: sldi r4, r4, 48
; CHECK-BE-NEXT: mtvsrd v4, r4
-; CHECK-BE-NEXT: mfvsrwz r4, f0
+; CHECK-BE-NEXT: mffprwz r4, f0
; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: mtvsrd v1, r5
; CHECK-BE-NEXT: vmrghh v0, v0, v1
; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: xscvdpsxws f1, v2
; CHECK-P8-NEXT: xscvdpsxws f0, f0
-; CHECK-P8-NEXT: mfvsrwz r3, f1
-; CHECK-P8-NEXT: mfvsrwz r4, f0
-; CHECK-P8-NEXT: mtvsrd f0, r3
-; CHECK-P8-NEXT: mtvsrd f1, r4
+; CHECK-P8-NEXT: mffprwz r3, f1
+; CHECK-P8-NEXT: mffprwz r4, f0
+; CHECK-P8-NEXT: mtfprd f0, r3
+; CHECK-P8-NEXT: mtfprd f1, r4
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: xxswapd v3, vs1
; CHECK-P8-NEXT: vmrglh v2, v2, v3
; CHECK-P8-NEXT: xxswapd vs0, v2
-; CHECK-P8-NEXT: mfvsrwz r3, f0
+; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: blr
;
; CHECK-P9-LABEL: test2elt_signed:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: xscvdpsxws f0, v2
-; CHECK-P9-NEXT: mfvsrwz r3, f0
-; CHECK-P9-NEXT: mtvsrd f0, r3
+; CHECK-P9-NEXT: mffprwz r3, f0
+; CHECK-P9-NEXT: mtfprd f0, r3
; CHECK-P9-NEXT: xxswapd v3, vs0
; CHECK-P9-NEXT: xxswapd vs0, v2
; CHECK-P9-NEXT: xscvdpsxws f0, f0
-; CHECK-P9-NEXT: mfvsrwz r3, f0
-; CHECK-P9-NEXT: mtvsrd f0, r3
+; CHECK-P9-NEXT: mffprwz r3, f0
+; CHECK-P9-NEXT: mtfprd f0, r3
; CHECK-P9-NEXT: li r3, 0
; CHECK-P9-NEXT: xxswapd v2, vs0
; CHECK-P9-NEXT: vmrglh v2, v3, v2
; CHECK-BE-LABEL: test2elt_signed:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: xscvdpsxws f0, v2
-; CHECK-BE-NEXT: mfvsrwz r3, f0
+; CHECK-BE-NEXT: mffprwz r3, f0
; CHECK-BE-NEXT: xxswapd vs0, v2
; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: xscvdpsxws f0, f0
; CHECK-BE-NEXT: mtvsrd v3, r3
-; CHECK-BE-NEXT: mfvsrwz r3, f0
+; CHECK-BE-NEXT: mffprwz r3, f0
; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: mtvsrd v2, r3
; CHECK-BE-NEXT: li r3, 0
; CHECK-P8-NEXT: xxswapd vs1, vs1
; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: xscvdpsxws f1, f1
-; CHECK-P8-NEXT: mfvsrwz r3, f2
-; CHECK-P8-NEXT: mfvsrwz r4, f3
-; CHECK-P8-NEXT: mtvsrd f2, r3
-; CHECK-P8-NEXT: mtvsrd f3, r4
-; CHECK-P8-NEXT: mfvsrwz r3, f0
+; CHECK-P8-NEXT: mffprwz r3, f2
+; CHECK-P8-NEXT: mffprwz r4, f3
+; CHECK-P8-NEXT: mtfprd f2, r3
+; CHECK-P8-NEXT: mtfprd f3, r4
+; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: xxswapd v2, vs2
-; CHECK-P8-NEXT: mfvsrwz r4, f1
+; CHECK-P8-NEXT: mffprwz r4, f1
; CHECK-P8-NEXT: xxswapd v4, vs3
-; CHECK-P8-NEXT: mtvsrd f0, r3
-; CHECK-P8-NEXT: mtvsrd f1, r4
+; CHECK-P8-NEXT: mtfprd f0, r3
+; CHECK-P8-NEXT: mtfprd f1, r4
; CHECK-P8-NEXT: xxswapd v3, vs0
; CHECK-P8-NEXT: xxswapd v5, vs1
; CHECK-P8-NEXT: vmrglh v2, v3, v2
; CHECK-P8-NEXT: vmrglh v3, v5, v4
; CHECK-P8-NEXT: vmrglw v2, v3, v2
; CHECK-P8-NEXT: xxswapd vs0, v2
-; CHECK-P8-NEXT: mfvsrd r3, f0
+; CHECK-P8-NEXT: mffprd r3, f0
; CHECK-P8-NEXT: blr
;
; CHECK-P9-LABEL: test4elt_signed:
; CHECK-P9-NEXT: xxswapd vs1, vs1
; CHECK-P9-NEXT: xscvdpsxws f1, f1
; CHECK-P9-NEXT: lxv vs0, 16(r3)
-; CHECK-P9-NEXT: mfvsrwz r3, f2
-; CHECK-P9-NEXT: mtvsrd f2, r3
-; CHECK-P9-NEXT: mfvsrwz r3, f1
+; CHECK-P9-NEXT: mffprwz r3, f2
+; CHECK-P9-NEXT: mtfprd f2, r3
+; CHECK-P9-NEXT: mffprwz r3, f1
; CHECK-P9-NEXT: xxswapd v2, vs2
-; CHECK-P9-NEXT: mtvsrd f1, r3
+; CHECK-P9-NEXT: mtfprd f1, r3
; CHECK-P9-NEXT: xxswapd v3, vs1
; CHECK-P9-NEXT: xscvdpsxws f1, f0
; CHECK-P9-NEXT: xxswapd vs0, vs0
; CHECK-P9-NEXT: xscvdpsxws f0, f0
-; CHECK-P9-NEXT: mfvsrwz r3, f1
-; CHECK-P9-NEXT: mtvsrd f1, r3
-; CHECK-P9-NEXT: mfvsrwz r3, f0
-; CHECK-P9-NEXT: mtvsrd f0, r3
+; CHECK-P9-NEXT: mffprwz r3, f1
+; CHECK-P9-NEXT: mtfprd f1, r3
+; CHECK-P9-NEXT: mffprwz r3, f0
+; CHECK-P9-NEXT: mtfprd f0, r3
; CHECK-P9-NEXT: vmrglh v2, v2, v3
; CHECK-P9-NEXT: xxswapd v3, vs1
; CHECK-P9-NEXT: xxswapd v4, vs0
; CHECK-BE-NEXT: xxswapd vs1, vs1
; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: lxv vs0, 0(r3)
-; CHECK-BE-NEXT: mfvsrwz r3, f2
+; CHECK-BE-NEXT: mffprwz r3, f2
; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: mtvsrd v2, r3
-; CHECK-BE-NEXT: mfvsrwz r3, f1
+; CHECK-BE-NEXT: mffprwz r3, f1
; CHECK-BE-NEXT: xscvdpsxws f1, f0
; CHECK-BE-NEXT: xxswapd vs0, vs0
; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: xscvdpsxws f0, f0
; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: vmrghh v2, v2, v3
-; CHECK-BE-NEXT: mfvsrwz r3, f1
+; CHECK-BE-NEXT: mffprwz r3, f1
; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: mtvsrd v3, r3
-; CHECK-BE-NEXT: mfvsrwz r3, f0
+; CHECK-BE-NEXT: mffprwz r3, f0
; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: vmrghh v3, v3, v4
; CHECK-P8-NEXT: xxswapd vs3, vs3
; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: xscvdpsxws f1, f1
-; CHECK-P8-NEXT: mfvsrwz r3, f4
+; CHECK-P8-NEXT: mffprwz r3, f4
; CHECK-P8-NEXT: xscvdpsxws f2, f2
; CHECK-P8-NEXT: xscvdpsxws f3, f3
-; CHECK-P8-NEXT: mfvsrwz r4, f5
-; CHECK-P8-NEXT: mtvsrd f4, r3
-; CHECK-P8-NEXT: mfvsrwz r3, f6
-; CHECK-P8-NEXT: mtvsrd f5, r4
+; CHECK-P8-NEXT: mffprwz r4, f5
+; CHECK-P8-NEXT: mtfprd f4, r3
+; CHECK-P8-NEXT: mffprwz r3, f6
+; CHECK-P8-NEXT: mtfprd f5, r4
; CHECK-P8-NEXT: xxswapd v2, vs4
-; CHECK-P8-NEXT: mfvsrwz r4, f7
-; CHECK-P8-NEXT: mtvsrd f6, r3
+; CHECK-P8-NEXT: mffprwz r4, f7
+; CHECK-P8-NEXT: mtfprd f6, r3
; CHECK-P8-NEXT: xxswapd v3, vs5
-; CHECK-P8-NEXT: mfvsrwz r3, f0
-; CHECK-P8-NEXT: mtvsrd f7, r4
+; CHECK-P8-NEXT: mffprwz r3, f0
+; CHECK-P8-NEXT: mtfprd f7, r4
; CHECK-P8-NEXT: xxswapd v4, vs6
-; CHECK-P8-NEXT: mfvsrwz r4, f1
-; CHECK-P8-NEXT: mtvsrd f0, r3
+; CHECK-P8-NEXT: mffprwz r4, f1
+; CHECK-P8-NEXT: mtfprd f0, r3
; CHECK-P8-NEXT: xxswapd v1, vs7
-; CHECK-P8-NEXT: mfvsrwz r3, f2
-; CHECK-P8-NEXT: mtvsrd f1, r4
+; CHECK-P8-NEXT: mffprwz r3, f2
+; CHECK-P8-NEXT: mtfprd f1, r4
; CHECK-P8-NEXT: xxswapd v5, vs0
-; CHECK-P8-NEXT: mfvsrwz r4, f3
-; CHECK-P8-NEXT: mtvsrd f2, r3
+; CHECK-P8-NEXT: mffprwz r4, f3
+; CHECK-P8-NEXT: mtfprd f2, r3
; CHECK-P8-NEXT: xxswapd v0, vs1
-; CHECK-P8-NEXT: mtvsrd f0, r4
+; CHECK-P8-NEXT: mtfprd f0, r4
; CHECK-P8-NEXT: xxswapd v6, vs2
; CHECK-P8-NEXT: vmrglh v2, v5, v2
; CHECK-P8-NEXT: xxswapd v5, vs0
; CHECK-P9-NEXT: lxv vs0, 48(r3)
; CHECK-P9-NEXT: lxv vs1, 32(r3)
; CHECK-P9-NEXT: lxv vs2, 16(r3)
-; CHECK-P9-NEXT: mfvsrwz r3, f4
-; CHECK-P9-NEXT: mtvsrd f4, r3
-; CHECK-P9-NEXT: mfvsrwz r3, f3
+; CHECK-P9-NEXT: mffprwz r3, f4
+; CHECK-P9-NEXT: mtfprd f4, r3
+; CHECK-P9-NEXT: mffprwz r3, f3
; CHECK-P9-NEXT: xxswapd v2, vs4
-; CHECK-P9-NEXT: mtvsrd f3, r3
+; CHECK-P9-NEXT: mtfprd f3, r3
; CHECK-P9-NEXT: xxswapd v3, vs3
; CHECK-P9-NEXT: xscvdpsxws f3, f2
; CHECK-P9-NEXT: xxswapd vs2, vs2
; CHECK-P9-NEXT: xscvdpsxws f2, f2
-; CHECK-P9-NEXT: mfvsrwz r3, f3
-; CHECK-P9-NEXT: mtvsrd f3, r3
-; CHECK-P9-NEXT: mfvsrwz r3, f2
-; CHECK-P9-NEXT: mtvsrd f2, r3
+; CHECK-P9-NEXT: mffprwz r3, f3
+; CHECK-P9-NEXT: mtfprd f3, r3
+; CHECK-P9-NEXT: mffprwz r3, f2
+; CHECK-P9-NEXT: mtfprd f2, r3
; CHECK-P9-NEXT: xxswapd v4, vs2
; CHECK-P9-NEXT: xscvdpsxws f2, f1
; CHECK-P9-NEXT: xxswapd vs1, vs1
; CHECK-P9-NEXT: xscvdpsxws f1, f1
-; CHECK-P9-NEXT: mfvsrwz r3, f2
-; CHECK-P9-NEXT: mtvsrd f2, r3
-; CHECK-P9-NEXT: mfvsrwz r3, f1
+; CHECK-P9-NEXT: mffprwz r3, f2
+; CHECK-P9-NEXT: mtfprd f2, r3
+; CHECK-P9-NEXT: mffprwz r3, f1
; CHECK-P9-NEXT: vmrglh v2, v2, v3
; CHECK-P9-NEXT: xxswapd v3, vs3
; CHECK-P9-NEXT: vmrglh v3, v3, v4
; CHECK-P9-NEXT: vmrglw v2, v3, v2
; CHECK-P9-NEXT: xxswapd v3, vs2
-; CHECK-P9-NEXT: mtvsrd f1, r3
+; CHECK-P9-NEXT: mtfprd f1, r3
; CHECK-P9-NEXT: xxswapd v4, vs1
; CHECK-P9-NEXT: xscvdpsxws f1, f0
; CHECK-P9-NEXT: xxswapd vs0, vs0
; CHECK-P9-NEXT: xscvdpsxws f0, f0
-; CHECK-P9-NEXT: mfvsrwz r3, f1
-; CHECK-P9-NEXT: mtvsrd f1, r3
-; CHECK-P9-NEXT: mfvsrwz r3, f0
-; CHECK-P9-NEXT: mtvsrd f0, r3
+; CHECK-P9-NEXT: mffprwz r3, f1
+; CHECK-P9-NEXT: mtfprd f1, r3
+; CHECK-P9-NEXT: mffprwz r3, f0
+; CHECK-P9-NEXT: mtfprd f0, r3
; CHECK-P9-NEXT: vmrglh v3, v3, v4
; CHECK-P9-NEXT: xxswapd v4, vs1
; CHECK-P9-NEXT: xxswapd v5, vs0
; CHECK-BE-NEXT: lxv vs2, 32(r3)
; CHECK-BE-NEXT: lxv vs0, 0(r3)
; CHECK-BE-NEXT: lxv vs1, 16(r3)
-; CHECK-BE-NEXT: mfvsrwz r3, f4
+; CHECK-BE-NEXT: mffprwz r3, f4
; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: mtvsrd v2, r3
-; CHECK-BE-NEXT: mfvsrwz r3, f3
+; CHECK-BE-NEXT: mffprwz r3, f3
; CHECK-BE-NEXT: xscvdpsxws f3, f2
; CHECK-BE-NEXT: xxswapd vs2, vs2
; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: xscvdpsxws f2, f2
; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: vmrghh v2, v2, v3
-; CHECK-BE-NEXT: mfvsrwz r3, f3
+; CHECK-BE-NEXT: mffprwz r3, f3
; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: mtvsrd v3, r3
-; CHECK-BE-NEXT: mfvsrwz r3, f2
+; CHECK-BE-NEXT: mffprwz r3, f2
; CHECK-BE-NEXT: xscvdpsxws f2, f1
; CHECK-BE-NEXT: xxswapd vs1, vs1
; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: vmrghh v3, v3, v4
-; CHECK-BE-NEXT: mfvsrwz r3, f2
+; CHECK-BE-NEXT: mffprwz r3, f2
; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: vmrghw v2, v3, v2
; CHECK-BE-NEXT: mtvsrd v3, r3
-; CHECK-BE-NEXT: mfvsrwz r3, f1
+; CHECK-BE-NEXT: mffprwz r3, f1
; CHECK-BE-NEXT: xscvdpsxws f1, f0
; CHECK-BE-NEXT: xxswapd vs0, vs0
; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: xscvdpsxws f0, f0
; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: vmrghh v3, v3, v4
-; CHECK-BE-NEXT: mfvsrwz r3, f1
+; CHECK-BE-NEXT: mffprwz r3, f1
; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: mtvsrd v4, r3
-; CHECK-BE-NEXT: mfvsrwz r3, f0
+; CHECK-BE-NEXT: mffprwz r3, f0
; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: mtvsrd v5, r3
; CHECK-BE-NEXT: vmrghh v4, v4, v5
; CHECK-P8-NEXT: xxswapd vs7, vs7
; CHECK-P8-NEXT: xscvdpsxws v2, f9
; CHECK-P8-NEXT: xxswapd vs9, vs9
-; CHECK-P8-NEXT: mfvsrwz r4, f4
+; CHECK-P8-NEXT: mffprwz r4, f4
; CHECK-P8-NEXT: xscvdpsxws v3, f11
; CHECK-P8-NEXT: xxswapd vs11, vs11
; CHECK-P8-NEXT: xscvdpsxws f0, f0
-; CHECK-P8-NEXT: mfvsrwz r6, f6
-; CHECK-P8-NEXT: mtvsrd f4, r4
-; CHECK-P8-NEXT: mfvsrwz r4, f8
+; CHECK-P8-NEXT: mffprwz r6, f6
+; CHECK-P8-NEXT: mtfprd f4, r4
+; CHECK-P8-NEXT: mffprwz r4, f8
; CHECK-P8-NEXT: xscvdpsxws f1, f1
; CHECK-P8-NEXT: xxswapd v4, vs4
; CHECK-P8-NEXT: xscvdpsxws f2, f2
-; CHECK-P8-NEXT: mtvsrd f6, r6
-; CHECK-P8-NEXT: mfvsrwz r6, f10
-; CHECK-P8-NEXT: mtvsrd f8, r4
+; CHECK-P8-NEXT: mtfprd f6, r6
+; CHECK-P8-NEXT: mffprwz r6, f10
+; CHECK-P8-NEXT: mtfprd f8, r4
; CHECK-P8-NEXT: xxswapd v5, vs6
-; CHECK-P8-NEXT: mfvsrwz r4, f12
+; CHECK-P8-NEXT: mffprwz r4, f12
; CHECK-P8-NEXT: xscvdpsxws f5, f5
; CHECK-P8-NEXT: xxswapd v0, vs8
-; CHECK-P8-NEXT: mtvsrd f10, r6
-; CHECK-P8-NEXT: mfvsrwz r6, f13
-; CHECK-P8-NEXT: mtvsrd f12, r4
+; CHECK-P8-NEXT: mtfprd f10, r6
+; CHECK-P8-NEXT: mffprwz r6, f13
+; CHECK-P8-NEXT: mtfprd f12, r4
; CHECK-P8-NEXT: xxswapd v1, vs10
; CHECK-P8-NEXT: mfvsrwz r4, v2
; CHECK-P8-NEXT: xscvdpsxws f3, f3
; CHECK-P8-NEXT: xxswapd v6, vs12
; CHECK-P8-NEXT: xscvdpsxws f9, f9
-; CHECK-P8-NEXT: mtvsrd f13, r6
+; CHECK-P8-NEXT: mtfprd f13, r6
; CHECK-P8-NEXT: mfvsrwz r6, v3
; CHECK-P8-NEXT: mtvsrd v2, r4
; CHECK-P8-NEXT: xxswapd v7, vs13
-; CHECK-P8-NEXT: mfvsrwz r4, f0
+; CHECK-P8-NEXT: mffprwz r4, f0
; CHECK-P8-NEXT: xscvdpsxws f7, f7
; CHECK-P8-NEXT: xxswapd v2, v2
; CHECK-P8-NEXT: xscvdpsxws f11, f11
; CHECK-P8-NEXT: mtvsrd v3, r6
-; CHECK-P8-NEXT: mfvsrwz r6, f1
-; CHECK-P8-NEXT: mtvsrd f0, r4
+; CHECK-P8-NEXT: mffprwz r6, f1
+; CHECK-P8-NEXT: mtfprd f0, r4
; CHECK-P8-NEXT: xxswapd v3, v3
-; CHECK-P8-NEXT: mfvsrwz r4, f2
-; CHECK-P8-NEXT: mtvsrd f1, r6
+; CHECK-P8-NEXT: mffprwz r4, f2
+; CHECK-P8-NEXT: mtfprd f1, r6
; CHECK-P8-NEXT: xxswapd v8, vs0
-; CHECK-P8-NEXT: mtvsrd f2, r4
-; CHECK-P8-NEXT: mfvsrwz r4, f5
+; CHECK-P8-NEXT: mtfprd f2, r4
+; CHECK-P8-NEXT: mffprwz r4, f5
; CHECK-P8-NEXT: xxswapd v9, vs1
-; CHECK-P8-NEXT: mfvsrwz r6, f3
+; CHECK-P8-NEXT: mffprwz r6, f3
; CHECK-P8-NEXT: xxswapd v10, vs2
-; CHECK-P8-NEXT: mtvsrd f5, r4
-; CHECK-P8-NEXT: mfvsrwz r4, f9
-; CHECK-P8-NEXT: mtvsrd f3, r6
-; CHECK-P8-NEXT: mfvsrwz r6, f7
-; CHECK-P8-NEXT: mtvsrd f9, r4
-; CHECK-P8-NEXT: mfvsrwz r4, f11
+; CHECK-P8-NEXT: mtfprd f5, r4
+; CHECK-P8-NEXT: mffprwz r4, f9
+; CHECK-P8-NEXT: mtfprd f3, r6
+; CHECK-P8-NEXT: mffprwz r6, f7
+; CHECK-P8-NEXT: mtfprd f9, r4
+; CHECK-P8-NEXT: mffprwz r4, f11
; CHECK-P8-NEXT: vmrglh v4, v8, v4
; CHECK-P8-NEXT: xxswapd v8, vs3
; CHECK-P8-NEXT: vmrglh v5, v9, v5
; CHECK-P8-NEXT: xxswapd v9, vs5
-; CHECK-P8-NEXT: mtvsrd f7, r6
-; CHECK-P8-NEXT: mtvsrd f0, r4
+; CHECK-P8-NEXT: mtfprd f7, r6
+; CHECK-P8-NEXT: mtfprd f0, r4
; CHECK-P8-NEXT: vmrglh v0, v10, v0
; CHECK-P8-NEXT: xxswapd v10, vs7
; CHECK-P8-NEXT: vmrglh v1, v8, v1
; CHECK-P9-NEXT: xscvdpsxws f8, f1
; CHECK-P9-NEXT: xxswapd vs4, vs4
; CHECK-P9-NEXT: xscvdpsxws f4, f4
-; CHECK-P9-NEXT: mfvsrwz r5, f5
+; CHECK-P9-NEXT: mffprwz r5, f5
; CHECK-P9-NEXT: xscvdpsxws f9, f0
; CHECK-P9-NEXT: xxswapd vs3, vs3
; CHECK-P9-NEXT: xscvdpsxws f3, f3
-; CHECK-P9-NEXT: mtvsrd f5, r5
-; CHECK-P9-NEXT: mfvsrwz r5, f6
+; CHECK-P9-NEXT: mtfprd f5, r5
+; CHECK-P9-NEXT: mffprwz r5, f6
; CHECK-P9-NEXT: xxswapd vs2, vs2
; CHECK-P9-NEXT: xscvdpsxws f2, f2
-; CHECK-P9-NEXT: mtvsrd f6, r5
-; CHECK-P9-NEXT: mfvsrwz r5, f7
-; CHECK-P9-NEXT: mtvsrd f7, r5
-; CHECK-P9-NEXT: mfvsrwz r5, f8
-; CHECK-P9-NEXT: mtvsrd f8, r5
-; CHECK-P9-NEXT: mfvsrwz r5, f9
-; CHECK-P9-NEXT: mtvsrd f9, r5
-; CHECK-P9-NEXT: mfvsrwz r5, f4
-; CHECK-P9-NEXT: mtvsrd f4, r5
-; CHECK-P9-NEXT: mfvsrwz r5, f3
+; CHECK-P9-NEXT: mtfprd f6, r5
+; CHECK-P9-NEXT: mffprwz r5, f7
+; CHECK-P9-NEXT: mtfprd f7, r5
+; CHECK-P9-NEXT: mffprwz r5, f8
+; CHECK-P9-NEXT: mtfprd f8, r5
+; CHECK-P9-NEXT: mffprwz r5, f9
+; CHECK-P9-NEXT: mtfprd f9, r5
+; CHECK-P9-NEXT: mffprwz r5, f4
+; CHECK-P9-NEXT: mtfprd f4, r5
+; CHECK-P9-NEXT: mffprwz r5, f3
; CHECK-P9-NEXT: xxswapd vs1, vs1
; CHECK-P9-NEXT: xscvdpsxws f1, f1
; CHECK-P9-NEXT: xxswapd v2, vs5
; CHECK-P9-NEXT: xxswapd v5, vs8
; CHECK-P9-NEXT: xxswapd v0, vs9
-; CHECK-P9-NEXT: mtvsrd f3, r5
-; CHECK-P9-NEXT: mfvsrwz r5, f2
-; CHECK-P9-NEXT: mtvsrd f2, r5
+; CHECK-P9-NEXT: mtfprd f3, r5
+; CHECK-P9-NEXT: mffprwz r5, f2
+; CHECK-P9-NEXT: mtfprd f2, r5
; CHECK-P9-NEXT: xxswapd vs0, vs0
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: xxswapd v1, vs2
; CHECK-P9-NEXT: xxswapd v4, vs3
; CHECK-P9-NEXT: xscvdpsxws f3, f2
; CHECK-P9-NEXT: xxswapd vs2, vs2
-; CHECK-P9-NEXT: mfvsrwz r5, f1
+; CHECK-P9-NEXT: mffprwz r5, f1
; CHECK-P9-NEXT: vmrglh v3, v3, v4
; CHECK-P9-NEXT: xxswapd v4, vs7
-; CHECK-P9-NEXT: mtvsrd f1, r5
-; CHECK-P9-NEXT: mfvsrwz r5, f0
+; CHECK-P9-NEXT: mtfprd f1, r5
+; CHECK-P9-NEXT: mffprwz r5, f0
; CHECK-P9-NEXT: vmrglh v4, v4, v1
; CHECK-P9-NEXT: xxswapd v1, vs1
-; CHECK-P9-NEXT: mtvsrd f0, r5
+; CHECK-P9-NEXT: mtfprd f0, r5
; CHECK-P9-NEXT: vmrglh v5, v5, v1
; CHECK-P9-NEXT: xscvdpsxws f2, f2
; CHECK-P9-NEXT: xxswapd v1, vs0
; CHECK-P9-NEXT: lxv vs0, 112(r4)
; CHECK-P9-NEXT: lxv vs1, 96(r4)
-; CHECK-P9-NEXT: mfvsrwz r4, f3
-; CHECK-P9-NEXT: mtvsrd f3, r4
-; CHECK-P9-NEXT: mfvsrwz r4, f2
+; CHECK-P9-NEXT: mffprwz r4, f3
+; CHECK-P9-NEXT: mtfprd f3, r4
+; CHECK-P9-NEXT: mffprwz r4, f2
; CHECK-P9-NEXT: vmrglw v2, v3, v2
; CHECK-P9-NEXT: vmrglw v3, v5, v4
; CHECK-P9-NEXT: xxmrgld vs4, v3, v2
; CHECK-P9-NEXT: xxswapd v2, vs3
; CHECK-P9-NEXT: vmrglh v0, v0, v1
-; CHECK-P9-NEXT: mtvsrd f2, r4
+; CHECK-P9-NEXT: mtfprd f2, r4
; CHECK-P9-NEXT: xxswapd v3, vs2
; CHECK-P9-NEXT: xscvdpsxws f2, f1
; CHECK-P9-NEXT: xxswapd vs1, vs1
; CHECK-P9-NEXT: xscvdpsxws f1, f1
-; CHECK-P9-NEXT: mfvsrwz r4, f2
-; CHECK-P9-NEXT: mtvsrd f2, r4
-; CHECK-P9-NEXT: mfvsrwz r4, f1
-; CHECK-P9-NEXT: mtvsrd f1, r4
+; CHECK-P9-NEXT: mffprwz r4, f2
+; CHECK-P9-NEXT: mtfprd f2, r4
+; CHECK-P9-NEXT: mffprwz r4, f1
+; CHECK-P9-NEXT: mtfprd f1, r4
; CHECK-P9-NEXT: xxswapd v4, vs1
; CHECK-P9-NEXT: xscvdpsxws f1, f0
; CHECK-P9-NEXT: xxswapd vs0, vs0
; CHECK-P9-NEXT: xscvdpsxws f0, f0
-; CHECK-P9-NEXT: mfvsrwz r4, f1
-; CHECK-P9-NEXT: mtvsrd f1, r4
-; CHECK-P9-NEXT: mfvsrwz r4, f0
+; CHECK-P9-NEXT: mffprwz r4, f1
+; CHECK-P9-NEXT: mtfprd f1, r4
+; CHECK-P9-NEXT: mffprwz r4, f0
; CHECK-P9-NEXT: vmrglh v2, v2, v3
; CHECK-P9-NEXT: xxswapd v3, vs2
; CHECK-P9-NEXT: vmrglh v3, v3, v4
; CHECK-P9-NEXT: xxswapd v4, vs1
; CHECK-P9-NEXT: vmrglw v2, v2, v0
-; CHECK-P9-NEXT: mtvsrd f0, r4
+; CHECK-P9-NEXT: mtfprd f0, r4
; CHECK-P9-NEXT: xxswapd v5, vs0
; CHECK-P9-NEXT: vmrglh v4, v4, v5
; CHECK-P9-NEXT: vmrglw v3, v4, v3
; CHECK-BE-NEXT: xscvdpsxws f6, f3
; CHECK-BE-NEXT: xxswapd vs3, vs3
; CHECK-BE-NEXT: xscvdpsxws f4, f4
-; CHECK-BE-NEXT: mfvsrwz r5, f5
+; CHECK-BE-NEXT: mffprwz r5, f5
; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: lxv vs2, 16(r4)
; CHECK-BE-NEXT: xscvdpsxws f3, f3
; CHECK-BE-NEXT: xxswapd vs2, vs2
; CHECK-BE-NEXT: xscvdpsxws f2, f2
; CHECK-BE-NEXT: mtvsrd v2, r5
-; CHECK-BE-NEXT: mfvsrwz r5, f4
+; CHECK-BE-NEXT: mffprwz r5, f4
; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: lxv vs1, 0(r4)
; CHECK-BE-NEXT: xscvdpsxws f4, f1
; CHECK-BE-NEXT: xxswapd vs1, vs1
; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: mtvsrd v3, r5
-; CHECK-BE-NEXT: mfvsrwz r5, f6
+; CHECK-BE-NEXT: mffprwz r5, f6
; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: lxv vs0, 112(r4)
; CHECK-BE-NEXT: vmrghh v2, v2, v3
; CHECK-BE-NEXT: mtvsrd v3, r5
-; CHECK-BE-NEXT: mfvsrwz r5, f3
+; CHECK-BE-NEXT: mffprwz r5, f3
; CHECK-BE-NEXT: xscvdpsxws f3, f0
; CHECK-BE-NEXT: xxswapd vs0, vs0
; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: xscvdpsxws f0, f0
; CHECK-BE-NEXT: mtvsrd v4, r5
-; CHECK-BE-NEXT: mfvsrwz r5, f7
+; CHECK-BE-NEXT: mffprwz r5, f7
; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: vmrghh v3, v3, v4
; CHECK-BE-NEXT: mtvsrd v4, r5
-; CHECK-BE-NEXT: mfvsrwz r5, f4
+; CHECK-BE-NEXT: mffprwz r5, f4
; CHECK-BE-NEXT: vmrghw v2, v3, v2
; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: mtvsrd v5, r5
-; CHECK-BE-NEXT: mfvsrwz r5, f3
+; CHECK-BE-NEXT: mffprwz r5, f3
; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: mtvsrd v0, r5
-; CHECK-BE-NEXT: mfvsrwz r5, f2
+; CHECK-BE-NEXT: mffprwz r5, f2
; CHECK-BE-NEXT: lxv vs2, 96(r4)
; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: mtvsrd v1, r5
-; CHECK-BE-NEXT: mfvsrwz r5, f1
+; CHECK-BE-NEXT: mffprwz r5, f1
; CHECK-BE-NEXT: lxv vs1, 80(r4)
; CHECK-BE-NEXT: xscvdpsxws f3, f2
; CHECK-BE-NEXT: xxswapd vs2, vs2
; CHECK-BE-NEXT: mtvsrd v1, r5
; CHECK-BE-NEXT: xscvdpsxws f2, f2
; CHECK-BE-NEXT: vmrghh v5, v5, v1
-; CHECK-BE-NEXT: mfvsrwz r5, f0
+; CHECK-BE-NEXT: mffprwz r5, f0
; CHECK-BE-NEXT: lxv vs0, 64(r4)
-; CHECK-BE-NEXT: mfvsrwz r4, f3
+; CHECK-BE-NEXT: mffprwz r4, f3
; CHECK-BE-NEXT: sldi r4, r4, 48
; CHECK-BE-NEXT: vmrghw v3, v5, v4
; CHECK-BE-NEXT: xxmrghd vs3, v3, v2
; CHECK-BE-NEXT: mtvsrd v2, r4
-; CHECK-BE-NEXT: mfvsrwz r4, f2
+; CHECK-BE-NEXT: mffprwz r4, f2
; CHECK-BE-NEXT: xscvdpsxws f2, f1
; CHECK-BE-NEXT: xxswapd vs1, vs1
; CHECK-BE-NEXT: sldi r4, r4, 48
; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: mtvsrd v3, r4
; CHECK-BE-NEXT: vmrghh v2, v2, v3
-; CHECK-BE-NEXT: mfvsrwz r4, f2
+; CHECK-BE-NEXT: mffprwz r4, f2
; CHECK-BE-NEXT: sldi r4, r4, 48
; CHECK-BE-NEXT: mtvsrd v3, r4
-; CHECK-BE-NEXT: mfvsrwz r4, f1
+; CHECK-BE-NEXT: mffprwz r4, f1
; CHECK-BE-NEXT: xscvdpsxws f1, f0
; CHECK-BE-NEXT: xxswapd vs0, vs0
; CHECK-BE-NEXT: sldi r4, r4, 48
; CHECK-BE-NEXT: xscvdpsxws f0, f0
; CHECK-BE-NEXT: mtvsrd v4, r4
; CHECK-BE-NEXT: vmrghh v3, v3, v4
-; CHECK-BE-NEXT: mfvsrwz r4, f1
+; CHECK-BE-NEXT: mffprwz r4, f1
; CHECK-BE-NEXT: sldi r4, r4, 48
; CHECK-BE-NEXT: mtvsrd v4, r4
-; CHECK-BE-NEXT: mfvsrwz r4, f0
+; CHECK-BE-NEXT: mffprwz r4, f0
; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: mtvsrd v1, r5
; CHECK-BE-NEXT: vmrghh v0, v0, v1
; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: xscvdpuxws f1, v2
; CHECK-P8-NEXT: xscvdpuxws f0, f0
-; CHECK-P8-NEXT: mfvsrwz r3, f1
-; CHECK-P8-NEXT: mfvsrwz r4, f0
-; CHECK-P8-NEXT: mtvsrd f0, r3
-; CHECK-P8-NEXT: mtvsrd f1, r4
+; CHECK-P8-NEXT: mffprwz r3, f1
+; CHECK-P8-NEXT: mffprwz r4, f0
+; CHECK-P8-NEXT: mtfprd f0, r3
+; CHECK-P8-NEXT: mtfprd f1, r4
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: xxswapd v3, vs1
; CHECK-P8-NEXT: vmrglw v2, v2, v3
; CHECK-P8-NEXT: xxswapd vs0, v2
-; CHECK-P8-NEXT: mfvsrd r3, f0
+; CHECK-P8-NEXT: mffprd r3, f0
; CHECK-P8-NEXT: blr
;
; CHECK-P9-LABEL: test2elt:
; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: xscvdpsxws f1, v2
; CHECK-P8-NEXT: xscvdpsxws f0, f0
-; CHECK-P8-NEXT: mfvsrwz r3, f1
-; CHECK-P8-NEXT: mfvsrwz r4, f0
-; CHECK-P8-NEXT: mtvsrd f0, r3
-; CHECK-P8-NEXT: mtvsrd f1, r4
+; CHECK-P8-NEXT: mffprwz r3, f1
+; CHECK-P8-NEXT: mffprwz r4, f0
+; CHECK-P8-NEXT: mtfprd f0, r3
+; CHECK-P8-NEXT: mtfprd f1, r4
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: xxswapd v3, vs1
; CHECK-P8-NEXT: vmrglw v2, v2, v3
; CHECK-P8-NEXT: xxswapd vs0, v2
-; CHECK-P8-NEXT: mfvsrd r3, f0
+; CHECK-P8-NEXT: mffprd r3, f0
; CHECK-P8-NEXT: blr
;
; CHECK-P9-LABEL: test2elt_signed:
; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: xscvdpsxws f1, v2
; CHECK-P8-NEXT: xscvdpsxws f0, f0
-; CHECK-P8-NEXT: mfvsrwz r3, f1
-; CHECK-P8-NEXT: mfvsrwz r4, f0
-; CHECK-P8-NEXT: mtvsrd f0, r3
-; CHECK-P8-NEXT: mtvsrd f1, r4
+; CHECK-P8-NEXT: mffprwz r3, f1
+; CHECK-P8-NEXT: mffprwz r4, f0
+; CHECK-P8-NEXT: mtfprd f0, r3
+; CHECK-P8-NEXT: mtfprd f1, r4
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: xxswapd v3, vs1
; CHECK-P8-NEXT: vmrglb v2, v2, v3
; CHECK-P8-NEXT: xxswapd vs0, v2
-; CHECK-P8-NEXT: mfvsrd r3, f0
+; CHECK-P8-NEXT: mffprd r3, f0
; CHECK-P8-NEXT: clrldi r3, r3, 48
; CHECK-P8-NEXT: sth r3, -2(r1)
; CHECK-P8-NEXT: lhz r3, -2(r1)
; CHECK-P9-LABEL: test2elt:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: xscvdpsxws f0, v2
-; CHECK-P9-NEXT: mfvsrwz r3, f0
-; CHECK-P9-NEXT: mtvsrd f0, r3
+; CHECK-P9-NEXT: mffprwz r3, f0
+; CHECK-P9-NEXT: mtfprd f0, r3
; CHECK-P9-NEXT: xxswapd v3, vs0
; CHECK-P9-NEXT: xxswapd vs0, v2
; CHECK-P9-NEXT: xscvdpsxws f0, f0
-; CHECK-P9-NEXT: mfvsrwz r3, f0
-; CHECK-P9-NEXT: mtvsrd f0, r3
+; CHECK-P9-NEXT: mffprwz r3, f0
+; CHECK-P9-NEXT: mtfprd f0, r3
; CHECK-P9-NEXT: addi r3, r1, -2
; CHECK-P9-NEXT: xxswapd v2, vs0
; CHECK-P9-NEXT: vmrglb v2, v3, v2
; CHECK-BE-LABEL: test2elt:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: xscvdpsxws f0, v2
-; CHECK-BE-NEXT: mfvsrwz r3, f0
+; CHECK-BE-NEXT: mffprwz r3, f0
; CHECK-BE-NEXT: xxswapd vs0, v2
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvdpsxws f0, f0
; CHECK-BE-NEXT: mtvsrd v3, r3
-; CHECK-BE-NEXT: mfvsrwz r3, f0
+; CHECK-BE-NEXT: mffprwz r3, f0
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v2, r3
; CHECK-BE-NEXT: addi r3, r1, -2
; CHECK-P8-NEXT: xxswapd vs1, vs1
; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: xscvdpsxws f1, f1
-; CHECK-P8-NEXT: mfvsrwz r3, f2
-; CHECK-P8-NEXT: mfvsrwz r4, f3
-; CHECK-P8-NEXT: mtvsrd f2, r3
-; CHECK-P8-NEXT: mtvsrd f3, r4
-; CHECK-P8-NEXT: mfvsrwz r3, f0
+; CHECK-P8-NEXT: mffprwz r3, f2
+; CHECK-P8-NEXT: mffprwz r4, f3
+; CHECK-P8-NEXT: mtfprd f2, r3
+; CHECK-P8-NEXT: mtfprd f3, r4
+; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: xxswapd v2, vs2
-; CHECK-P8-NEXT: mfvsrwz r4, f1
+; CHECK-P8-NEXT: mffprwz r4, f1
; CHECK-P8-NEXT: xxswapd v4, vs3
-; CHECK-P8-NEXT: mtvsrd f0, r3
-; CHECK-P8-NEXT: mtvsrd f1, r4
+; CHECK-P8-NEXT: mtfprd f0, r3
+; CHECK-P8-NEXT: mtfprd f1, r4
; CHECK-P8-NEXT: xxswapd v3, vs0
; CHECK-P8-NEXT: xxswapd v5, vs1
; CHECK-P8-NEXT: vmrglb v2, v3, v2
; CHECK-P8-NEXT: vmrglb v3, v5, v4
; CHECK-P8-NEXT: vmrglh v2, v3, v2
; CHECK-P8-NEXT: xxswapd vs0, v2
-; CHECK-P8-NEXT: mfvsrwz r3, f0
+; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: blr
;
; CHECK-P9-LABEL: test4elt:
; CHECK-P9-NEXT: xxswapd vs1, vs1
; CHECK-P9-NEXT: xscvdpsxws f1, f1
; CHECK-P9-NEXT: lxv vs0, 16(r3)
-; CHECK-P9-NEXT: mfvsrwz r3, f2
-; CHECK-P9-NEXT: mtvsrd f2, r3
-; CHECK-P9-NEXT: mfvsrwz r3, f1
+; CHECK-P9-NEXT: mffprwz r3, f2
+; CHECK-P9-NEXT: mtfprd f2, r3
+; CHECK-P9-NEXT: mffprwz r3, f1
; CHECK-P9-NEXT: xxswapd v2, vs2
-; CHECK-P9-NEXT: mtvsrd f1, r3
+; CHECK-P9-NEXT: mtfprd f1, r3
; CHECK-P9-NEXT: xxswapd v3, vs1
; CHECK-P9-NEXT: xscvdpsxws f1, f0
; CHECK-P9-NEXT: xxswapd vs0, vs0
; CHECK-P9-NEXT: xscvdpsxws f0, f0
-; CHECK-P9-NEXT: mfvsrwz r3, f1
-; CHECK-P9-NEXT: mtvsrd f1, r3
-; CHECK-P9-NEXT: mfvsrwz r3, f0
-; CHECK-P9-NEXT: mtvsrd f0, r3
+; CHECK-P9-NEXT: mffprwz r3, f1
+; CHECK-P9-NEXT: mtfprd f1, r3
+; CHECK-P9-NEXT: mffprwz r3, f0
+; CHECK-P9-NEXT: mtfprd f0, r3
; CHECK-P9-NEXT: vmrglb v2, v2, v3
; CHECK-P9-NEXT: xxswapd v3, vs1
; CHECK-P9-NEXT: xxswapd v4, vs0
; CHECK-BE-NEXT: xxswapd vs1, vs1
; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: lxv vs0, 0(r3)
-; CHECK-BE-NEXT: mfvsrwz r3, f2
+; CHECK-BE-NEXT: mffprwz r3, f2
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v2, r3
-; CHECK-BE-NEXT: mfvsrwz r3, f1
+; CHECK-BE-NEXT: mffprwz r3, f1
; CHECK-BE-NEXT: xscvdpsxws f1, f0
; CHECK-BE-NEXT: xxswapd vs0, vs0
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvdpsxws f0, f0
; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: vmrghb v2, v2, v3
-; CHECK-BE-NEXT: mfvsrwz r3, f1
+; CHECK-BE-NEXT: mffprwz r3, f1
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v3, r3
-; CHECK-BE-NEXT: mfvsrwz r3, f0
+; CHECK-BE-NEXT: mffprwz r3, f0
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: li r3, 0
; CHECK-P8-NEXT: xxswapd vs3, vs3
; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: xscvdpsxws f1, f1
-; CHECK-P8-NEXT: mfvsrwz r3, f4
+; CHECK-P8-NEXT: mffprwz r3, f4
; CHECK-P8-NEXT: xscvdpsxws f2, f2
; CHECK-P8-NEXT: xscvdpsxws f3, f3
-; CHECK-P8-NEXT: mfvsrwz r4, f5
-; CHECK-P8-NEXT: mtvsrd f4, r3
-; CHECK-P8-NEXT: mfvsrwz r3, f6
-; CHECK-P8-NEXT: mtvsrd f5, r4
+; CHECK-P8-NEXT: mffprwz r4, f5
+; CHECK-P8-NEXT: mtfprd f4, r3
+; CHECK-P8-NEXT: mffprwz r3, f6
+; CHECK-P8-NEXT: mtfprd f5, r4
; CHECK-P8-NEXT: xxswapd v2, vs4
-; CHECK-P8-NEXT: mfvsrwz r4, f7
-; CHECK-P8-NEXT: mtvsrd f6, r3
+; CHECK-P8-NEXT: mffprwz r4, f7
+; CHECK-P8-NEXT: mtfprd f6, r3
; CHECK-P8-NEXT: xxswapd v3, vs5
-; CHECK-P8-NEXT: mfvsrwz r3, f0
-; CHECK-P8-NEXT: mtvsrd f7, r4
+; CHECK-P8-NEXT: mffprwz r3, f0
+; CHECK-P8-NEXT: mtfprd f7, r4
; CHECK-P8-NEXT: xxswapd v4, vs6
-; CHECK-P8-NEXT: mfvsrwz r4, f1
-; CHECK-P8-NEXT: mtvsrd f0, r3
+; CHECK-P8-NEXT: mffprwz r4, f1
+; CHECK-P8-NEXT: mtfprd f0, r3
; CHECK-P8-NEXT: xxswapd v1, vs7
-; CHECK-P8-NEXT: mfvsrwz r3, f2
-; CHECK-P8-NEXT: mtvsrd f1, r4
+; CHECK-P8-NEXT: mffprwz r3, f2
+; CHECK-P8-NEXT: mtfprd f1, r4
; CHECK-P8-NEXT: xxswapd v5, vs0
-; CHECK-P8-NEXT: mfvsrwz r4, f3
-; CHECK-P8-NEXT: mtvsrd f2, r3
+; CHECK-P8-NEXT: mffprwz r4, f3
+; CHECK-P8-NEXT: mtfprd f2, r3
; CHECK-P8-NEXT: xxswapd v0, vs1
-; CHECK-P8-NEXT: mtvsrd f0, r4
+; CHECK-P8-NEXT: mtfprd f0, r4
; CHECK-P8-NEXT: xxswapd v6, vs2
; CHECK-P8-NEXT: vmrglb v2, v5, v2
; CHECK-P8-NEXT: xxswapd v5, vs0
; CHECK-P8-NEXT: vmrglh v3, v5, v4
; CHECK-P8-NEXT: vmrglw v2, v3, v2
; CHECK-P8-NEXT: xxswapd vs0, v2
-; CHECK-P8-NEXT: mfvsrd r3, f0
+; CHECK-P8-NEXT: mffprd r3, f0
; CHECK-P8-NEXT: blr
;
; CHECK-P9-LABEL: test8elt:
; CHECK-P9-NEXT: lxv vs0, 48(r3)
; CHECK-P9-NEXT: lxv vs1, 32(r3)
; CHECK-P9-NEXT: lxv vs2, 16(r3)
-; CHECK-P9-NEXT: mfvsrwz r3, f4
-; CHECK-P9-NEXT: mtvsrd f4, r3
-; CHECK-P9-NEXT: mfvsrwz r3, f3
+; CHECK-P9-NEXT: mffprwz r3, f4
+; CHECK-P9-NEXT: mtfprd f4, r3
+; CHECK-P9-NEXT: mffprwz r3, f3
; CHECK-P9-NEXT: xxswapd v2, vs4
-; CHECK-P9-NEXT: mtvsrd f3, r3
+; CHECK-P9-NEXT: mtfprd f3, r3
; CHECK-P9-NEXT: xxswapd v3, vs3
; CHECK-P9-NEXT: xscvdpsxws f3, f2
; CHECK-P9-NEXT: xxswapd vs2, vs2
; CHECK-P9-NEXT: xscvdpsxws f2, f2
-; CHECK-P9-NEXT: mfvsrwz r3, f3
-; CHECK-P9-NEXT: mtvsrd f3, r3
-; CHECK-P9-NEXT: mfvsrwz r3, f2
-; CHECK-P9-NEXT: mtvsrd f2, r3
+; CHECK-P9-NEXT: mffprwz r3, f3
+; CHECK-P9-NEXT: mtfprd f3, r3
+; CHECK-P9-NEXT: mffprwz r3, f2
+; CHECK-P9-NEXT: mtfprd f2, r3
; CHECK-P9-NEXT: xxswapd v4, vs2
; CHECK-P9-NEXT: xscvdpsxws f2, f1
; CHECK-P9-NEXT: xxswapd vs1, vs1
; CHECK-P9-NEXT: xscvdpsxws f1, f1
-; CHECK-P9-NEXT: mfvsrwz r3, f2
-; CHECK-P9-NEXT: mtvsrd f2, r3
-; CHECK-P9-NEXT: mfvsrwz r3, f1
+; CHECK-P9-NEXT: mffprwz r3, f2
+; CHECK-P9-NEXT: mtfprd f2, r3
+; CHECK-P9-NEXT: mffprwz r3, f1
; CHECK-P9-NEXT: vmrglb v2, v2, v3
; CHECK-P9-NEXT: xxswapd v3, vs3
; CHECK-P9-NEXT: vmrglb v3, v3, v4
; CHECK-P9-NEXT: vmrglh v2, v3, v2
; CHECK-P9-NEXT: xxswapd v3, vs2
-; CHECK-P9-NEXT: mtvsrd f1, r3
+; CHECK-P9-NEXT: mtfprd f1, r3
; CHECK-P9-NEXT: xxswapd v4, vs1
; CHECK-P9-NEXT: xscvdpsxws f1, f0
; CHECK-P9-NEXT: xxswapd vs0, vs0
; CHECK-P9-NEXT: xscvdpsxws f0, f0
-; CHECK-P9-NEXT: mfvsrwz r3, f1
-; CHECK-P9-NEXT: mtvsrd f1, r3
-; CHECK-P9-NEXT: mfvsrwz r3, f0
-; CHECK-P9-NEXT: mtvsrd f0, r3
+; CHECK-P9-NEXT: mffprwz r3, f1
+; CHECK-P9-NEXT: mtfprd f1, r3
+; CHECK-P9-NEXT: mffprwz r3, f0
+; CHECK-P9-NEXT: mtfprd f0, r3
; CHECK-P9-NEXT: vmrglb v3, v3, v4
; CHECK-P9-NEXT: xxswapd v4, vs1
; CHECK-P9-NEXT: xxswapd v5, vs0
; CHECK-BE-NEXT: lxv vs2, 32(r3)
; CHECK-BE-NEXT: lxv vs0, 0(r3)
; CHECK-BE-NEXT: lxv vs1, 16(r3)
-; CHECK-BE-NEXT: mfvsrwz r3, f4
+; CHECK-BE-NEXT: mffprwz r3, f4
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v2, r3
-; CHECK-BE-NEXT: mfvsrwz r3, f3
+; CHECK-BE-NEXT: mffprwz r3, f3
; CHECK-BE-NEXT: xscvdpsxws f3, f2
; CHECK-BE-NEXT: xxswapd vs2, vs2
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvdpsxws f2, f2
; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: vmrghb v2, v2, v3
-; CHECK-BE-NEXT: mfvsrwz r3, f3
+; CHECK-BE-NEXT: mffprwz r3, f3
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v3, r3
-; CHECK-BE-NEXT: mfvsrwz r3, f2
+; CHECK-BE-NEXT: mffprwz r3, f2
; CHECK-BE-NEXT: xscvdpsxws f2, f1
; CHECK-BE-NEXT: xxswapd vs1, vs1
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: vmrghb v3, v3, v4
-; CHECK-BE-NEXT: mfvsrwz r3, f2
+; CHECK-BE-NEXT: mffprwz r3, f2
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: vmrghh v2, v3, v2
; CHECK-BE-NEXT: mtvsrd v3, r3
-; CHECK-BE-NEXT: mfvsrwz r3, f1
+; CHECK-BE-NEXT: mffprwz r3, f1
; CHECK-BE-NEXT: xscvdpsxws f1, f0
; CHECK-BE-NEXT: xxswapd vs0, vs0
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvdpsxws f0, f0
; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: vmrghb v3, v3, v4
-; CHECK-BE-NEXT: mfvsrwz r3, f1
+; CHECK-BE-NEXT: mffprwz r3, f1
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v4, r3
-; CHECK-BE-NEXT: mfvsrwz r3, f0
+; CHECK-BE-NEXT: mffprwz r3, f0
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v5, r3
; CHECK-BE-NEXT: vmrghb v4, v4, v5
; CHECK-P8-NEXT: xxswapd vs7, vs7
; CHECK-P8-NEXT: xscvdpsxws v2, f9
; CHECK-P8-NEXT: xxswapd vs9, vs9
-; CHECK-P8-NEXT: mfvsrwz r3, f4
+; CHECK-P8-NEXT: mffprwz r3, f4
; CHECK-P8-NEXT: xscvdpsxws v3, f11
; CHECK-P8-NEXT: xxswapd vs11, vs11
-; CHECK-P8-NEXT: mfvsrwz r4, f6
+; CHECK-P8-NEXT: mffprwz r4, f6
; CHECK-P8-NEXT: xscvdpsxws f0, f0
-; CHECK-P8-NEXT: mtvsrd f4, r3
-; CHECK-P8-NEXT: mfvsrwz r3, f8
+; CHECK-P8-NEXT: mtfprd f4, r3
+; CHECK-P8-NEXT: mffprwz r3, f8
; CHECK-P8-NEXT: xscvdpsxws f1, f1
; CHECK-P8-NEXT: xxswapd v4, vs4
-; CHECK-P8-NEXT: mtvsrd f6, r4
-; CHECK-P8-NEXT: mfvsrwz r4, f10
+; CHECK-P8-NEXT: mtfprd f6, r4
+; CHECK-P8-NEXT: mffprwz r4, f10
; CHECK-P8-NEXT: xscvdpsxws f2, f2
; CHECK-P8-NEXT: xxswapd v5, vs6
-; CHECK-P8-NEXT: mtvsrd f8, r3
-; CHECK-P8-NEXT: mfvsrwz r3, f12
+; CHECK-P8-NEXT: mtfprd f8, r3
+; CHECK-P8-NEXT: mffprwz r3, f12
; CHECK-P8-NEXT: xscvdpsxws f3, f3
; CHECK-P8-NEXT: xxswapd v0, vs8
-; CHECK-P8-NEXT: mtvsrd f10, r4
-; CHECK-P8-NEXT: mfvsrwz r4, f13
+; CHECK-P8-NEXT: mtfprd f10, r4
+; CHECK-P8-NEXT: mffprwz r4, f13
; CHECK-P8-NEXT: xscvdpsxws f5, f5
; CHECK-P8-NEXT: xxswapd v1, vs10
-; CHECK-P8-NEXT: mtvsrd f12, r3
+; CHECK-P8-NEXT: mtfprd f12, r3
; CHECK-P8-NEXT: mfvsrwz r3, v2
; CHECK-P8-NEXT: xscvdpsxws f7, f7
; CHECK-P8-NEXT: xxswapd v6, vs12
-; CHECK-P8-NEXT: mtvsrd f13, r4
+; CHECK-P8-NEXT: mtfprd f13, r4
; CHECK-P8-NEXT: mfvsrwz r4, v3
; CHECK-P8-NEXT: mtvsrd v2, r3
; CHECK-P8-NEXT: xxswapd v7, vs13
-; CHECK-P8-NEXT: mfvsrwz r3, f0
+; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: xscvdpsxws f9, f9
; CHECK-P8-NEXT: xxswapd v2, v2
; CHECK-P8-NEXT: xscvdpsxws f11, f11
; CHECK-P8-NEXT: mtvsrd v3, r4
-; CHECK-P8-NEXT: mfvsrwz r4, f1
-; CHECK-P8-NEXT: mtvsrd f0, r3
+; CHECK-P8-NEXT: mffprwz r4, f1
+; CHECK-P8-NEXT: mtfprd f0, r3
; CHECK-P8-NEXT: xxswapd v3, v3
-; CHECK-P8-NEXT: mfvsrwz r3, f2
-; CHECK-P8-NEXT: mtvsrd f1, r4
+; CHECK-P8-NEXT: mffprwz r3, f2
+; CHECK-P8-NEXT: mtfprd f1, r4
; CHECK-P8-NEXT: xxswapd v8, vs0
-; CHECK-P8-NEXT: mfvsrwz r4, f3
-; CHECK-P8-NEXT: mtvsrd f2, r3
+; CHECK-P8-NEXT: mffprwz r4, f3
+; CHECK-P8-NEXT: mtfprd f2, r3
; CHECK-P8-NEXT: xxswapd v9, vs1
-; CHECK-P8-NEXT: mfvsrwz r3, f5
-; CHECK-P8-NEXT: mtvsrd f3, r4
+; CHECK-P8-NEXT: mffprwz r3, f5
+; CHECK-P8-NEXT: mtfprd f3, r4
; CHECK-P8-NEXT: xxswapd v10, vs2
-; CHECK-P8-NEXT: mfvsrwz r4, f7
-; CHECK-P8-NEXT: mtvsrd f5, r3
-; CHECK-P8-NEXT: mfvsrwz r3, f9
-; CHECK-P8-NEXT: mtvsrd f7, r4
-; CHECK-P8-NEXT: mfvsrwz r4, f11
+; CHECK-P8-NEXT: mffprwz r4, f7
+; CHECK-P8-NEXT: mtfprd f5, r3
+; CHECK-P8-NEXT: mffprwz r3, f9
+; CHECK-P8-NEXT: mtfprd f7, r4
+; CHECK-P8-NEXT: mffprwz r4, f11
; CHECK-P8-NEXT: vmrglb v4, v8, v4
; CHECK-P8-NEXT: xxswapd v8, vs3
; CHECK-P8-NEXT: vmrglb v5, v9, v5
; CHECK-P8-NEXT: xxswapd v9, vs5
-; CHECK-P8-NEXT: mtvsrd f0, r3
-; CHECK-P8-NEXT: mtvsrd f1, r4
+; CHECK-P8-NEXT: mtfprd f0, r3
+; CHECK-P8-NEXT: mtfprd f1, r4
; CHECK-P8-NEXT: vmrglb v0, v10, v0
; CHECK-P8-NEXT: xxswapd v10, vs7
; CHECK-P8-NEXT: vmrglb v1, v8, v1
; CHECK-P9-NEXT: lxv vs4, 48(r3)
; CHECK-P9-NEXT: lxv vs5, 32(r3)
; CHECK-P9-NEXT: lxv vs6, 16(r3)
-; CHECK-P9-NEXT: mfvsrwz r3, f8
-; CHECK-P9-NEXT: mtvsrd f8, r3
-; CHECK-P9-NEXT: mfvsrwz r3, f7
+; CHECK-P9-NEXT: mffprwz r3, f8
+; CHECK-P9-NEXT: mtfprd f8, r3
+; CHECK-P9-NEXT: mffprwz r3, f7
; CHECK-P9-NEXT: xxswapd v2, vs8
-; CHECK-P9-NEXT: mtvsrd f7, r3
+; CHECK-P9-NEXT: mtfprd f7, r3
; CHECK-P9-NEXT: xxswapd v3, vs7
; CHECK-P9-NEXT: xscvdpsxws f7, f6
; CHECK-P9-NEXT: xxswapd vs6, vs6
; CHECK-P9-NEXT: xscvdpsxws f6, f6
-; CHECK-P9-NEXT: mfvsrwz r3, f7
-; CHECK-P9-NEXT: mtvsrd f7, r3
-; CHECK-P9-NEXT: mfvsrwz r3, f6
-; CHECK-P9-NEXT: mtvsrd f6, r3
+; CHECK-P9-NEXT: mffprwz r3, f7
+; CHECK-P9-NEXT: mtfprd f7, r3
+; CHECK-P9-NEXT: mffprwz r3, f6
+; CHECK-P9-NEXT: mtfprd f6, r3
; CHECK-P9-NEXT: xxswapd v4, vs6
; CHECK-P9-NEXT: xscvdpsxws f6, f5
; CHECK-P9-NEXT: xxswapd vs5, vs5
; CHECK-P9-NEXT: xscvdpsxws f5, f5
-; CHECK-P9-NEXT: mfvsrwz r3, f6
-; CHECK-P9-NEXT: mtvsrd f6, r3
-; CHECK-P9-NEXT: mfvsrwz r3, f5
+; CHECK-P9-NEXT: mffprwz r3, f6
+; CHECK-P9-NEXT: mtfprd f6, r3
+; CHECK-P9-NEXT: mffprwz r3, f5
; CHECK-P9-NEXT: vmrglb v2, v2, v3
; CHECK-P9-NEXT: xxswapd v3, vs7
; CHECK-P9-NEXT: vmrglb v3, v3, v4
; CHECK-P9-NEXT: vmrglh v2, v3, v2
; CHECK-P9-NEXT: xxswapd v3, vs6
-; CHECK-P9-NEXT: mtvsrd f5, r3
+; CHECK-P9-NEXT: mtfprd f5, r3
; CHECK-P9-NEXT: xxswapd v4, vs5
; CHECK-P9-NEXT: xscvdpsxws f5, f4
; CHECK-P9-NEXT: xxswapd vs4, vs4
; CHECK-P9-NEXT: xscvdpsxws f4, f4
-; CHECK-P9-NEXT: mfvsrwz r3, f5
-; CHECK-P9-NEXT: mtvsrd f5, r3
-; CHECK-P9-NEXT: mfvsrwz r3, f4
-; CHECK-P9-NEXT: mtvsrd f4, r3
+; CHECK-P9-NEXT: mffprwz r3, f5
+; CHECK-P9-NEXT: mtfprd f5, r3
+; CHECK-P9-NEXT: mffprwz r3, f4
+; CHECK-P9-NEXT: mtfprd f4, r3
; CHECK-P9-NEXT: xxswapd v5, vs4
; CHECK-P9-NEXT: xscvdpsxws f4, f3
; CHECK-P9-NEXT: xxswapd vs3, vs3
; CHECK-P9-NEXT: xxswapd v4, vs5
; CHECK-P9-NEXT: vmrglb v4, v4, v5
; CHECK-P9-NEXT: vmrglh v3, v4, v3
-; CHECK-P9-NEXT: mfvsrwz r3, f4
-; CHECK-P9-NEXT: mtvsrd f4, r3
-; CHECK-P9-NEXT: mfvsrwz r3, f3
-; CHECK-P9-NEXT: mtvsrd f3, r3
+; CHECK-P9-NEXT: mffprwz r3, f4
+; CHECK-P9-NEXT: mtfprd f4, r3
+; CHECK-P9-NEXT: mffprwz r3, f3
+; CHECK-P9-NEXT: mtfprd f3, r3
; CHECK-P9-NEXT: xxswapd v4, vs3
; CHECK-P9-NEXT: xscvdpsxws f3, f2
; CHECK-P9-NEXT: xxswapd vs2, vs2
; CHECK-P9-NEXT: xscvdpsxws f2, f2
-; CHECK-P9-NEXT: mfvsrwz r3, f3
-; CHECK-P9-NEXT: mtvsrd f3, r3
-; CHECK-P9-NEXT: mfvsrwz r3, f2
-; CHECK-P9-NEXT: mtvsrd f2, r3
+; CHECK-P9-NEXT: mffprwz r3, f3
+; CHECK-P9-NEXT: mtfprd f3, r3
+; CHECK-P9-NEXT: mffprwz r3, f2
+; CHECK-P9-NEXT: mtfprd f2, r3
; CHECK-P9-NEXT: xxswapd v5, vs2
; CHECK-P9-NEXT: xscvdpsxws f2, f1
; CHECK-P9-NEXT: xxswapd vs1, vs1
; CHECK-P9-NEXT: xxswapd v4, vs3
; CHECK-P9-NEXT: vmrglb v4, v4, v5
; CHECK-P9-NEXT: vmrglh v3, v4, v3
-; CHECK-P9-NEXT: mfvsrwz r3, f2
-; CHECK-P9-NEXT: mtvsrd f2, r3
-; CHECK-P9-NEXT: mfvsrwz r3, f1
+; CHECK-P9-NEXT: mffprwz r3, f2
+; CHECK-P9-NEXT: mtfprd f2, r3
+; CHECK-P9-NEXT: mffprwz r3, f1
; CHECK-P9-NEXT: xxswapd v4, vs2
-; CHECK-P9-NEXT: mtvsrd f1, r3
+; CHECK-P9-NEXT: mtfprd f1, r3
; CHECK-P9-NEXT: xxswapd v5, vs1
; CHECK-P9-NEXT: xscvdpsxws f1, f0
; CHECK-P9-NEXT: xxswapd vs0, vs0
; CHECK-P9-NEXT: xscvdpsxws f0, f0
-; CHECK-P9-NEXT: mfvsrwz r3, f1
-; CHECK-P9-NEXT: mtvsrd f1, r3
-; CHECK-P9-NEXT: mfvsrwz r3, f0
-; CHECK-P9-NEXT: mtvsrd f0, r3
+; CHECK-P9-NEXT: mffprwz r3, f1
+; CHECK-P9-NEXT: mtfprd f1, r3
+; CHECK-P9-NEXT: mffprwz r3, f0
+; CHECK-P9-NEXT: mtfprd f0, r3
; CHECK-P9-NEXT: vmrglb v4, v4, v5
; CHECK-P9-NEXT: xxswapd v5, vs1
; CHECK-P9-NEXT: xxswapd v0, vs0
; CHECK-BE-NEXT: lxv vs3, 48(r3)
; CHECK-BE-NEXT: lxv vs4, 64(r3)
; CHECK-BE-NEXT: lxv vs5, 80(r3)
-; CHECK-BE-NEXT: mfvsrwz r3, f8
+; CHECK-BE-NEXT: mffprwz r3, f8
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v2, r3
-; CHECK-BE-NEXT: mfvsrwz r3, f7
+; CHECK-BE-NEXT: mffprwz r3, f7
; CHECK-BE-NEXT: xscvdpsxws f7, f6
; CHECK-BE-NEXT: xxswapd vs6, vs6
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvdpsxws f6, f6
; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: vmrghb v2, v2, v3
-; CHECK-BE-NEXT: mfvsrwz r3, f7
+; CHECK-BE-NEXT: mffprwz r3, f7
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v3, r3
-; CHECK-BE-NEXT: mfvsrwz r3, f6
+; CHECK-BE-NEXT: mffprwz r3, f6
; CHECK-BE-NEXT: xscvdpsxws f6, f5
; CHECK-BE-NEXT: xxswapd vs5, vs5
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvdpsxws f5, f5
; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: vmrghb v3, v3, v4
-; CHECK-BE-NEXT: mfvsrwz r3, f6
+; CHECK-BE-NEXT: mffprwz r3, f6
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: vmrghh v2, v3, v2
; CHECK-BE-NEXT: mtvsrd v3, r3
-; CHECK-BE-NEXT: mfvsrwz r3, f5
+; CHECK-BE-NEXT: mffprwz r3, f5
; CHECK-BE-NEXT: xscvdpsxws f5, f4
; CHECK-BE-NEXT: xxswapd vs4, vs4
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvdpsxws f4, f4
; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: vmrghb v3, v3, v4
-; CHECK-BE-NEXT: mfvsrwz r3, f5
+; CHECK-BE-NEXT: mffprwz r3, f5
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v4, r3
-; CHECK-BE-NEXT: mfvsrwz r3, f4
+; CHECK-BE-NEXT: mffprwz r3, f4
; CHECK-BE-NEXT: xscvdpsxws f4, f3
; CHECK-BE-NEXT: xxswapd vs3, vs3
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvdpsxws f3, f3
; CHECK-BE-NEXT: mtvsrd v5, r3
; CHECK-BE-NEXT: vmrghb v4, v4, v5
-; CHECK-BE-NEXT: mfvsrwz r3, f4
+; CHECK-BE-NEXT: mffprwz r3, f4
; CHECK-BE-NEXT: vmrghh v3, v4, v3
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: vmrghw v2, v3, v2
; CHECK-BE-NEXT: mtvsrd v3, r3
-; CHECK-BE-NEXT: mfvsrwz r3, f3
+; CHECK-BE-NEXT: mffprwz r3, f3
; CHECK-BE-NEXT: xscvdpsxws f3, f2
; CHECK-BE-NEXT: xxswapd vs2, vs2
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvdpsxws f2, f2
; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: vmrghb v3, v3, v4
-; CHECK-BE-NEXT: mfvsrwz r3, f3
+; CHECK-BE-NEXT: mffprwz r3, f3
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v4, r3
-; CHECK-BE-NEXT: mfvsrwz r3, f2
+; CHECK-BE-NEXT: mffprwz r3, f2
; CHECK-BE-NEXT: xscvdpsxws f2, f1
; CHECK-BE-NEXT: xxswapd vs1, vs1
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: mtvsrd v5, r3
; CHECK-BE-NEXT: vmrghb v4, v4, v5
-; CHECK-BE-NEXT: mfvsrwz r3, f2
+; CHECK-BE-NEXT: mffprwz r3, f2
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: vmrghh v3, v4, v3
; CHECK-BE-NEXT: mtvsrd v4, r3
-; CHECK-BE-NEXT: mfvsrwz r3, f1
+; CHECK-BE-NEXT: mffprwz r3, f1
; CHECK-BE-NEXT: xscvdpsxws f1, f0
; CHECK-BE-NEXT: xxswapd vs0, vs0
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvdpsxws f0, f0
; CHECK-BE-NEXT: mtvsrd v5, r3
; CHECK-BE-NEXT: vmrghb v4, v4, v5
-; CHECK-BE-NEXT: mfvsrwz r3, f1
+; CHECK-BE-NEXT: mffprwz r3, f1
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v5, r3
-; CHECK-BE-NEXT: mfvsrwz r3, f0
+; CHECK-BE-NEXT: mffprwz r3, f0
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v0, r3
; CHECK-BE-NEXT: vmrghb v5, v5, v0
; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: xscvdpsxws f1, v2
; CHECK-P8-NEXT: xscvdpsxws f0, f0
-; CHECK-P8-NEXT: mfvsrwz r3, f1
-; CHECK-P8-NEXT: mfvsrwz r4, f0
-; CHECK-P8-NEXT: mtvsrd f0, r3
-; CHECK-P8-NEXT: mtvsrd f1, r4
+; CHECK-P8-NEXT: mffprwz r3, f1
+; CHECK-P8-NEXT: mffprwz r4, f0
+; CHECK-P8-NEXT: mtfprd f0, r3
+; CHECK-P8-NEXT: mtfprd f1, r4
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: xxswapd v3, vs1
; CHECK-P8-NEXT: vmrglb v2, v2, v3
; CHECK-P8-NEXT: xxswapd vs0, v2
-; CHECK-P8-NEXT: mfvsrd r3, f0
+; CHECK-P8-NEXT: mffprd r3, f0
; CHECK-P8-NEXT: clrldi r3, r3, 48
; CHECK-P8-NEXT: sth r3, -2(r1)
; CHECK-P8-NEXT: lhz r3, -2(r1)
; CHECK-P9-LABEL: test2elt_signed:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: xscvdpsxws f0, v2
-; CHECK-P9-NEXT: mfvsrwz r3, f0
-; CHECK-P9-NEXT: mtvsrd f0, r3
+; CHECK-P9-NEXT: mffprwz r3, f0
+; CHECK-P9-NEXT: mtfprd f0, r3
; CHECK-P9-NEXT: xxswapd v3, vs0
; CHECK-P9-NEXT: xxswapd vs0, v2
; CHECK-P9-NEXT: xscvdpsxws f0, f0
-; CHECK-P9-NEXT: mfvsrwz r3, f0
-; CHECK-P9-NEXT: mtvsrd f0, r3
+; CHECK-P9-NEXT: mffprwz r3, f0
+; CHECK-P9-NEXT: mtfprd f0, r3
; CHECK-P9-NEXT: addi r3, r1, -2
; CHECK-P9-NEXT: xxswapd v2, vs0
; CHECK-P9-NEXT: vmrglb v2, v3, v2
; CHECK-BE-LABEL: test2elt_signed:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: xscvdpsxws f0, v2
-; CHECK-BE-NEXT: mfvsrwz r3, f0
+; CHECK-BE-NEXT: mffprwz r3, f0
; CHECK-BE-NEXT: xxswapd vs0, v2
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvdpsxws f0, f0
; CHECK-BE-NEXT: mtvsrd v3, r3
-; CHECK-BE-NEXT: mfvsrwz r3, f0
+; CHECK-BE-NEXT: mffprwz r3, f0
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v2, r3
; CHECK-BE-NEXT: addi r3, r1, -2
; CHECK-P8-NEXT: xxswapd vs1, vs1
; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: xscvdpsxws f1, f1
-; CHECK-P8-NEXT: mfvsrwz r3, f2
-; CHECK-P8-NEXT: mfvsrwz r4, f3
-; CHECK-P8-NEXT: mtvsrd f2, r3
-; CHECK-P8-NEXT: mtvsrd f3, r4
-; CHECK-P8-NEXT: mfvsrwz r3, f0
+; CHECK-P8-NEXT: mffprwz r3, f2
+; CHECK-P8-NEXT: mffprwz r4, f3
+; CHECK-P8-NEXT: mtfprd f2, r3
+; CHECK-P8-NEXT: mtfprd f3, r4
+; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: xxswapd v2, vs2
-; CHECK-P8-NEXT: mfvsrwz r4, f1
+; CHECK-P8-NEXT: mffprwz r4, f1
; CHECK-P8-NEXT: xxswapd v4, vs3
-; CHECK-P8-NEXT: mtvsrd f0, r3
-; CHECK-P8-NEXT: mtvsrd f1, r4
+; CHECK-P8-NEXT: mtfprd f0, r3
+; CHECK-P8-NEXT: mtfprd f1, r4
; CHECK-P8-NEXT: xxswapd v3, vs0
; CHECK-P8-NEXT: xxswapd v5, vs1
; CHECK-P8-NEXT: vmrglb v2, v3, v2
; CHECK-P8-NEXT: vmrglb v3, v5, v4
; CHECK-P8-NEXT: vmrglh v2, v3, v2
; CHECK-P8-NEXT: xxswapd vs0, v2
-; CHECK-P8-NEXT: mfvsrwz r3, f0
+; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: blr
;
; CHECK-P9-LABEL: test4elt_signed:
; CHECK-P9-NEXT: xxswapd vs1, vs1
; CHECK-P9-NEXT: xscvdpsxws f1, f1
; CHECK-P9-NEXT: lxv vs0, 16(r3)
-; CHECK-P9-NEXT: mfvsrwz r3, f2
-; CHECK-P9-NEXT: mtvsrd f2, r3
-; CHECK-P9-NEXT: mfvsrwz r3, f1
+; CHECK-P9-NEXT: mffprwz r3, f2
+; CHECK-P9-NEXT: mtfprd f2, r3
+; CHECK-P9-NEXT: mffprwz r3, f1
; CHECK-P9-NEXT: xxswapd v2, vs2
-; CHECK-P9-NEXT: mtvsrd f1, r3
+; CHECK-P9-NEXT: mtfprd f1, r3
; CHECK-P9-NEXT: xxswapd v3, vs1
; CHECK-P9-NEXT: xscvdpsxws f1, f0
; CHECK-P9-NEXT: xxswapd vs0, vs0
; CHECK-P9-NEXT: xscvdpsxws f0, f0
-; CHECK-P9-NEXT: mfvsrwz r3, f1
-; CHECK-P9-NEXT: mtvsrd f1, r3
-; CHECK-P9-NEXT: mfvsrwz r3, f0
-; CHECK-P9-NEXT: mtvsrd f0, r3
+; CHECK-P9-NEXT: mffprwz r3, f1
+; CHECK-P9-NEXT: mtfprd f1, r3
+; CHECK-P9-NEXT: mffprwz r3, f0
+; CHECK-P9-NEXT: mtfprd f0, r3
; CHECK-P9-NEXT: vmrglb v2, v2, v3
; CHECK-P9-NEXT: xxswapd v3, vs1
; CHECK-P9-NEXT: xxswapd v4, vs0
; CHECK-BE-NEXT: xxswapd vs1, vs1
; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: lxv vs0, 0(r3)
-; CHECK-BE-NEXT: mfvsrwz r3, f2
+; CHECK-BE-NEXT: mffprwz r3, f2
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v2, r3
-; CHECK-BE-NEXT: mfvsrwz r3, f1
+; CHECK-BE-NEXT: mffprwz r3, f1
; CHECK-BE-NEXT: xscvdpsxws f1, f0
; CHECK-BE-NEXT: xxswapd vs0, vs0
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvdpsxws f0, f0
; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: vmrghb v2, v2, v3
-; CHECK-BE-NEXT: mfvsrwz r3, f1
+; CHECK-BE-NEXT: mffprwz r3, f1
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v3, r3
-; CHECK-BE-NEXT: mfvsrwz r3, f0
+; CHECK-BE-NEXT: mffprwz r3, f0
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: li r3, 0
; CHECK-P8-NEXT: xxswapd vs3, vs3
; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: xscvdpsxws f1, f1
-; CHECK-P8-NEXT: mfvsrwz r3, f4
+; CHECK-P8-NEXT: mffprwz r3, f4
; CHECK-P8-NEXT: xscvdpsxws f2, f2
; CHECK-P8-NEXT: xscvdpsxws f3, f3
-; CHECK-P8-NEXT: mfvsrwz r4, f5
-; CHECK-P8-NEXT: mtvsrd f4, r3
-; CHECK-P8-NEXT: mfvsrwz r3, f6
-; CHECK-P8-NEXT: mtvsrd f5, r4
+; CHECK-P8-NEXT: mffprwz r4, f5
+; CHECK-P8-NEXT: mtfprd f4, r3
+; CHECK-P8-NEXT: mffprwz r3, f6
+; CHECK-P8-NEXT: mtfprd f5, r4
; CHECK-P8-NEXT: xxswapd v2, vs4
-; CHECK-P8-NEXT: mfvsrwz r4, f7
-; CHECK-P8-NEXT: mtvsrd f6, r3
+; CHECK-P8-NEXT: mffprwz r4, f7
+; CHECK-P8-NEXT: mtfprd f6, r3
; CHECK-P8-NEXT: xxswapd v3, vs5
-; CHECK-P8-NEXT: mfvsrwz r3, f0
-; CHECK-P8-NEXT: mtvsrd f7, r4
+; CHECK-P8-NEXT: mffprwz r3, f0
+; CHECK-P8-NEXT: mtfprd f7, r4
; CHECK-P8-NEXT: xxswapd v4, vs6
-; CHECK-P8-NEXT: mfvsrwz r4, f1
-; CHECK-P8-NEXT: mtvsrd f0, r3
+; CHECK-P8-NEXT: mffprwz r4, f1
+; CHECK-P8-NEXT: mtfprd f0, r3
; CHECK-P8-NEXT: xxswapd v1, vs7
-; CHECK-P8-NEXT: mfvsrwz r3, f2
-; CHECK-P8-NEXT: mtvsrd f1, r4
+; CHECK-P8-NEXT: mffprwz r3, f2
+; CHECK-P8-NEXT: mtfprd f1, r4
; CHECK-P8-NEXT: xxswapd v5, vs0
-; CHECK-P8-NEXT: mfvsrwz r4, f3
-; CHECK-P8-NEXT: mtvsrd f2, r3
+; CHECK-P8-NEXT: mffprwz r4, f3
+; CHECK-P8-NEXT: mtfprd f2, r3
; CHECK-P8-NEXT: xxswapd v0, vs1
-; CHECK-P8-NEXT: mtvsrd f0, r4
+; CHECK-P8-NEXT: mtfprd f0, r4
; CHECK-P8-NEXT: xxswapd v6, vs2
; CHECK-P8-NEXT: vmrglb v2, v5, v2
; CHECK-P8-NEXT: xxswapd v5, vs0
; CHECK-P8-NEXT: vmrglh v3, v5, v4
; CHECK-P8-NEXT: vmrglw v2, v3, v2
; CHECK-P8-NEXT: xxswapd vs0, v2
-; CHECK-P8-NEXT: mfvsrd r3, f0
+; CHECK-P8-NEXT: mffprd r3, f0
; CHECK-P8-NEXT: blr
;
; CHECK-P9-LABEL: test8elt_signed:
; CHECK-P9-NEXT: lxv vs0, 48(r3)
; CHECK-P9-NEXT: lxv vs1, 32(r3)
; CHECK-P9-NEXT: lxv vs2, 16(r3)
-; CHECK-P9-NEXT: mfvsrwz r3, f4
-; CHECK-P9-NEXT: mtvsrd f4, r3
-; CHECK-P9-NEXT: mfvsrwz r3, f3
+; CHECK-P9-NEXT: mffprwz r3, f4
+; CHECK-P9-NEXT: mtfprd f4, r3
+; CHECK-P9-NEXT: mffprwz r3, f3
; CHECK-P9-NEXT: xxswapd v2, vs4
-; CHECK-P9-NEXT: mtvsrd f3, r3
+; CHECK-P9-NEXT: mtfprd f3, r3
; CHECK-P9-NEXT: xxswapd v3, vs3
; CHECK-P9-NEXT: xscvdpsxws f3, f2
; CHECK-P9-NEXT: xxswapd vs2, vs2
; CHECK-P9-NEXT: xscvdpsxws f2, f2
-; CHECK-P9-NEXT: mfvsrwz r3, f3
-; CHECK-P9-NEXT: mtvsrd f3, r3
-; CHECK-P9-NEXT: mfvsrwz r3, f2
-; CHECK-P9-NEXT: mtvsrd f2, r3
+; CHECK-P9-NEXT: mffprwz r3, f3
+; CHECK-P9-NEXT: mtfprd f3, r3
+; CHECK-P9-NEXT: mffprwz r3, f2
+; CHECK-P9-NEXT: mtfprd f2, r3
; CHECK-P9-NEXT: xxswapd v4, vs2
; CHECK-P9-NEXT: xscvdpsxws f2, f1
; CHECK-P9-NEXT: xxswapd vs1, vs1
; CHECK-P9-NEXT: xscvdpsxws f1, f1
-; CHECK-P9-NEXT: mfvsrwz r3, f2
-; CHECK-P9-NEXT: mtvsrd f2, r3
-; CHECK-P9-NEXT: mfvsrwz r3, f1
+; CHECK-P9-NEXT: mffprwz r3, f2
+; CHECK-P9-NEXT: mtfprd f2, r3
+; CHECK-P9-NEXT: mffprwz r3, f1
; CHECK-P9-NEXT: vmrglb v2, v2, v3
; CHECK-P9-NEXT: xxswapd v3, vs3
; CHECK-P9-NEXT: vmrglb v3, v3, v4
; CHECK-P9-NEXT: vmrglh v2, v3, v2
; CHECK-P9-NEXT: xxswapd v3, vs2
-; CHECK-P9-NEXT: mtvsrd f1, r3
+; CHECK-P9-NEXT: mtfprd f1, r3
; CHECK-P9-NEXT: xxswapd v4, vs1
; CHECK-P9-NEXT: xscvdpsxws f1, f0
; CHECK-P9-NEXT: xxswapd vs0, vs0
; CHECK-P9-NEXT: xscvdpsxws f0, f0
-; CHECK-P9-NEXT: mfvsrwz r3, f1
-; CHECK-P9-NEXT: mtvsrd f1, r3
-; CHECK-P9-NEXT: mfvsrwz r3, f0
-; CHECK-P9-NEXT: mtvsrd f0, r3
+; CHECK-P9-NEXT: mffprwz r3, f1
+; CHECK-P9-NEXT: mtfprd f1, r3
+; CHECK-P9-NEXT: mffprwz r3, f0
+; CHECK-P9-NEXT: mtfprd f0, r3
; CHECK-P9-NEXT: vmrglb v3, v3, v4
; CHECK-P9-NEXT: xxswapd v4, vs1
; CHECK-P9-NEXT: xxswapd v5, vs0
; CHECK-BE-NEXT: lxv vs2, 32(r3)
; CHECK-BE-NEXT: lxv vs0, 0(r3)
; CHECK-BE-NEXT: lxv vs1, 16(r3)
-; CHECK-BE-NEXT: mfvsrwz r3, f4
+; CHECK-BE-NEXT: mffprwz r3, f4
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v2, r3
-; CHECK-BE-NEXT: mfvsrwz r3, f3
+; CHECK-BE-NEXT: mffprwz r3, f3
; CHECK-BE-NEXT: xscvdpsxws f3, f2
; CHECK-BE-NEXT: xxswapd vs2, vs2
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvdpsxws f2, f2
; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: vmrghb v2, v2, v3
-; CHECK-BE-NEXT: mfvsrwz r3, f3
+; CHECK-BE-NEXT: mffprwz r3, f3
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v3, r3
-; CHECK-BE-NEXT: mfvsrwz r3, f2
+; CHECK-BE-NEXT: mffprwz r3, f2
; CHECK-BE-NEXT: xscvdpsxws f2, f1
; CHECK-BE-NEXT: xxswapd vs1, vs1
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: vmrghb v3, v3, v4
-; CHECK-BE-NEXT: mfvsrwz r3, f2
+; CHECK-BE-NEXT: mffprwz r3, f2
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: vmrghh v2, v3, v2
; CHECK-BE-NEXT: mtvsrd v3, r3
-; CHECK-BE-NEXT: mfvsrwz r3, f1
+; CHECK-BE-NEXT: mffprwz r3, f1
; CHECK-BE-NEXT: xscvdpsxws f1, f0
; CHECK-BE-NEXT: xxswapd vs0, vs0
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvdpsxws f0, f0
; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: vmrghb v3, v3, v4
-; CHECK-BE-NEXT: mfvsrwz r3, f1
+; CHECK-BE-NEXT: mffprwz r3, f1
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v4, r3
-; CHECK-BE-NEXT: mfvsrwz r3, f0
+; CHECK-BE-NEXT: mffprwz r3, f0
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v5, r3
; CHECK-BE-NEXT: vmrghb v4, v4, v5
; CHECK-P8-NEXT: xxswapd vs7, vs7
; CHECK-P8-NEXT: xscvdpsxws v2, f9
; CHECK-P8-NEXT: xxswapd vs9, vs9
-; CHECK-P8-NEXT: mfvsrwz r3, f4
+; CHECK-P8-NEXT: mffprwz r3, f4
; CHECK-P8-NEXT: xscvdpsxws v3, f11
; CHECK-P8-NEXT: xxswapd vs11, vs11
-; CHECK-P8-NEXT: mfvsrwz r4, f6
+; CHECK-P8-NEXT: mffprwz r4, f6
; CHECK-P8-NEXT: xscvdpsxws f0, f0
-; CHECK-P8-NEXT: mtvsrd f4, r3
-; CHECK-P8-NEXT: mfvsrwz r3, f8
+; CHECK-P8-NEXT: mtfprd f4, r3
+; CHECK-P8-NEXT: mffprwz r3, f8
; CHECK-P8-NEXT: xscvdpsxws f1, f1
; CHECK-P8-NEXT: xxswapd v4, vs4
-; CHECK-P8-NEXT: mtvsrd f6, r4
-; CHECK-P8-NEXT: mfvsrwz r4, f10
+; CHECK-P8-NEXT: mtfprd f6, r4
+; CHECK-P8-NEXT: mffprwz r4, f10
; CHECK-P8-NEXT: xscvdpsxws f2, f2
; CHECK-P8-NEXT: xxswapd v5, vs6
-; CHECK-P8-NEXT: mtvsrd f8, r3
-; CHECK-P8-NEXT: mfvsrwz r3, f12
+; CHECK-P8-NEXT: mtfprd f8, r3
+; CHECK-P8-NEXT: mffprwz r3, f12
; CHECK-P8-NEXT: xscvdpsxws f3, f3
; CHECK-P8-NEXT: xxswapd v0, vs8
-; CHECK-P8-NEXT: mtvsrd f10, r4
-; CHECK-P8-NEXT: mfvsrwz r4, f13
+; CHECK-P8-NEXT: mtfprd f10, r4
+; CHECK-P8-NEXT: mffprwz r4, f13
; CHECK-P8-NEXT: xscvdpsxws f5, f5
; CHECK-P8-NEXT: xxswapd v1, vs10
-; CHECK-P8-NEXT: mtvsrd f12, r3
+; CHECK-P8-NEXT: mtfprd f12, r3
; CHECK-P8-NEXT: mfvsrwz r3, v2
; CHECK-P8-NEXT: xscvdpsxws f7, f7
; CHECK-P8-NEXT: xxswapd v6, vs12
-; CHECK-P8-NEXT: mtvsrd f13, r4
+; CHECK-P8-NEXT: mtfprd f13, r4
; CHECK-P8-NEXT: mfvsrwz r4, v3
; CHECK-P8-NEXT: mtvsrd v2, r3
; CHECK-P8-NEXT: xxswapd v7, vs13
-; CHECK-P8-NEXT: mfvsrwz r3, f0
+; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: xscvdpsxws f9, f9
; CHECK-P8-NEXT: xxswapd v2, v2
; CHECK-P8-NEXT: xscvdpsxws f11, f11
; CHECK-P8-NEXT: mtvsrd v3, r4
-; CHECK-P8-NEXT: mfvsrwz r4, f1
-; CHECK-P8-NEXT: mtvsrd f0, r3
+; CHECK-P8-NEXT: mffprwz r4, f1
+; CHECK-P8-NEXT: mtfprd f0, r3
; CHECK-P8-NEXT: xxswapd v3, v3
-; CHECK-P8-NEXT: mfvsrwz r3, f2
-; CHECK-P8-NEXT: mtvsrd f1, r4
+; CHECK-P8-NEXT: mffprwz r3, f2
+; CHECK-P8-NEXT: mtfprd f1, r4
; CHECK-P8-NEXT: xxswapd v8, vs0
-; CHECK-P8-NEXT: mfvsrwz r4, f3
-; CHECK-P8-NEXT: mtvsrd f2, r3
+; CHECK-P8-NEXT: mffprwz r4, f3
+; CHECK-P8-NEXT: mtfprd f2, r3
; CHECK-P8-NEXT: xxswapd v9, vs1
-; CHECK-P8-NEXT: mfvsrwz r3, f5
-; CHECK-P8-NEXT: mtvsrd f3, r4
+; CHECK-P8-NEXT: mffprwz r3, f5
+; CHECK-P8-NEXT: mtfprd f3, r4
; CHECK-P8-NEXT: xxswapd v10, vs2
-; CHECK-P8-NEXT: mfvsrwz r4, f7
-; CHECK-P8-NEXT: mtvsrd f5, r3
-; CHECK-P8-NEXT: mfvsrwz r3, f9
-; CHECK-P8-NEXT: mtvsrd f7, r4
-; CHECK-P8-NEXT: mfvsrwz r4, f11
+; CHECK-P8-NEXT: mffprwz r4, f7
+; CHECK-P8-NEXT: mtfprd f5, r3
+; CHECK-P8-NEXT: mffprwz r3, f9
+; CHECK-P8-NEXT: mtfprd f7, r4
+; CHECK-P8-NEXT: mffprwz r4, f11
; CHECK-P8-NEXT: vmrglb v4, v8, v4
; CHECK-P8-NEXT: xxswapd v8, vs3
; CHECK-P8-NEXT: vmrglb v5, v9, v5
; CHECK-P8-NEXT: xxswapd v9, vs5
-; CHECK-P8-NEXT: mtvsrd f0, r3
-; CHECK-P8-NEXT: mtvsrd f1, r4
+; CHECK-P8-NEXT: mtfprd f0, r3
+; CHECK-P8-NEXT: mtfprd f1, r4
; CHECK-P8-NEXT: vmrglb v0, v10, v0
; CHECK-P8-NEXT: xxswapd v10, vs7
; CHECK-P8-NEXT: vmrglb v1, v8, v1
; CHECK-P9-NEXT: lxv vs4, 48(r3)
; CHECK-P9-NEXT: lxv vs5, 32(r3)
; CHECK-P9-NEXT: lxv vs6, 16(r3)
-; CHECK-P9-NEXT: mfvsrwz r3, f8
-; CHECK-P9-NEXT: mtvsrd f8, r3
-; CHECK-P9-NEXT: mfvsrwz r3, f7
+; CHECK-P9-NEXT: mffprwz r3, f8
+; CHECK-P9-NEXT: mtfprd f8, r3
+; CHECK-P9-NEXT: mffprwz r3, f7
; CHECK-P9-NEXT: xxswapd v2, vs8
-; CHECK-P9-NEXT: mtvsrd f7, r3
+; CHECK-P9-NEXT: mtfprd f7, r3
; CHECK-P9-NEXT: xxswapd v3, vs7
; CHECK-P9-NEXT: xscvdpsxws f7, f6
; CHECK-P9-NEXT: xxswapd vs6, vs6
; CHECK-P9-NEXT: xscvdpsxws f6, f6
-; CHECK-P9-NEXT: mfvsrwz r3, f7
-; CHECK-P9-NEXT: mtvsrd f7, r3
-; CHECK-P9-NEXT: mfvsrwz r3, f6
-; CHECK-P9-NEXT: mtvsrd f6, r3
+; CHECK-P9-NEXT: mffprwz r3, f7
+; CHECK-P9-NEXT: mtfprd f7, r3
+; CHECK-P9-NEXT: mffprwz r3, f6
+; CHECK-P9-NEXT: mtfprd f6, r3
; CHECK-P9-NEXT: xxswapd v4, vs6
; CHECK-P9-NEXT: xscvdpsxws f6, f5
; CHECK-P9-NEXT: xxswapd vs5, vs5
; CHECK-P9-NEXT: xscvdpsxws f5, f5
-; CHECK-P9-NEXT: mfvsrwz r3, f6
-; CHECK-P9-NEXT: mtvsrd f6, r3
-; CHECK-P9-NEXT: mfvsrwz r3, f5
+; CHECK-P9-NEXT: mffprwz r3, f6
+; CHECK-P9-NEXT: mtfprd f6, r3
+; CHECK-P9-NEXT: mffprwz r3, f5
; CHECK-P9-NEXT: vmrglb v2, v2, v3
; CHECK-P9-NEXT: xxswapd v3, vs7
; CHECK-P9-NEXT: vmrglb v3, v3, v4
; CHECK-P9-NEXT: vmrglh v2, v3, v2
; CHECK-P9-NEXT: xxswapd v3, vs6
-; CHECK-P9-NEXT: mtvsrd f5, r3
+; CHECK-P9-NEXT: mtfprd f5, r3
; CHECK-P9-NEXT: xxswapd v4, vs5
; CHECK-P9-NEXT: xscvdpsxws f5, f4
; CHECK-P9-NEXT: xxswapd vs4, vs4
; CHECK-P9-NEXT: xscvdpsxws f4, f4
-; CHECK-P9-NEXT: mfvsrwz r3, f5
-; CHECK-P9-NEXT: mtvsrd f5, r3
-; CHECK-P9-NEXT: mfvsrwz r3, f4
-; CHECK-P9-NEXT: mtvsrd f4, r3
+; CHECK-P9-NEXT: mffprwz r3, f5
+; CHECK-P9-NEXT: mtfprd f5, r3
+; CHECK-P9-NEXT: mffprwz r3, f4
+; CHECK-P9-NEXT: mtfprd f4, r3
; CHECK-P9-NEXT: xxswapd v5, vs4
; CHECK-P9-NEXT: xscvdpsxws f4, f3
; CHECK-P9-NEXT: xxswapd vs3, vs3
; CHECK-P9-NEXT: xxswapd v4, vs5
; CHECK-P9-NEXT: vmrglb v4, v4, v5
; CHECK-P9-NEXT: vmrglh v3, v4, v3
-; CHECK-P9-NEXT: mfvsrwz r3, f4
-; CHECK-P9-NEXT: mtvsrd f4, r3
-; CHECK-P9-NEXT: mfvsrwz r3, f3
-; CHECK-P9-NEXT: mtvsrd f3, r3
+; CHECK-P9-NEXT: mffprwz r3, f4
+; CHECK-P9-NEXT: mtfprd f4, r3
+; CHECK-P9-NEXT: mffprwz r3, f3
+; CHECK-P9-NEXT: mtfprd f3, r3
; CHECK-P9-NEXT: xxswapd v4, vs3
; CHECK-P9-NEXT: xscvdpsxws f3, f2
; CHECK-P9-NEXT: xxswapd vs2, vs2
; CHECK-P9-NEXT: xscvdpsxws f2, f2
-; CHECK-P9-NEXT: mfvsrwz r3, f3
-; CHECK-P9-NEXT: mtvsrd f3, r3
-; CHECK-P9-NEXT: mfvsrwz r3, f2
-; CHECK-P9-NEXT: mtvsrd f2, r3
+; CHECK-P9-NEXT: mffprwz r3, f3
+; CHECK-P9-NEXT: mtfprd f3, r3
+; CHECK-P9-NEXT: mffprwz r3, f2
+; CHECK-P9-NEXT: mtfprd f2, r3
; CHECK-P9-NEXT: xxswapd v5, vs2
; CHECK-P9-NEXT: xscvdpsxws f2, f1
; CHECK-P9-NEXT: xxswapd vs1, vs1
; CHECK-P9-NEXT: xxswapd v4, vs3
; CHECK-P9-NEXT: vmrglb v4, v4, v5
; CHECK-P9-NEXT: vmrglh v3, v4, v3
-; CHECK-P9-NEXT: mfvsrwz r3, f2
-; CHECK-P9-NEXT: mtvsrd f2, r3
-; CHECK-P9-NEXT: mfvsrwz r3, f1
+; CHECK-P9-NEXT: mffprwz r3, f2
+; CHECK-P9-NEXT: mtfprd f2, r3
+; CHECK-P9-NEXT: mffprwz r3, f1
; CHECK-P9-NEXT: xxswapd v4, vs2
-; CHECK-P9-NEXT: mtvsrd f1, r3
+; CHECK-P9-NEXT: mtfprd f1, r3
; CHECK-P9-NEXT: xxswapd v5, vs1
; CHECK-P9-NEXT: xscvdpsxws f1, f0
; CHECK-P9-NEXT: xxswapd vs0, vs0
; CHECK-P9-NEXT: xscvdpsxws f0, f0
-; CHECK-P9-NEXT: mfvsrwz r3, f1
-; CHECK-P9-NEXT: mtvsrd f1, r3
-; CHECK-P9-NEXT: mfvsrwz r3, f0
-; CHECK-P9-NEXT: mtvsrd f0, r3
+; CHECK-P9-NEXT: mffprwz r3, f1
+; CHECK-P9-NEXT: mtfprd f1, r3
+; CHECK-P9-NEXT: mffprwz r3, f0
+; CHECK-P9-NEXT: mtfprd f0, r3
; CHECK-P9-NEXT: vmrglb v4, v4, v5
; CHECK-P9-NEXT: xxswapd v5, vs1
; CHECK-P9-NEXT: xxswapd v0, vs0
; CHECK-BE-NEXT: lxv vs3, 48(r3)
; CHECK-BE-NEXT: lxv vs4, 64(r3)
; CHECK-BE-NEXT: lxv vs5, 80(r3)
-; CHECK-BE-NEXT: mfvsrwz r3, f8
+; CHECK-BE-NEXT: mffprwz r3, f8
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v2, r3
-; CHECK-BE-NEXT: mfvsrwz r3, f7
+; CHECK-BE-NEXT: mffprwz r3, f7
; CHECK-BE-NEXT: xscvdpsxws f7, f6
; CHECK-BE-NEXT: xxswapd vs6, vs6
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvdpsxws f6, f6
; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: vmrghb v2, v2, v3
-; CHECK-BE-NEXT: mfvsrwz r3, f7
+; CHECK-BE-NEXT: mffprwz r3, f7
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v3, r3
-; CHECK-BE-NEXT: mfvsrwz r3, f6
+; CHECK-BE-NEXT: mffprwz r3, f6
; CHECK-BE-NEXT: xscvdpsxws f6, f5
; CHECK-BE-NEXT: xxswapd vs5, vs5
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvdpsxws f5, f5
; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: vmrghb v3, v3, v4
-; CHECK-BE-NEXT: mfvsrwz r3, f6
+; CHECK-BE-NEXT: mffprwz r3, f6
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: vmrghh v2, v3, v2
; CHECK-BE-NEXT: mtvsrd v3, r3
-; CHECK-BE-NEXT: mfvsrwz r3, f5
+; CHECK-BE-NEXT: mffprwz r3, f5
; CHECK-BE-NEXT: xscvdpsxws f5, f4
; CHECK-BE-NEXT: xxswapd vs4, vs4
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvdpsxws f4, f4
; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: vmrghb v3, v3, v4
-; CHECK-BE-NEXT: mfvsrwz r3, f5
+; CHECK-BE-NEXT: mffprwz r3, f5
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v4, r3
-; CHECK-BE-NEXT: mfvsrwz r3, f4
+; CHECK-BE-NEXT: mffprwz r3, f4
; CHECK-BE-NEXT: xscvdpsxws f4, f3
; CHECK-BE-NEXT: xxswapd vs3, vs3
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvdpsxws f3, f3
; CHECK-BE-NEXT: mtvsrd v5, r3
; CHECK-BE-NEXT: vmrghb v4, v4, v5
-; CHECK-BE-NEXT: mfvsrwz r3, f4
+; CHECK-BE-NEXT: mffprwz r3, f4
; CHECK-BE-NEXT: vmrghh v3, v4, v3
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: vmrghw v2, v3, v2
; CHECK-BE-NEXT: mtvsrd v3, r3
-; CHECK-BE-NEXT: mfvsrwz r3, f3
+; CHECK-BE-NEXT: mffprwz r3, f3
; CHECK-BE-NEXT: xscvdpsxws f3, f2
; CHECK-BE-NEXT: xxswapd vs2, vs2
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvdpsxws f2, f2
; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: vmrghb v3, v3, v4
-; CHECK-BE-NEXT: mfvsrwz r3, f3
+; CHECK-BE-NEXT: mffprwz r3, f3
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v4, r3
-; CHECK-BE-NEXT: mfvsrwz r3, f2
+; CHECK-BE-NEXT: mffprwz r3, f2
; CHECK-BE-NEXT: xscvdpsxws f2, f1
; CHECK-BE-NEXT: xxswapd vs1, vs1
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: mtvsrd v5, r3
; CHECK-BE-NEXT: vmrghb v4, v4, v5
-; CHECK-BE-NEXT: mfvsrwz r3, f2
+; CHECK-BE-NEXT: mffprwz r3, f2
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: vmrghh v3, v4, v3
; CHECK-BE-NEXT: mtvsrd v4, r3
-; CHECK-BE-NEXT: mfvsrwz r3, f1
+; CHECK-BE-NEXT: mffprwz r3, f1
; CHECK-BE-NEXT: xscvdpsxws f1, f0
; CHECK-BE-NEXT: xxswapd vs0, vs0
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvdpsxws f0, f0
; CHECK-BE-NEXT: mtvsrd v5, r3
; CHECK-BE-NEXT: vmrghb v4, v4, v5
-; CHECK-BE-NEXT: mfvsrwz r3, f1
+; CHECK-BE-NEXT: mffprwz r3, f1
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v5, r3
-; CHECK-BE-NEXT: mfvsrwz r3, f0
+; CHECK-BE-NEXT: mffprwz r3, f0
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v0, r3
; CHECK-BE-NEXT: vmrghb v5, v5, v0
define i64 @test2elt(i64 %a.coerce) local_unnamed_addr #0 {
; CHECK-P8-LABEL: test2elt:
; CHECK-P8: # %bb.0: # %entry
-; CHECK-P8-NEXT: mtvsrd f0, r3
+; CHECK-P8-NEXT: mtfprd f0, r3
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: xvcvspuxws vs0, v2
; CHECK-P8-NEXT: xxswapd vs0, vs0
-; CHECK-P8-NEXT: mfvsrd r3, f0
+; CHECK-P8-NEXT: mffprd r3, f0
; CHECK-P8-NEXT: blr
;
; CHECK-P9-LABEL: test2elt:
; CHECK-P9: # %bb.0: # %entry
-; CHECK-P9-NEXT: mtvsrd f0, r3
+; CHECK-P9-NEXT: mtfprd f0, r3
; CHECK-P9-NEXT: xxswapd v2, vs0
; CHECK-P9-NEXT: xvcvspuxws vs0, v2
; CHECK-P9-NEXT: mfvsrld r3, vs0
;
; CHECK-BE-LABEL: test2elt:
; CHECK-BE: # %bb.0: # %entry
-; CHECK-BE-NEXT: mtvsrd f0, r3
+; CHECK-BE-NEXT: mtfprd f0, r3
; CHECK-BE-NEXT: xvcvspuxws vs0, vs0
-; CHECK-BE-NEXT: mfvsrd r3, f0
+; CHECK-BE-NEXT: mffprd r3, f0
; CHECK-BE-NEXT: blr
entry:
%0 = bitcast i64 %a.coerce to <2 x float>
define i64 @test2elt_signed(i64 %a.coerce) local_unnamed_addr #0 {
; CHECK-P8-LABEL: test2elt_signed:
; CHECK-P8: # %bb.0: # %entry
-; CHECK-P8-NEXT: mtvsrd f0, r3
+; CHECK-P8-NEXT: mtfprd f0, r3
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: xvcvspsxws vs0, v2
; CHECK-P8-NEXT: xxswapd vs0, vs0
-; CHECK-P8-NEXT: mfvsrd r3, f0
+; CHECK-P8-NEXT: mffprd r3, f0
; CHECK-P8-NEXT: blr
;
; CHECK-P9-LABEL: test2elt_signed:
; CHECK-P9: # %bb.0: # %entry
-; CHECK-P9-NEXT: mtvsrd f0, r3
+; CHECK-P9-NEXT: mtfprd f0, r3
; CHECK-P9-NEXT: xxswapd v2, vs0
; CHECK-P9-NEXT: xvcvspsxws vs0, v2
; CHECK-P9-NEXT: mfvsrld r3, vs0
;
; CHECK-BE-LABEL: test2elt_signed:
; CHECK-BE: # %bb.0: # %entry
-; CHECK-BE-NEXT: mtvsrd f0, r3
+; CHECK-BE-NEXT: mtfprd f0, r3
; CHECK-BE-NEXT: xvcvspsxws vs0, vs0
-; CHECK-BE-NEXT: mfvsrd r3, f0
+; CHECK-BE-NEXT: mffprd r3, f0
; CHECK-BE-NEXT: blr
entry:
%0 = bitcast i64 %a.coerce to <2 x float>
define i64 @test2elt(i32 %a.coerce) local_unnamed_addr #0 {
; CHECK-P8-LABEL: test2elt:
; CHECK-P8: # %bb.0: # %entry
-; CHECK-P8-NEXT: mtvsrd f0, r3
-; CHECK-P8-NEXT: mfvsrd r3, f0
+; CHECK-P8-NEXT: mtfprd f0, r3
+; CHECK-P8-NEXT: mffprd r3, f0
; CHECK-P8-NEXT: clrldi r4, r3, 48
; CHECK-P8-NEXT: rldicl r3, r3, 48, 48
-; CHECK-P8-NEXT: rlwinm r4, r4, 0, 16, 31
-; CHECK-P8-NEXT: rlwinm r3, r3, 0, 16, 31
+; CHECK-P8-NEXT: clrlwi r4, r4, 16
+; CHECK-P8-NEXT: clrlwi r3, r3, 16
; CHECK-P8-NEXT: mtfprwz f0, r4
; CHECK-P8-NEXT: mtfprwz f1, r3
; CHECK-P8-NEXT: xscvuxdsp f0, f0
; CHECK-P8-NEXT: xxsldwi v3, vs1, vs1, 1
; CHECK-P8-NEXT: vmrglw v2, v3, v2
; CHECK-P8-NEXT: xxswapd vs0, v2
-; CHECK-P8-NEXT: mfvsrd r3, f0
+; CHECK-P8-NEXT: mffprd r3, f0
; CHECK-P8-NEXT: blr
;
; CHECK-P9-LABEL: test2elt:
; CHECK-P9-NEXT: mtvsrws v2, r3
; CHECK-P9-NEXT: li r3, 0
; CHECK-P9-NEXT: vextuhrx r3, r3, v2
-; CHECK-P9-NEXT: rlwinm r3, r3, 0, 16, 31
+; CHECK-P9-NEXT: clrlwi r3, r3, 16
; CHECK-P9-NEXT: mtfprwz f0, r3
; CHECK-P9-NEXT: li r3, 2
; CHECK-P9-NEXT: xscvuxdsp f0, f0
; CHECK-P9-NEXT: xscvdpspn vs0, f0
; CHECK-P9-NEXT: vextuhrx r3, r3, v2
-; CHECK-P9-NEXT: rlwinm r3, r3, 0, 16, 31
+; CHECK-P9-NEXT: clrlwi r3, r3, 16
; CHECK-P9-NEXT: xxsldwi v3, vs0, vs0, 1
; CHECK-P9-NEXT: mtfprwz f0, r3
; CHECK-P9-NEXT: xscvuxdsp f0, f0
; CHECK-BE-NEXT: mtvsrws v2, r3
; CHECK-BE-NEXT: li r3, 2
; CHECK-BE-NEXT: vextuhlx r3, r3, v2
-; CHECK-BE-NEXT: rlwinm r3, r3, 0, 16, 31
+; CHECK-BE-NEXT: clrlwi r3, r3, 16
; CHECK-BE-NEXT: mtfprwz f0, r3
; CHECK-BE-NEXT: li r3, 0
; CHECK-BE-NEXT: xscvuxdsp f0, f0
; CHECK-BE-NEXT: vextuhlx r3, r3, v2
-; CHECK-BE-NEXT: rlwinm r3, r3, 0, 16, 31
+; CHECK-BE-NEXT: clrlwi r3, r3, 16
; CHECK-BE-NEXT: xscvdpspn v3, f0
; CHECK-BE-NEXT: mtfprwz f0, r3
; CHECK-BE-NEXT: xscvuxdsp f0, f0
; CHECK-P8-LABEL: test4elt:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: addis r4, r2, .LCPI1_0@toc@ha
-; CHECK-P8-NEXT: mtvsrd f0, r3
+; CHECK-P8-NEXT: mtfprd f0, r3
; CHECK-P8-NEXT: addi r3, r4, .LCPI1_0@toc@l
; CHECK-P8-NEXT: xxlxor v4, v4, v4
; CHECK-P8-NEXT: xxswapd v2, vs0
;
; CHECK-P9-LABEL: test4elt:
; CHECK-P9: # %bb.0: # %entry
-; CHECK-P9-NEXT: mtvsrd f0, r3
+; CHECK-P9-NEXT: mtfprd f0, r3
; CHECK-P9-NEXT: addis r3, r2, .LCPI1_0@toc@ha
; CHECK-P9-NEXT: addi r3, r3, .LCPI1_0@toc@l
; CHECK-P9-NEXT: lxvx v3, 0, r3
define i64 @test2elt_signed(i32 %a.coerce) local_unnamed_addr #0 {
; CHECK-P8-LABEL: test2elt_signed:
; CHECK-P8: # %bb.0: # %entry
-; CHECK-P8-NEXT: mtvsrd f0, r3
-; CHECK-P8-NEXT: mfvsrd r3, f0
+; CHECK-P8-NEXT: mtfprd f0, r3
+; CHECK-P8-NEXT: mffprd r3, f0
; CHECK-P8-NEXT: clrldi r4, r3, 48
; CHECK-P8-NEXT: rldicl r3, r3, 48, 48
; CHECK-P8-NEXT: extsh r4, r4
; CHECK-P8-NEXT: xxsldwi v3, vs1, vs1, 1
; CHECK-P8-NEXT: vmrglw v2, v3, v2
; CHECK-P8-NEXT: xxswapd vs0, v2
-; CHECK-P8-NEXT: mfvsrd r3, f0
+; CHECK-P8-NEXT: mffprd r3, f0
; CHECK-P8-NEXT: blr
;
; CHECK-P9-LABEL: test2elt_signed:
define <4 x float> @test4elt_signed(i64 %a.coerce) local_unnamed_addr #1 {
; CHECK-P8-LABEL: test4elt_signed:
; CHECK-P8: # %bb.0: # %entry
-; CHECK-P8-NEXT: mtvsrd f0, r3
+; CHECK-P8-NEXT: mtfprd f0, r3
; CHECK-P8-NEXT: vspltisw v3, 8
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: vadduwm v3, v3, v3
;
; CHECK-P9-LABEL: test4elt_signed:
; CHECK-P9: # %bb.0: # %entry
-; CHECK-P9-NEXT: mtvsrd f0, r3
+; CHECK-P9-NEXT: mtfprd f0, r3
; CHECK-P9-NEXT: xxswapd v2, vs0
; CHECK-P9-NEXT: vmrglh v2, v2, v2
; CHECK-P9-NEXT: vextsh2w v2, v2
; CHECK-P8-LABEL: test2elt:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: addis r4, r2, .LCPI0_0@toc@ha
-; CHECK-P8-NEXT: mtvsrd f0, r3
+; CHECK-P8-NEXT: mtfprd f0, r3
; CHECK-P8-NEXT: addi r3, r4, .LCPI0_0@toc@l
; CHECK-P8-NEXT: xxlxor v4, v4, v4
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-LABEL: test4elt:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: addis r5, r2, .LCPI1_0@toc@ha
-; CHECK-P8-NEXT: mtvsrd f0, r4
+; CHECK-P8-NEXT: mtfprd f0, r4
; CHECK-P8-NEXT: addis r4, r2, .LCPI1_1@toc@ha
; CHECK-P8-NEXT: addi r5, r5, .LCPI1_0@toc@l
; CHECK-P8-NEXT: addi r4, r4, .LCPI1_1@toc@l
;
; CHECK-P9-LABEL: test4elt:
; CHECK-P9: # %bb.0: # %entry
-; CHECK-P9-NEXT: mtvsrd f0, r4
+; CHECK-P9-NEXT: mtfprd f0, r4
; CHECK-P9-NEXT: addis r4, r2, .LCPI1_0@toc@ha
; CHECK-P9-NEXT: addi r4, r4, .LCPI1_0@toc@l
; CHECK-P9-NEXT: lxvx v3, 0, r4
; CHECK-P8-LABEL: test2elt_signed:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: addis r4, r2, .LCPI4_0@toc@ha
-; CHECK-P8-NEXT: mtvsrd f0, r3
+; CHECK-P8-NEXT: mtfprd f0, r3
; CHECK-P8-NEXT: addi r3, r4, .LCPI4_0@toc@l
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: lvx v3, 0, r3
; CHECK-P8-LABEL: test4elt_signed:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: addis r5, r2, .LCPI5_0@toc@ha
-; CHECK-P8-NEXT: mtvsrd f0, r4
+; CHECK-P8-NEXT: mtfprd f0, r4
; CHECK-P8-NEXT: addis r4, r2, .LCPI5_2@toc@ha
; CHECK-P8-NEXT: addi r5, r5, .LCPI5_0@toc@l
; CHECK-P8-NEXT: addi r4, r4, .LCPI5_2@toc@l
;
; CHECK-P9-LABEL: test4elt_signed:
; CHECK-P9: # %bb.0: # %entry
-; CHECK-P9-NEXT: mtvsrd f0, r4
+; CHECK-P9-NEXT: mtfprd f0, r4
; CHECK-P9-NEXT: addis r4, r2, .LCPI5_0@toc@ha
; CHECK-P9-NEXT: addi r4, r4, .LCPI5_0@toc@l
; CHECK-P9-NEXT: lxvx v3, 0, r4
define <2 x double> @test2elt(i64 %a.coerce) local_unnamed_addr #0 {
; CHECK-P8-LABEL: test2elt:
; CHECK-P8: # %bb.0: # %entry
-; CHECK-P8-NEXT: mtvsrd f0, r3
+; CHECK-P8-NEXT: mtfprd f0, r3
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: xxmrglw v2, v2, v2
; CHECK-P8-NEXT: xvcvuxwdp v2, v2
;
; CHECK-P9-LABEL: test2elt:
; CHECK-P9: # %bb.0: # %entry
-; CHECK-P9-NEXT: mtvsrd f0, r3
+; CHECK-P9-NEXT: mtfprd f0, r3
; CHECK-P9-NEXT: xxswapd v2, vs0
; CHECK-P9-NEXT: xxmrglw v2, v2, v2
; CHECK-P9-NEXT: xvcvuxwdp v2, v2
;
; CHECK-BE-LABEL: test2elt:
; CHECK-BE: # %bb.0: # %entry
-; CHECK-BE-NEXT: mtvsrd f0, r3
+; CHECK-BE-NEXT: mtfprd f0, r3
; CHECK-BE-NEXT: xxmrghw v2, vs0, vs0
; CHECK-BE-NEXT: xvcvuxwdp v2, v2
; CHECK-BE-NEXT: blr
define <2 x double> @test2elt_signed(i64 %a.coerce) local_unnamed_addr #0 {
; CHECK-P8-LABEL: test2elt_signed:
; CHECK-P8: # %bb.0: # %entry
-; CHECK-P8-NEXT: mtvsrd f0, r3
+; CHECK-P8-NEXT: mtfprd f0, r3
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: xxmrglw v2, v2, v2
; CHECK-P8-NEXT: xvcvsxwdp v2, v2
;
; CHECK-P9-LABEL: test2elt_signed:
; CHECK-P9: # %bb.0: # %entry
-; CHECK-P9-NEXT: mtvsrd f0, r3
+; CHECK-P9-NEXT: mtfprd f0, r3
; CHECK-P9-NEXT: xxswapd v2, vs0
; CHECK-P9-NEXT: xxmrglw v2, v2, v2
; CHECK-P9-NEXT: xvcvsxwdp v2, v2
;
; CHECK-BE-LABEL: test2elt_signed:
; CHECK-BE: # %bb.0: # %entry
-; CHECK-BE-NEXT: mtvsrd f0, r3
+; CHECK-BE-NEXT: mtfprd f0, r3
; CHECK-BE-NEXT: xxmrghw v2, vs0, vs0
; CHECK-BE-NEXT: xvcvsxwdp v2, v2
; CHECK-BE-NEXT: blr
; CHECK-P8-NEXT: xxsldwi v2, vs0, vs0, 1
; CHECK-P8-NEXT: vmrglw v2, v3, v2
; CHECK-P8-NEXT: xxswapd vs0, v2
-; CHECK-P8-NEXT: mfvsrd r3, f0
+; CHECK-P8-NEXT: mffprd r3, f0
; CHECK-P8-NEXT: blr
;
; CHECK-P9-LABEL: test2elt:
; CHECK-P8-NEXT: xxsldwi v2, vs0, vs0, 1
; CHECK-P8-NEXT: vmrglw v2, v3, v2
; CHECK-P8-NEXT: xxswapd vs0, v2
-; CHECK-P8-NEXT: mfvsrd r3, f0
+; CHECK-P8-NEXT: mffprd r3, f0
; CHECK-P8-NEXT: blr
;
; CHECK-P9-LABEL: test2elt_signed:
define i64 @test2elt(i16 %a.coerce) local_unnamed_addr #0 {
; CHECK-P8-LABEL: test2elt:
; CHECK-P8: # %bb.0: # %entry
-; CHECK-P8-NEXT: mtvsrd f0, r3
-; CHECK-P8-NEXT: mfvsrd r3, f0
+; CHECK-P8-NEXT: mtfprd f0, r3
+; CHECK-P8-NEXT: mffprd r3, f0
; CHECK-P8-NEXT: clrldi r4, r3, 56
; CHECK-P8-NEXT: rldicl r3, r3, 56, 56
-; CHECK-P8-NEXT: rlwinm r4, r4, 0, 24, 31
-; CHECK-P8-NEXT: rlwinm r3, r3, 0, 24, 31
+; CHECK-P8-NEXT: clrlwi r4, r4, 24
+; CHECK-P8-NEXT: clrlwi r3, r3, 24
; CHECK-P8-NEXT: mtfprwz f0, r4
; CHECK-P8-NEXT: mtfprwz f1, r3
; CHECK-P8-NEXT: xscvuxdsp f0, f0
; CHECK-P8-NEXT: xxsldwi v3, vs1, vs1, 1
; CHECK-P8-NEXT: vmrglw v2, v3, v2
; CHECK-P8-NEXT: xxswapd vs0, v2
-; CHECK-P8-NEXT: mfvsrd r3, f0
+; CHECK-P8-NEXT: mffprd r3, f0
; CHECK-P8-NEXT: blr
;
; CHECK-P9-LABEL: test2elt:
; CHECK-P9-NEXT: mtvsrws v2, r3
; CHECK-P9-NEXT: li r3, 0
; CHECK-P9-NEXT: vextubrx r3, r3, v2
-; CHECK-P9-NEXT: rlwinm r3, r3, 0, 24, 31
+; CHECK-P9-NEXT: clrlwi r3, r3, 24
; CHECK-P9-NEXT: mtfprwz f0, r3
; CHECK-P9-NEXT: li r3, 1
; CHECK-P9-NEXT: xscvuxdsp f0, f0
; CHECK-P9-NEXT: xscvdpspn vs0, f0
; CHECK-P9-NEXT: vextubrx r3, r3, v2
-; CHECK-P9-NEXT: rlwinm r3, r3, 0, 24, 31
+; CHECK-P9-NEXT: clrlwi r3, r3, 24
; CHECK-P9-NEXT: xxsldwi v3, vs0, vs0, 1
; CHECK-P9-NEXT: mtfprwz f0, r3
; CHECK-P9-NEXT: xscvuxdsp f0, f0
; CHECK-BE-NEXT: mtvsrws v2, r3
; CHECK-BE-NEXT: li r3, 1
; CHECK-BE-NEXT: vextublx r3, r3, v2
-; CHECK-BE-NEXT: rlwinm r3, r3, 0, 24, 31
+; CHECK-BE-NEXT: clrlwi r3, r3, 24
; CHECK-BE-NEXT: mtfprwz f0, r3
; CHECK-BE-NEXT: li r3, 0
; CHECK-BE-NEXT: xscvuxdsp f0, f0
; CHECK-BE-NEXT: vextublx r3, r3, v2
-; CHECK-BE-NEXT: rlwinm r3, r3, 0, 24, 31
+; CHECK-BE-NEXT: clrlwi r3, r3, 24
; CHECK-BE-NEXT: xscvdpspn v3, f0
; CHECK-BE-NEXT: mtfprwz f0, r3
; CHECK-BE-NEXT: xscvuxdsp f0, f0
; CHECK-P8-LABEL: test4elt:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: addis r4, r2, .LCPI1_0@toc@ha
-; CHECK-P8-NEXT: mtvsrd f0, r3
+; CHECK-P8-NEXT: mtfprd f0, r3
; CHECK-P8-NEXT: addi r3, r4, .LCPI1_0@toc@l
; CHECK-P8-NEXT: xxlxor v4, v4, v4
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-LABEL: test8elt:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: addis r5, r2, .LCPI2_0@toc@ha
-; CHECK-P8-NEXT: mtvsrd f0, r4
+; CHECK-P8-NEXT: mtfprd f0, r4
; CHECK-P8-NEXT: addis r4, r2, .LCPI2_1@toc@ha
; CHECK-P8-NEXT: addi r5, r5, .LCPI2_0@toc@l
; CHECK-P8-NEXT: addi r4, r4, .LCPI2_1@toc@l
;
; CHECK-P9-LABEL: test8elt:
; CHECK-P9: # %bb.0: # %entry
-; CHECK-P9-NEXT: mtvsrd f0, r4
+; CHECK-P9-NEXT: mtfprd f0, r4
; CHECK-P9-NEXT: addis r4, r2, .LCPI2_0@toc@ha
; CHECK-P9-NEXT: addi r4, r4, .LCPI2_0@toc@l
; CHECK-P9-NEXT: lxvx v3, 0, r4
define i64 @test2elt_signed(i16 %a.coerce) local_unnamed_addr #0 {
; CHECK-P8-LABEL: test2elt_signed:
; CHECK-P8: # %bb.0: # %entry
-; CHECK-P8-NEXT: mtvsrd f0, r3
-; CHECK-P8-NEXT: mfvsrd r3, f0
+; CHECK-P8-NEXT: mtfprd f0, r3
+; CHECK-P8-NEXT: mffprd r3, f0
; CHECK-P8-NEXT: clrldi r4, r3, 56
; CHECK-P8-NEXT: rldicl r3, r3, 56, 56
; CHECK-P8-NEXT: extsb r4, r4
; CHECK-P8-NEXT: xxsldwi v3, vs1, vs1, 1
; CHECK-P8-NEXT: vmrglw v2, v3, v2
; CHECK-P8-NEXT: xxswapd vs0, v2
-; CHECK-P8-NEXT: mfvsrd r3, f0
+; CHECK-P8-NEXT: mffprd r3, f0
; CHECK-P8-NEXT: blr
;
; CHECK-P9-LABEL: test2elt_signed:
; CHECK-P8-LABEL: test4elt_signed:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: addis r4, r2, .LCPI5_0@toc@ha
-; CHECK-P8-NEXT: mtvsrd f0, r3
+; CHECK-P8-NEXT: mtfprd f0, r3
; CHECK-P8-NEXT: addi r3, r4, .LCPI5_0@toc@l
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: lvx v3, 0, r3
; CHECK-P8-LABEL: test8elt_signed:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: addis r5, r2, .LCPI6_0@toc@ha
-; CHECK-P8-NEXT: mtvsrd f0, r4
+; CHECK-P8-NEXT: mtfprd f0, r4
; CHECK-P8-NEXT: addis r4, r2, .LCPI6_1@toc@ha
; CHECK-P8-NEXT: vspltisw v5, 12
; CHECK-P8-NEXT: addi r5, r5, .LCPI6_0@toc@l
;
; CHECK-P9-LABEL: test8elt_signed:
; CHECK-P9: # %bb.0: # %entry
-; CHECK-P9-NEXT: mtvsrd f0, r4
+; CHECK-P9-NEXT: mtfprd f0, r4
; CHECK-P9-NEXT: addis r4, r2, .LCPI6_0@toc@ha
; CHECK-P9-NEXT: addi r4, r4, .LCPI6_0@toc@l
; CHECK-P9-NEXT: lxvx v3, 0, r4
; CHECK-P8-LABEL: test2elt:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: addis r4, r2, .LCPI0_0@toc@ha
-; CHECK-P8-NEXT: mtvsrd f0, r3
+; CHECK-P8-NEXT: mtfprd f0, r3
; CHECK-P8-NEXT: addi r3, r4, .LCPI0_0@toc@l
; CHECK-P8-NEXT: xxlxor v4, v4, v4
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-LABEL: test4elt:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: addis r5, r2, .LCPI1_0@toc@ha
-; CHECK-P8-NEXT: mtvsrd f0, r4
+; CHECK-P8-NEXT: mtfprd f0, r4
; CHECK-P8-NEXT: addis r4, r2, .LCPI1_1@toc@ha
; CHECK-P8-NEXT: addi r5, r5, .LCPI1_0@toc@l
; CHECK-P8-NEXT: addi r4, r4, .LCPI1_1@toc@l
; CHECK-P8-LABEL: test8elt:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: addis r5, r2, .LCPI2_0@toc@ha
-; CHECK-P8-NEXT: mtvsrd f0, r4
+; CHECK-P8-NEXT: mtfprd f0, r4
; CHECK-P8-NEXT: addis r4, r2, .LCPI2_2@toc@ha
; CHECK-P8-NEXT: addi r5, r5, .LCPI2_0@toc@l
; CHECK-P8-NEXT: addi r4, r4, .LCPI2_2@toc@l
;
; CHECK-P9-LABEL: test8elt:
; CHECK-P9: # %bb.0: # %entry
-; CHECK-P9-NEXT: mtvsrd f0, r4
+; CHECK-P9-NEXT: mtfprd f0, r4
; CHECK-P9-NEXT: addis r4, r2, .LCPI2_0@toc@ha
; CHECK-P9-NEXT: addi r4, r4, .LCPI2_0@toc@l
; CHECK-P9-NEXT: lxvx v3, 0, r4
; CHECK-P8-LABEL: test2elt_signed:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: addis r4, r2, .LCPI4_0@toc@ha
-; CHECK-P8-NEXT: mtvsrd f0, r3
+; CHECK-P8-NEXT: mtfprd f0, r3
; CHECK-P8-NEXT: addi r3, r4, .LCPI4_0@toc@l
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: lvx v3, 0, r3
; CHECK-P8-LABEL: test4elt_signed:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: addis r5, r2, .LCPI5_0@toc@ha
-; CHECK-P8-NEXT: mtvsrd f0, r4
+; CHECK-P8-NEXT: mtfprd f0, r4
; CHECK-P8-NEXT: addis r4, r2, .LCPI5_2@toc@ha
; CHECK-P8-NEXT: addi r5, r5, .LCPI5_0@toc@l
; CHECK-P8-NEXT: addi r4, r4, .LCPI5_2@toc@l
define void @test8elt_signed(<8 x double>* noalias nocapture sret %agg.result, i64 %a.coerce) local_unnamed_addr #1 {
; CHECK-P8-LABEL: test8elt_signed:
; CHECK-P8: # %bb.0: # %entry
-; CHECK-P8-NEXT: mtvsrd f0, r4
+; CHECK-P8-NEXT: mtfprd f0, r4
; CHECK-P8-NEXT: addis r4, r2, .LCPI6_2@toc@ha
; CHECK-P8-NEXT: addis r5, r2, .LCPI6_0@toc@ha
; CHECK-P8-NEXT: addis r6, r2, .LCPI6_3@toc@ha
;
; CHECK-P9-LABEL: test8elt_signed:
; CHECK-P9: # %bb.0: # %entry
-; CHECK-P9-NEXT: mtvsrd f0, r4
+; CHECK-P9-NEXT: mtfprd f0, r4
; CHECK-P9-NEXT: addis r4, r2, .LCPI6_0@toc@ha
; CHECK-P9-NEXT: addi r4, r4, .LCPI6_0@toc@l
; CHECK-P9-NEXT: lxvx v3, 0, r4
define i64 @test2elt(i64 %a.coerce) local_unnamed_addr #0 {
; CHECK-P8-LABEL: test2elt:
; CHECK-P8: # %bb.0: # %entry
-; CHECK-P8-NEXT: mtvsrd f0, r3
+; CHECK-P8-NEXT: mtfprd f0, r3
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: xvcvuxwsp vs0, v2
; CHECK-P8-NEXT: xxswapd vs0, vs0
-; CHECK-P8-NEXT: mfvsrd r3, f0
+; CHECK-P8-NEXT: mffprd r3, f0
; CHECK-P8-NEXT: blr
;
; CHECK-P9-LABEL: test2elt:
; CHECK-P9: # %bb.0: # %entry
-; CHECK-P9-NEXT: mtvsrd f0, r3
+; CHECK-P9-NEXT: mtfprd f0, r3
; CHECK-P9-NEXT: xxswapd v2, vs0
; CHECK-P9-NEXT: xvcvuxwsp vs0, v2
; CHECK-P9-NEXT: mfvsrld r3, vs0
;
; CHECK-BE-LABEL: test2elt:
; CHECK-BE: # %bb.0: # %entry
-; CHECK-BE-NEXT: mtvsrd f0, r3
+; CHECK-BE-NEXT: mtfprd f0, r3
; CHECK-BE-NEXT: xvcvuxwsp vs0, vs0
-; CHECK-BE-NEXT: mfvsrd r3, f0
+; CHECK-BE-NEXT: mffprd r3, f0
; CHECK-BE-NEXT: blr
entry:
%0 = bitcast i64 %a.coerce to <2 x i32>
define i64 @test2elt_signed(i64 %a.coerce) local_unnamed_addr #0 {
; CHECK-P8-LABEL: test2elt_signed:
; CHECK-P8: # %bb.0: # %entry
-; CHECK-P8-NEXT: mtvsrd f0, r3
+; CHECK-P8-NEXT: mtfprd f0, r3
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: xvcvsxwsp vs0, v2
; CHECK-P8-NEXT: xxswapd vs0, vs0
-; CHECK-P8-NEXT: mfvsrd r3, f0
+; CHECK-P8-NEXT: mffprd r3, f0
; CHECK-P8-NEXT: blr
;
; CHECK-P9-LABEL: test2elt_signed:
; CHECK-P9: # %bb.0: # %entry
-; CHECK-P9-NEXT: mtvsrd f0, r3
+; CHECK-P9-NEXT: mtfprd f0, r3
; CHECK-P9-NEXT: xxswapd v2, vs0
; CHECK-P9-NEXT: xvcvsxwsp vs0, v2
; CHECK-P9-NEXT: mfvsrld r3, vs0
;
; CHECK-BE-LABEL: test2elt_signed:
; CHECK-BE: # %bb.0: # %entry
-; CHECK-BE-NEXT: mtvsrd f0, r3
+; CHECK-BE-NEXT: mtfprd f0, r3
; CHECK-BE-NEXT: xvcvsxwsp vs0, vs0
-; CHECK-BE-NEXT: mfvsrd r3, f0
+; CHECK-BE-NEXT: mffprd r3, f0
; CHECK-BE-NEXT: blr
entry:
%0 = bitcast i64 %a.coerce to <2 x i32>
;
; CHECK-LE-LABEL: test80:
; CHECK-LE: # %bb.0:
-; CHECK-LE-NEXT: mtvsrd f0, r3
+; CHECK-LE-NEXT: mtfprd f0, r3
; CHECK-LE-NEXT: addis r4, r2, .LCPI65_0@toc@ha
; CHECK-LE-NEXT: addi r3, r4, .LCPI65_0@toc@l
; CHECK-LE-NEXT: xxswapd vs0, vs0
define void @Foo(i32 signext %a, i32 signext %b) #0 {
; CHECK-LABEL: @Foo
-; CHECK: cmpw [[CR:[0-9]+]]
-; CHECK-NEXT: ble [[CR]], [[LABEL:\.[a-zA-Z0-9]+]]
+; CHECK: cmpw
+; CHECK-NEXT: ble 0, [[LABEL:\.[a-zA-Z0-9]+]]
; CHECK-NEXT: .p2align 3
; CHECK-NEXT: {{\.[a-zA-Z0-9]+}}:
; CHECK-NEXT: blr
define void @Foo2(i32 signext %a, i32 signext %b) #0 {
; CHECK-LABEL: @Foo2
-; CHECK: cmpw [[CR:[0-9]+]]
-; CHECK-NEXT: bge [[CR]], [[LABEL:\.[a-zA-Z0-9]+]]
+; CHECK: cmpw
+; CHECK-NEXT: bge 0, [[LABEL:\.[a-zA-Z0-9]+]]
; CHECK-NEXT: .p2align 3
; CHECK-NEXT: {{\.[a-zA-Z0-9]+}}:
; CHECK-NEXT: blr