case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTER_BUFFERS:
case PIPE_CAP_TGSI_ATOMFADD:
case PIPE_CAP_TGSI_SKIP_SHRINK_IO_ARRAYS:
+ case PIPE_CAP_IMAGE_LOAD_FORMATTED:
return 0;
case PIPE_CAP_MAX_GS_INVOCATIONS:
arrays should be skipped and enforce keeping the declared array sizes instead.
A driver might rely on the input mapping that was defined with the original
GLSL code.
+* ``PIPE_CAP_IMAGE_LOAD_FORMATTED``: True if a format for image loads does not need to be specified in the shader IR
.. _pipe_capf:
case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE:
case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS:
case PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS:
+ case PIPE_CAP_IMAGE_LOAD_FORMATTED:
return 0;
case PIPE_CAP_MAX_GS_INVOCATIONS:
case PIPE_CAP_GLSL_TESS_LEVELS_AS_INPUTS:
case PIPE_CAP_NIR_COMPACT_ARRAYS:
case PIPE_CAP_COMPUTE:
+ case PIPE_CAP_IMAGE_LOAD_FORMATTED:
return 0;
case PIPE_CAP_VENDOR_ID:
case PIPE_CAP_RGB_OVERRIDE_DST_ALPHA_BLEND:
case PIPE_CAP_GLSL_TESS_LEVELS_AS_INPUTS:
case PIPE_CAP_NIR_COMPACT_ARRAYS:
+ case PIPE_CAP_IMAGE_LOAD_FORMATTED:
return 0;
case PIPE_CAP_VENDOR_ID:
case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS:
case PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS:
case PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET:
+ case PIPE_CAP_IMAGE_LOAD_FORMATTED:
return 0;
case PIPE_CAP_MAX_GS_INVOCATIONS:
return 32;
case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
+ case PIPE_SHADER_CAP_IMAGE_LOAD_FORMATTED:
return 0;
case PIPE_SHADER_CAP_SCALAR_ISA:
return 1;
PIPE_CAP_COMPUTE_GRID_INFO_LAST_BLOCK,
PIPE_CAP_COMPUTE_SHADER_DERIVATIVES,
PIPE_CAP_TGSI_SKIP_SHRINK_IO_ARRAYS,
+ PIPE_CAP_IMAGE_LOAD_FORMATTED,
};
/**