iommu/arm-smmu: Convert GR1 registers to bitfields

As for GR0, use the bitfield helpers to make GR1 usage a little cleaner,
and use it as an opportunity to audit and tidy the definitions. This
tweaks the handling of CBAR types to match what we did for S2CR a while
back, and fixes a couple of names which didn't quite match the latest
architecture spec (IHI0062D.c).

Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Will Deacon <will@kernel.org>

diff --git a/drivers/iommu/arm-smmu-regs.h b/drivers/iommu/arm-smmu-regs.h
index 351ab09..8522330 100644 (file)
--- a/drivers/iommu/arm-smmu-regs.h
+++ b/drivers/iommu/arm-smmu-regs.h
@@ -108,30 +108,25 @@ enum arm_smmu_s2cr_type {
 
 /* Context bank attribute registers */
 #define ARM_SMMU_GR1_CBAR(n)           (0x0 + ((n) << 2))
-#define CBAR_VMID_SHIFT                        0
-#define CBAR_VMID_MASK                 0xff
-#define CBAR_S1_BPSHCFG_SHIFT          8
-#define CBAR_S1_BPSHCFG_MASK           3
-#define CBAR_S1_BPSHCFG_NSH            3
-#define CBAR_S1_MEMATTR_SHIFT          12
-#define CBAR_S1_MEMATTR_MASK           0xf
+#define CBAR_IRPTNDX                   GENMASK(31, 24)
+#define CBAR_TYPE                      GENMASK(17, 16)
+enum arm_smmu_cbar_type {
+       CBAR_TYPE_S2_TRANS,
+       CBAR_TYPE_S1_TRANS_S2_BYPASS,
+       CBAR_TYPE_S1_TRANS_S2_FAULT,
+       CBAR_TYPE_S1_TRANS_S2_TRANS,
+};
+#define CBAR_S1_MEMATTR                        GENMASK(15, 12)
 #define CBAR_S1_MEMATTR_WB             0xf
-#define CBAR_TYPE_SHIFT                        16
-#define CBAR_TYPE_MASK                 0x3
-#define CBAR_TYPE_S2_TRANS             (0 << CBAR_TYPE_SHIFT)
-#define CBAR_TYPE_S1_TRANS_S2_BYPASS   (1 << CBAR_TYPE_SHIFT)
-#define CBAR_TYPE_S1_TRANS_S2_FAULT    (2 << CBAR_TYPE_SHIFT)
-#define CBAR_TYPE_S1_TRANS_S2_TRANS    (3 << CBAR_TYPE_SHIFT)
-#define CBAR_IRPTNDX_SHIFT             24
-#define CBAR_IRPTNDX_MASK              0xff
+#define CBAR_S1_BPSHCFG                        GENMASK(9, 8)
+#define CBAR_S1_BPSHCFG_NSH            3
+#define CBAR_VMID                      GENMASK(7, 0)
 
 #define ARM_SMMU_GR1_CBFRSYNRA(n)      (0x400 + ((n) << 2))
 
 #define ARM_SMMU_GR1_CBA2R(n)          (0x800 + ((n) << 2))
-#define CBA2R_RW64_32BIT               (0 << 0)
-#define CBA2R_RW64_64BIT               (1 << 0)
-#define CBA2R_VMID_SHIFT               16
-#define CBA2R_VMID_MASK                        0xffff
+#define CBA2R_VMID16                   GENMASK(31, 16)
+#define CBA2R_VA64                     BIT(0)
 
 #define ARM_SMMU_CB_SCTLR              0x0
 #define ARM_SMMU_CB_ACTLR              0x4

diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
index 1050157..293a95b 100644 (file)
--- a/drivers/iommu/arm-smmu.c
+++ b/drivers/iommu/arm-smmu.c
@@ -237,7 +237,7 @@ struct arm_smmu_cfg {
                u16                     asid;
                u16                     vmid;
        };
-       u32                             cbar;
+       enum arm_smmu_cbar_type         cbar;
        enum arm_smmu_context_fmt       fmt;
 };
 #define INVALID_IRPTNDX                        0xff
@@ -692,31 +692,31 @@ static void arm_smmu_write_context_bank(struct arm_smmu_device *smmu, int idx)
        /* CBA2R */
        if (smmu->version > ARM_SMMU_V1) {
                if (cfg->fmt == ARM_SMMU_CTX_FMT_AARCH64)
-                       reg = CBA2R_RW64_64BIT;
+                       reg = CBA2R_VA64;
                else
-                       reg = CBA2R_RW64_32BIT;
+                       reg = 0;
                /* 16-bit VMIDs live in CBA2R */
                if (smmu->features & ARM_SMMU_FEAT_VMID16)
-                       reg |= cfg->vmid << CBA2R_VMID_SHIFT;
+                       reg |= FIELD_PREP(CBA2R_VMID16, cfg->vmid);
 
                writel_relaxed(reg, gr1_base + ARM_SMMU_GR1_CBA2R(idx));
        }
 
        /* CBAR */
-       reg = cfg->cbar;
+       reg = FIELD_PREP(CBAR_TYPE, cfg->cbar);
        if (smmu->version < ARM_SMMU_V2)
-               reg |= cfg->irptndx << CBAR_IRPTNDX_SHIFT;
+               reg |= FIELD_PREP(CBAR_IRPTNDX, cfg->irptndx);
 
        /*
         * Use the weakest shareability/memory types, so they are
         * overridden by the ttbcr/pte.
         */
        if (stage1) {
-               reg |= (CBAR_S1_BPSHCFG_NSH << CBAR_S1_BPSHCFG_SHIFT) |
-                       (CBAR_S1_MEMATTR_WB << CBAR_S1_MEMATTR_SHIFT);
+               reg |= FIELD_PREP(CBAR_S1_BPSHCFG, CBAR_S1_BPSHCFG_NSH) |
+                       FIELD_PREP(CBAR_S1_MEMATTR, CBAR_S1_MEMATTR_WB);
        } else if (!(smmu->features & ARM_SMMU_FEAT_VMID16)) {
                /* 8-bit VMIDs live in CBAR */
-               reg |= cfg->vmid << CBAR_VMID_SHIFT;
+               reg |= FIELD_PREP(CBAR_VMID, cfg->vmid);
        }
        writel_relaxed(reg, gr1_base + ARM_SMMU_GR1_CBAR(idx));