fsl_esdhc: Add the workaround for erratum ESDHC-A001 (enable on P2020)

Data timeout counter (SYSCTL[DTOCV]) is not reliable for values of 4, 8,
and 12. Program one more than the desired value: 4 -> 5, 8 -> 9, 12 -> 13.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
index 0cc8b1e..4f8134b 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
+++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
@@ -59,6 +59,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 #if defined(CONFIG_SYS_FSL_ERRATUM_ESDHC136)
        puts("Work-around for Erratum ESDHC136 enabled\n");
 #endif
+#if defined(CONFIG_SYS_FSL_ERRATUM_ESDHC_A001)
+       puts("Work-around for Erratum ESDHC-A001 enabled\n");
+#endif
 #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A002
        puts("Work-around for Erratum CPC-A002 enabled\n");
 #endif

diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index 9919d97..c771a4b 100644 (file)
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -131,12 +131,14 @@
 #define CONFIG_SYS_FSL_NUM_LAWS                12
 #define CONFIG_SYS_FSL_SEC_COMPAT      2
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
+#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
 
 #elif defined(CONFIG_P2020)
 #define CONFIG_MAX_CPUS                        2
 #define CONFIG_SYS_FSL_NUM_LAWS                12
 #define CONFIG_SYS_FSL_SEC_COMPAT      2
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
+#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
 
 #elif defined(CONFIG_PPC_P2040)
 #define CONFIG_MAX_CPUS                        4

diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index d01c926..f3cccbe 100644 (file)
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -219,6 +219,11 @@ static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data)
        if (timeout < 0)
                timeout = 0;
 
+#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
+       if ((timeout == 4) || (timeout == 8) || (timeout == 12))
+               timeout++;
+#endif
+
        esdhc_clrsetbits32(&regs->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16);
 
        return 0;