+2017-11-21 Claudiu Zissulescu <claziss@synopsys.com>
+
+ * testsuite/gas/arc/b.d : Update test.
+ * testsuite/gas/arc/bl.d: Likewise.
+ * testsuite/gas/arc/jli-1.d: Likewise.
+ * testsuite/gas/arc/lp.d: Likewise.
+ * testsuite/gas/arc/pcl-relocs.d: Likewise.
+ * testsuite/gas/arc/pcrel-relocs.d: Likewise.
+ * testsuite/gas/arc/pic-relocs.d: Likewise.
+ * testsuite/gas/arc/plt-relocs.d: Likewise.
+ * testsuite/gas/arc/pseudos.d: Likewise.
+ * testsuite/gas/arc/relax-avoid2.d: Likewise.
+ * testsuite/gas/arc/relax-avoid3.d: Likewise.
+ * testsuite/gas/arc/relax-b.d: Likewise.
+ * testsuite/gas/arc/tls-relocs.d: Likewise.
+ * testsuite/gas/arc/relax-add01.d: Likewise.
+ * testsuite/gas/arc/relax-add04.d: Likewise.
+ * testsuite/gas/arc/relax-ld01.d: Likewise.
+ * testsuite/gas/arc/relax-sub01.d: Likewise.
+ * testsuite/gas/arc/relax-sub02.d: Likewise.
+ * testsuite/gas/arc/relax-sub04.d: Likewise.
+ * testsuite/gas/arc/pcl-print.s: New file.
+ * testsuite/gas/arc/pcl-print.d: Likewise.
+ * testsuite/gas/arc/nps400-12.d: Likewise.
+
2017-11-21 Alan Modra <amodra@gmail.com>
* config/tc-xtensa.c (finish_vinsn): Avoid multiple ngettext calls
Disassembly of section .text:
00000000 <text_label>:
- 0: 0001 0000 b 0 <text_label>
- 4: 07fc ffc0 b -4
- 8: 07f8 ffc0 b -8
- c: 07f4 ffc1 beq -12
- 10: 07f0 ffc1 beq -16
- 14: 07ec ffc2 bne -20
- 18: 07e8 ffc2 bne -24
- 1c: 07e4 ffc3 bp -28
- 20: 07e0 ffc3 bp -32
- 24: 07dc ffc4 bn -36
- 28: 07d8 ffc4 bn -40
- 2c: 07d4 ffc5 bc -44
- 30: 07d0 ffc5 bc -48
- 34: 07cc ffc5 bc -52
- 38: 07c8 ffc6 bnc -56
- 3c: 07c4 ffc6 bnc -60
- 40: 07c0 ffc6 bnc -64
- 44: 07bc ffc7 bv -68
- 48: 07b8 ffc7 bv -72
- 4c: 07b4 ffc8 bnv -76
- 50: 07b0 ffc8 bnv -80
- 54: 07ac ffc9 bgt -84
- 58: 07a8 ffca bge -88
- 5c: 07a4 ffcb blt -92
- 60: 07a0 ffcc ble -96
- 64: 079c ffcd bhi -100
- 68: 0798 ffce bls -104
- 6c: 0794 ffcf bpnz -108
- 70: 0791 ffef b.d 0 <text_label>
+ 0: 0001 0000 b 0 ;0 <text_label>
+ 4: 07fc ffc0 b -4 ;0 <text_label>
+ 8: 07f8 ffc0 b -8 ;0 <text_label>
+ c: 07f4 ffc1 beq -12 ;0 <text_label>
+ 10: 07f0 ffc1 beq -16 ;0 <text_label>
+ 14: 07ec ffc2 bne -20 ;0 <text_label>
+ 18: 07e8 ffc2 bne -24 ;0 <text_label>
+ 1c: 07e4 ffc3 bp -28 ;0 <text_label>
+ 20: 07e0 ffc3 bp -32 ;0 <text_label>
+ 24: 07dc ffc4 bn -36 ;0 <text_label>
+ 28: 07d8 ffc4 bn -40 ;0 <text_label>
+ 2c: 07d4 ffc5 bc -44 ;0 <text_label>
+ 30: 07d0 ffc5 bc -48 ;0 <text_label>
+ 34: 07cc ffc5 bc -52 ;0 <text_label>
+ 38: 07c8 ffc6 bnc -56 ;0 <text_label>
+ 3c: 07c4 ffc6 bnc -60 ;0 <text_label>
+ 40: 07c0 ffc6 bnc -64 ;0 <text_label>
+ 44: 07bc ffc7 bv -68 ;0 <text_label>
+ 48: 07b8 ffc7 bv -72 ;0 <text_label>
+ 4c: 07b4 ffc8 bnv -76 ;0 <text_label>
+ 50: 07b0 ffc8 bnv -80 ;0 <text_label>
+ 54: 07ac ffc9 bgt -84 ;0 <text_label>
+ 58: 07a8 ffca bge -88 ;0 <text_label>
+ 5c: 07a4 ffcb blt -92 ;0 <text_label>
+ 60: 07a0 ffcc ble -96 ;0 <text_label>
+ 64: 079c ffcd bhi -100 ;0 <text_label>
+ 68: 0798 ffce bls -104 ;0 <text_label>
+ 6c: 0794 ffcf bpnz -108 ;0 <text_label>
+ 70: 0791 ffef b.d -112 ;0 <text_label>
74: 264a 7000 nop
- 78: 0789 ffcf b 0 <text_label>
- 7c: 0785 ffef b.d 0 <text_label>
+ 78: 0789 ffcf b -120 ;0 <text_label>
+ 7c: 0785 ffef b.d -124 ;0 <text_label>
80: 264a 7000 nop
- 84: 077c ffe1 beq.d -132
+ 84: 077c ffe1 beq.d -132 ;0 <text_label>
88: 264a 7000 nop
- 8c: 0774 ffc2 bne -140
- 90: 0770 ffe6 bnc.d -144
+ 8c: 0774 ffc2 bne -140 ;0 <text_label>
+ 90: 0770 ffe6 bnc.d -144 ;0 <text_label>
94: 264a 7000 nop
Disassembly of section .text:
[0-9a-f]+ <text_label>:
- 0: 0802 0000 bl 0 <text_label>
- 4: 0ffc ffc0 bl 0 <text_label>
- 8: 0ff8 ffc0 bl 0 <text_label>
- c: 0ff4 ffc1 bleq 0 <text_label>
- 10: 0ff0 ffc1 bleq 0 <text_label>
- 14: 0fec ffc2 blne 0 <text_label>
- 18: 0fe8 ffc2 blne 0 <text_label>
- 1c: 0fe4 ffc3 blp 0 <text_label>
- 20: 0fe0 ffc3 blp 0 <text_label>
- 24: 0fdc ffc4 bln 0 <text_label>
- 28: 0fd8 ffc4 bln 0 <text_label>
- 2c: 0fd4 ffc5 blc 0 <text_label>
- 30: 0fd0 ffc5 blc 0 <text_label>
- 34: 0fcc ffc5 blc 0 <text_label>
- 38: 0fc8 ffc6 blnc 0 <text_label>
- 3c: 0fc4 ffc6 blnc 0 <text_label>
- 40: 0fc0 ffc6 blnc 0 <text_label>
- 44: 0fbc ffc7 blv 0 <text_label>
- 48: 0fb8 ffc7 blv 0 <text_label>
- 4c: 0fb4 ffc8 blnv 0 <text_label>
- 50: 0fb0 ffc8 blnv 0 <text_label>
- 54: 0fac ffc9 blgt 0 <text_label>
- 58: 0fa8 ffca blge 0 <text_label>
- 5c: 0fa4 ffcb bllt 0 <text_label>
- 60: 0fa0 ffcc blle 0 <text_label>
- 64: 0f9c ffcd blhi 0 <text_label>
- 68: 0f98 ffce blls 0 <text_label>
- 6c: 0f94 ffcf blpnz 0 <text_label>
- 70: 0f92 ffef bl.d 0 <text_label>
+ 0: 0802 0000 bl 0 ;0 <text_label>
+ 4: 0ffc ffc0 bl -4 ;0 <text_label>
+ 8: 0ff8 ffc0 bl -8 ;0 <text_label>
+ c: 0ff4 ffc1 bleq -12 ;0 <text_label>
+ 10: 0ff0 ffc1 bleq -16 ;0 <text_label>
+ 14: 0fec ffc2 blne -20 ;0 <text_label>
+ 18: 0fe8 ffc2 blne -24 ;0 <text_label>
+ 1c: 0fe4 ffc3 blp -28 ;0 <text_label>
+ 20: 0fe0 ffc3 blp -32 ;0 <text_label>
+ 24: 0fdc ffc4 bln -36 ;0 <text_label>
+ 28: 0fd8 ffc4 bln -40 ;0 <text_label>
+ 2c: 0fd4 ffc5 blc -44 ;0 <text_label>
+ 30: 0fd0 ffc5 blc -48 ;0 <text_label>
+ 34: 0fcc ffc5 blc -52 ;0 <text_label>
+ 38: 0fc8 ffc6 blnc -56 ;0 <text_label>
+ 3c: 0fc4 ffc6 blnc -60 ;0 <text_label>
+ 40: 0fc0 ffc6 blnc -64 ;0 <text_label>
+ 44: 0fbc ffc7 blv -68 ;0 <text_label>
+ 48: 0fb8 ffc7 blv -72 ;0 <text_label>
+ 4c: 0fb4 ffc8 blnv -76 ;0 <text_label>
+ 50: 0fb0 ffc8 blnv -80 ;0 <text_label>
+ 54: 0fac ffc9 blgt -84 ;0 <text_label>
+ 58: 0fa8 ffca blge -88 ;0 <text_label>
+ 5c: 0fa4 ffcb bllt -92 ;0 <text_label>
+ 60: 0fa0 ffcc blle -96 ;0 <text_label>
+ 64: 0f9c ffcd blhi -100 ;0 <text_label>
+ 68: 0f98 ffce blls -104 ;0 <text_label>
+ 6c: 0f94 ffcf blpnz -108 ;0 <text_label>
+ 70: 0f92 ffef bl.d -112 ;0 <text_label>
74: 78e0 nop_s
- 76: 0f8e ffcf bl 0 <text_label>
+ 76: 0f8e ffcf bl -116 ;0 <text_label>
7a: 78e0 nop_s
- 7c: 0f84 ffe1 bleq.d 0 <text_label>
+ 7c: 0f84 ffe1 bleq.d -124 ;0 <text_label>
80: 78e0 nop_s
- 82: 0f80 ffc2 blne 0 <text_label>
+ 82: 0f80 ffc2 blne -128 ;0 <text_label>
86: 78e0 nop_s
- 88: 0f78 ffe6 blnc.d 0 <text_label>
+ 88: 0f78 ffe6 blnc.d -136 ;0 <text_label>
8c: 78e0 nop_s
Disassembly of section .jlitab:
00000000 <__jli.foo>:
- 0: 0001 0000 b 0 <foo>
+ 0: 0001 0000 b 0 ;0 <foo>
0: R_ARC_S25H_PCREL foo
#...
Disassembly of section .text:
[0-9a-f]+ <text_label-0x72>:
- 0: 20a8 0e40 lp 72 <text_label>
- 4: 20e8 0de0 lp 72 <text_label>
- 8: 20e8 0d60 lp 72 <text_label>
- c: 20e8 0ce1 lpeq 72 <text_label>
- 10: 20e8 0c61 lpeq 72 <text_label>
- 14: 20e8 0be2 lpne 72 <text_label>
- 18: 20e8 0b62 lpne 72 <text_label>
- 1c: 20e8 0ae3 lpp 72 <text_label>
- 20: 20e8 0a63 lpp 72 <text_label>
- 24: 20e8 09e4 lpn 72 <text_label>
- 28: 20e8 0964 lpn 72 <text_label>
- 2c: 20e8 08e5 lpc 72 <text_label>
- 30: 20e8 0865 lpc 72 <text_label>
- 34: 20e8 07e5 lpc 72 <text_label>
- 38: 20e8 0766 lpnc 72 <text_label>
- 3c: 20e8 06e6 lpnc 72 <text_label>
- 40: 20e8 0666 lpnc 72 <text_label>
- 44: 20e8 05e7 lpv 72 <text_label>
- 48: 20e8 0567 lpv 72 <text_label>
- 4c: 20e8 04e8 lpnv 72 <text_label>
- 50: 20e8 0468 lpnv 72 <text_label>
- 54: 20e8 03e9 lpgt 72 <text_label>
- 58: 20e8 036a lpge 72 <text_label>
- 5c: 20e8 02eb lplt 72 <text_label>
- 60: 20e8 026c lple 72 <text_label>
- 64: 20e8 01ed lphi 72 <text_label>
- 68: 20e8 016e lpls 72 <text_label>
- 6c: 20e8 00ef lppnz 72 <text_label>
+ 0: 20a8 0e40 lp 114 ;72 <text_label>
+ 4: 20e8 0de0 lp 0x6e ;72 <text_label>
+ 8: 20e8 0d60 lp 0x6a ;72 <text_label>
+ c: 20e8 0ce1 lpeq 0x66 ;72 <text_label>
+ 10: 20e8 0c61 lpeq 0x62 ;72 <text_label>
+ 14: 20e8 0be2 lpne 0x5e ;72 <text_label>
+ 18: 20e8 0b62 lpne 0x5a ;72 <text_label>
+ 1c: 20e8 0ae3 lpp 0x56 ;72 <text_label>
+ 20: 20e8 0a63 lpp 0x52 ;72 <text_label>
+ 24: 20e8 09e4 lpn 0x4e ;72 <text_label>
+ 28: 20e8 0964 lpn 0x4a ;72 <text_label>
+ 2c: 20e8 08e5 lpc 0x46 ;72 <text_label>
+ 30: 20e8 0865 lpc 0x42 ;72 <text_label>
+ 34: 20e8 07e5 lpc 0x3e ;72 <text_label>
+ 38: 20e8 0766 lpnc 0x3a ;72 <text_label>
+ 3c: 20e8 06e6 lpnc 0x36 ;72 <text_label>
+ 40: 20e8 0666 lpnc 0x32 ;72 <text_label>
+ 44: 20e8 05e7 lpv 0x2e ;72 <text_label>
+ 48: 20e8 0567 lpv 0x2a ;72 <text_label>
+ 4c: 20e8 04e8 lpnv 0x26 ;72 <text_label>
+ 50: 20e8 0468 lpnv 0x22 ;72 <text_label>
+ 54: 20e8 03e9 lpgt 0x1e ;72 <text_label>
+ 58: 20e8 036a lpge 0x1a ;72 <text_label>
+ 5c: 20e8 02eb lplt 0x16 ;72 <text_label>
+ 60: 20e8 026c lple 0x12 ;72 <text_label>
+ 64: 20e8 01ed lphi 0xe ;72 <text_label>
+ 68: 20e8 016e lpls 0xa ;72 <text_label>
+ 6c: 20e8 00ef lppnz 0x6 ;72 <text_label>
70: 78e0 nop_s
000000b4 <label>:
b4: 3a2f 0025 getrtc r2,\[cm:r0\]
b8: 3e2f 7025 getrtc 0,\[cm:r0\]
- bc: 07f8 ffd5 bnj -8
- c0: 07f4 ffd7 bnm -12
- c4: 07f0 ffd8 bnt -16
+ bc: 07f8 ffd5 bnj -8.*
+ c0: 07f4 ffd7 bnm -12.*
+ c4: 07f0 ffd8 bnt -16.*
--- /dev/null
+#objdump: -dr --prefix-addresses --show-raw-insn
+
+.*: +file format .*arc.*
+
+Disassembly of section .text:
+0x00000000 1710 7001\s+ld\s+r1,\[pcl,16\] ;0x00000010
+0x00000004 d005\s+ld_s\s+r0,\[pcl,0x14\] ;0x00000018
+0x00000006 2630 7fc2 0000 0010\s+ld\s+r2,\[0x10,pcl\] ;0x00000014
--- /dev/null
+ .cpu HS
+ .text
+ ld r1,[pcl,0x10]
+ ld_s r0,[pcl,0x14]
+ ld r2,[0x10,pcl]
.*: +file format .*arc.*
Disassembly of section .text:
-0x[0-9a-f]+ 2700 7f80 0000 0000 add r0,pcl,0
+0x[0-9a-f]+ 2700 7f80 0000 0000 add r0,pcl,0.*
4: R_ARC_PC32 var
-0x[0-9a-f]+ 2736 7f86 0000 0000 ldd r6r7,\[pcl,0\]
+0x[0-9a-f]+ 2736 7f86 0000 0000 ldd r6r7,\[pcl,0\].*
c: R_ARC_PC32 var
-0x[0-9a-f]+ 2730 7f83 0000 0000 ld r3,\[pcl,0\]
+0x[0-9a-f]+ 2730 7f83 0000 0000 ld r3,\[pcl,0\].*
14: R_ARC_PC32 var
.*: +file format .*arc.*
Disassembly of section .text:
-0x[0-9a-f]+ 0000 0002 bne 0
+0x[0-9a-f]+ 0000 0002 bne 0 ;0x00000000
0: R_ARC_S21H_PCREL printf
-0x[0-9a-f]+ 0800 0002 blne 0x00000000
+0x[0-9a-f]+ 0800 0002 blne 0 ;0x00000000
4: R_ARC_S21W_PCREL printf
-0x[0-9a-f]+ 0001 0000 b 0x00000000
+0x[0-9a-f]+ 0001 0000 b 0 ;0x00000000
8: R_ARC_S25H_PCREL printf
-0x[0-9a-f]+ 0802 0000 bl 0x00000000
+0x[0-9a-f]+ 0802 0000 bl 0 ;0x00000000
c: R_ARC_S25W_PCREL printf
-0x[0-9a-f]+ f800 bl_s 0x00000000
+0x[0-9a-f]+ f800 bl_s 0 ;0x00000000
10: R_ARC_S13_PCREL printf
.*: +file format .*arc.*
Disassembly of section .text:
-0x[0-9a-f]+ 2730 7f82 0000 0000 ld r2,\[pcl,0\]
+0x[0-9a-f]+ 2730 7f82 0000 0000 ld r2,\[pcl,0\].*
4: R_ARC_GOTPC32 var
-0x[0-9a-f]+ 2700 7f9a 0000 0000 add gp,pcl,0
+0x[0-9a-f]+ 2700 7f9a 0000 0000 add gp,pcl,0.*
c: R_ARC_GOTPC32 var
0x[0-9a-f]+ 2200 3f82 0000 0000 add r2,gp,0
14: R_ARC_GOTOFF var
.*: +file format .*arc.*
Disassembly of section .text:
-0x[0-9a-f]+ 0000 0002 bne 0
+0x[0-9a-f]+ 0000 0002 bne 0 ;0x00000000
0: R_ARC_S21H_PCREL_PLT printf
-0x[0-9a-f]+ 0800 0002 blne 0x00000000
+0x[0-9a-f]+ 0800 0002 blne 0 ;0x00000000
4: R_ARC_S21W_PCREL_PLT printf
-0x[0-9a-f]+ 0001 0000 b 0x00000000
+0x[0-9a-f]+ 0001 0000 b 0 ;0x00000000
8: R_ARC_S25H_PCREL_PLT printf
-0x[0-9a-f]+ 0802 0000 bl 0x00000000
+0x[0-9a-f]+ 0802 0000 bl 0 ;0x00000000
c: R_ARC_S25W_PCREL_PLT printf
-0x[0-9a-f]+ 2700 7f80 0000 0000 add r0,pcl,0
+0x[0-9a-f]+ 2700 7f80 0000 0000 add r0,pcl,0.*
14: R_ARC_PLT32 printf
00000000 <.text>:
0: 1cfc b008 st.aw r0,\[sp,-4\]
4: 1404 3401 ld.ab r1,\[sp,4\]
- 8: 0901 0002 brlt.* r1,r0,0x8
- c: 08fd 8013 brge.* r0,0,0x8
- 10: 0ef9 f002 0000 003f brlt.* 0x3f,r0,0x8
- 18: 0ef1 f002 ffff fffe brlt.* 0xfffffffe,r0,0x8
- 20: 08e9 8f82 ffff fffe brlt.* r0,0xfffffffe,0x8
- 28: 0ee1 f013 ffff fffe brge.* 0xfffffffe,0,0x8
- 30: 0ed9 ffd3 ffff fffe brge.* 0xfffffffe,0x3f,0x8
- 38: 09d1 8044 brlo.* r1,r1,0x8
- 3c: 09cd 8015 brhs.* r1,0,0x8
- 40: 0ec9 f044 0000 003f brlo.* 0x3f,r1,0x8
- 48: 0ec1 f044 ffff fffe brlo.* 0xfffffffe,r1,0x8
- 50: 08b9 8f84 ffff fffe brlo.* r0,0xfffffffe,0x8
- 58: 0eb1 f015 ffff fffe brhs.* 0xfffffffe,0,0x8
- 60: 0ea9 ffd5 ffff fffe brhs.* 0xfffffffe,0x3f,0x8
- 68: 09a1 8043 brge.* r1,r1,0x8
- 6c: 099d 8012 brlt.* r1,0,0x8
- 70: 0e99 f043 0000 003f brge.* 0x3f,r1,0x8
- 78: 0e91 f043 ffff fffe brge.* 0xfffffffe,r1,0x8
- 80: 0889 8f83 ffff fffe brge.* r0,0xfffffffe,0x8
- 88: 0e81 f012 ffff fffe brlt.* 0xfffffffe,0,0x8
- 90: 0e79 ffd2 ffff fffe brlt.* 0xfffffffe,0x3f,0x8
- 98: 0971 8043 brge.* r1,r1,0x8
- 9c: 096d 8012 brlt.* r1,0,0x8
- a0: 0e69 f043 0000 003f brge.* 0x3f,r1,0x8
- a8: 0e61 f043 ffff fffe brge.* 0xfffffffe,r1,0x8
- b0: 0859 8f83 ffff fffe brge.* r0,0xfffffffe,0x8
- b8: 0e51 f012 ffff fffe brlt.* 0xfffffffe,0,0x8
- c0: 0e49 ffd2 ffff fffe brlt.* 0xfffffffe,0x3f,0x8
+ 8: 0901 0002 brlt.* r1,r0,0 ;0x8
+ c: 08fd 8013 brge.* r0,0,-4 ;0x8
+ 10: 0ef9 f002 0000 003f brlt.* 0x3f,r0,-8 ;0x8
+ 18: 0ef1 f002 ffff fffe brlt.* 0xfffffffe,r0,-16 ;0x8
+ 20: 08e9 8f82 ffff fffe brlt.* r0,0xfffffffe,-24 ;0x8
+ 28: 0ee1 f013 ffff fffe brge.* 0xfffffffe,0,-32 ;0x8
+ 30: 0ed9 ffd3 ffff fffe brge.* 0xfffffffe,0x3f,-40 ;0x8
+ 38: 09d1 8044 brlo.* r1,r1,-48 ;0x8
+ 3c: 09cd 8015 brhs.* r1,0,-52 ;0x8
+ 40: 0ec9 f044 0000 003f brlo.* 0x3f,r1,-56 ;0x8
+ 48: 0ec1 f044 ffff fffe brlo.* 0xfffffffe,r1,-64 ;0x8
+ 50: 08b9 8f84 ffff fffe brlo.* r0,0xfffffffe,-72 ;0x8
+ 58: 0eb1 f015 ffff fffe brhs.* 0xfffffffe,0,-80 ;0x8
+ 60: 0ea9 ffd5 ffff fffe brhs.* 0xfffffffe,0x3f,-88 ;0x8
+ 68: 09a1 8043 brge.* r1,r1,-96 ;0x8
+ 6c: 099d 8012 brlt.* r1,0,-100 ;0x8
+ 70: 0e99 f043 0000 003f brge.* 0x3f,r1,-104 ;0x8
+ 78: 0e91 f043 ffff fffe brge.* 0xfffffffe,r1,-112 ;0x8
+ 80: 0889 8f83 ffff fffe brge.* r0,0xfffffffe,-120 ;0x8
+ 88: 0e81 f012 ffff fffe brlt.* 0xfffffffe,0,-128 ;0x8
+ 90: 0e79 ffd2 ffff fffe brlt.* 0xfffffffe,0x3f,-136 ;0x8
+ 98: 0971 8043 brge.* r1,r1,-144 ;0x8
+ 9c: 096d 8012 brlt.* r1,0,-148 ;0x8
+ a0: 0e69 f043 0000 003f brge.* 0x3f,r1,-152 ;0x8
+ a8: 0e61 f043 ffff fffe brge.* 0xfffffffe,r1,-160 ;0x8
+ b0: 0859 8f83 ffff fffe brge.* r0,0xfffffffe,-168 ;0x8
+ b8: 0e51 f012 ffff fffe brlt.* 0xfffffffe,0,-176 ;0x8
+ c0: 0e49 ffd2 ffff fffe brlt.* 0xfffffffe,0x3f,-184 ;0x8
Disassembly of section .text:
00000000 <.text>:
- 0: 2740 7401 add r1,pcl,0x10
+ 0: 2740 7401 add r1,pcl,0x10\s.*
4: 264a 7000\s+.*
8: 264a 7000\s+.*
c: 264a 7000\s+.*
00000000 <.text>:
0: 78e0 nop_s
- 2: 2740 7281 add r1,pcl,0xa
+ 2: 2740 7281 add r1,pcl,0xa\s.*
6: 264a 7000\s+.*
a: 78e0 nop_s
c: 2000 0000 add r0,r0,r0
0: 2000 0000 add r0,r0,r0
00000004 <main>:
- 4: 0802 0000 bl 0 <test>
+ 4: 0802 0000 bl 0 ;0 <test>
4: R_ARC_S25W_PCREL_PLT test
0: 2000 0000 add r0,r0,r0
00000004 <main>:
- 4: 0001 0000 b 0 <test>
+ 4: 0001 0000 b 0 ;0 <test>
4: R_ARC_S25H_PCREL test
4: 2000 0000 add r0,r0,r0
00000008 <bar>:
- 8: ffff bl_s 4 <foo>
+ 8: ffff bl_s -4 ;4 <foo>
a: 2100 0041 add r1,r1,r1
- e: f1fc b_s 4 <foo>
+ e: f1fc b_s -8 ;4 <foo>
00000000 <.text>:
0: 78e0 nop_s
- 2: 1710 7001 ld r1,\[pcl,16\]
+ 2: 1710 7001 ld r1,\[pcl,16\]\s.*
6: 264a 7000\s+.*
a: 264a 7000\s+.*
e: 78e0 nop_s
Disassembly of section .text:
00000000 <.text>:
- 0: 2742 7401 sub r1,pcl,0x10
+ 0: 2742 7401 sub r1,pcl,0x10\s.*
4: 264a 7000\s+.*
8: 264a 7000\s+.*
c: 264a 7000\s+.*
Disassembly of section .text:
00000000 <.text>:
- 0: 2742 7401 sub r1,pcl,0x10
+ 0: 2742 7401 sub r1,pcl,0x10\s.*
4: 264a 7000\s+.*
8: 264a 7000\s+.*
c: 264a 7000\s+.*
00000000 <.text>:
0: 78e0 nop_s
- 2: 2742 7281 sub r1,pcl,0xa
+ 2: 2742 7281 sub r1,pcl,0xa\s.*
6: 264a 7000\s+.*
a: 78e0 nop_s
c: 2000 0000 add r0,r0,r0
.*: +file format .*arc.*
Disassembly of section .text:
-0x[0-9a-f]+ 2730 7f82 0000 0000 ld r2,\[pcl,0\]
+0x[0-9a-f]+ 2730 7f82 0000 0000 ld r2,\[pcl,0\].*
4: R_ARC_TLS_IE_GOT var
-0x[0-9a-f]+ 2700 7f80 0000 0000 add r0,pcl,0
+0x[0-9a-f]+ 2700 7f80 0000 0000 add r0,pcl,0.*
c: R_ARC_TLS_GD_GOT var
0x[0-9a-f]+ 2000 0f81 0000 0000 add r1,r0,0
14: R_ARC_TLS_DTPOFF var
0x[0-9a-f]+ 2100 3f80 0000 0000 add r0,r25,0
1c: R_ARC_TLS_LE_32 var
-0x[0-9a-f]+ 0802 0000 bl 0x00000000
+0x[0-9a-f]+ 0802 0000 bl 0 ;0x00000000
20: R_ARC_TLS_GD_LD .tdata
20: R_ARC_S25W_PCREL_PLT func
+2017-11-21 Claudiu Zissulescu <claziss@synopsys.com>
+
+ * testsuite/ld-arc/jli-simple.d: Update test.
+
2017-11-20 Nick Clifton <nickc@redhat.com>
PR 22450
Disassembly of section .jlitab:
00010060 <__jli.foo>:
- 10060: 07f9 ffcf b 10058 <foo>
+ 10060: 07f9 ffcf b -8 ;10058 <foo>
00010064 <__jli.bar>:
- 10064: 07f9 ffcf b 1005c <bar>
+ 10064: 07f9 ffcf b -8 ;1005c <bar>
+2017-11-21 Claudiu Zissulescu <claziss@synopsys.com>
+
+ * arc-dis.c (print_insn_arc): Pretty print pc-relative offsets.
+ * arc-opc.c (SIMM21_A16_5): Make it pc-relative.
+
2017-11-16 Tamar Christina <tamar.christina@arm.com>
* aarch64-tbl.h (aarch64_feature_fp_16_v8_2): Require AARCH64_FEATURE_F16_FML
bfd_boolean open_braket;
int size;
const struct arc_operand *operand;
- int value;
+ int value, vpcl;
struct arc_operand_iterator iter;
struct arc_disassemble_info *arc_infop;
+ bfd_boolean rpcl = FALSE, rset = FALSE;
if (info->disassembler_options)
{
/* Read the insn into a host word. */
status = (*info->read_memory_func) (memaddr, buffer, size, info);
+
if (status != 0)
{
(*info->memory_error_func) (status, memaddr, info);
switch (insn_len)
{
case 2:
- (*info->fprintf_func) (info->stream, ".long %#04llx",
+ (*info->fprintf_func) (info->stream, ".shor\t%#04llx",
insn & 0xffff);
break;
case 4:
- (*info->fprintf_func) (info->stream, ".long %#08llx",
+ (*info->fprintf_func) (info->stream, ".word\t%#08llx",
insn & 0xffffffff);
break;
case 6:
- (*info->fprintf_func) (info->stream, ".long %#08llx",
+ (*info->fprintf_func) (info->stream, ".long\t%#08llx",
insn & 0xffffffff);
- (*info->fprintf_func) (info->stream, ".long %#04llx",
+ (*info->fprintf_func) (info->stream, ".long\t%#04llx",
(insn >> 32) & 0xffff);
break;
case 8:
- (*info->fprintf_func) (info->stream, ".long %#08llx",
+ (*info->fprintf_func) (info->stream, ".long\t%#08llx",
insn & 0xffffffff);
- (*info->fprintf_func) (info->stream, ".long %#08llx",
+ (*info->fprintf_func) (info->stream, ".long\t%#08llx",
insn >> 32);
break;
default:
/* Now extract and print the operands. */
operand = NULL;
+ vpcl = 0;
while (operand_iterator_next (&iter, &operand, &value))
{
if (open_braket && (operand->flags & ARC_OPERAND_BRAKET))
need_comma = TRUE;
+ if (operand->flags & ARC_OPERAND_PCREL)
+ {
+ rpcl = TRUE;
+ vpcl = value;
+ rset = TRUE;
+
+ info->target = (bfd_vma) (memaddr & ~3) + value;
+ }
+ else if (!(operand->flags & ARC_OPERAND_IR))
+ {
+ vpcl = value;
+ rset = TRUE;
+ }
+
/* Print the operand as directed by the flags. */
if (operand->flags & ARC_OPERAND_IR)
{
rname = regnames[value + 1];
(*info->fprintf_func) (info->stream, "%s", rname);
}
+ if (value == 63)
+ rpcl = TRUE;
+ else
+ rpcl = FALSE;
}
else if (operand->flags & ARC_OPERAND_LIMM)
{
info->target = (bfd_vma) value;
}
}
- else if (operand->flags & ARC_OPERAND_PCREL)
- {
- /* PCL relative. */
- if (info->flags & INSN_HAS_RELOC)
- memaddr = 0;
- (*info->print_address_func) ((memaddr & ~3) + value, info);
-
- info->target = (bfd_vma) (memaddr & ~3) + value;
- }
else if (operand->flags & ARC_OPERAND_SIGNED)
{
const char *rname = get_auxreg (opcode, value, isa_mask);
&& !(operand->flags & ARC_OPERAND_ALIGNED16)
&& value >= 0 && value <= 14)
{
+ /* Leave/Enter mnemonics. */
switch (value)
{
case 0:
regnames[13 + value - 1]);
break;
}
+ rpcl = FALSE;
+ rset = FALSE;
}
else
{
arc_infop->operands_count ++;
}
+ /* Pretty print extra info for pc-relative operands. */
+ if (rpcl && rset)
+ {
+ if (info->flags & INSN_HAS_RELOC)
+ /* If the instruction has a reloc associated with it, then the
+ offset field in the instruction will actually be the addend
+ for the reloc. (We are using REL type relocs). In such
+ cases, we can ignore the pc when computing addresses, since
+ the addend is not currently pc-relative. */
+ memaddr = 0;
+
+ (*info->fprintf_func) (info->stream, "\t;");
+ (*info->print_address_func) ((memaddr & ~3) + vpcl, info);
+ }
+
return insn_len;
}
/* SIMM21_A16_5 mask = 00000111111111102222222222000000. */
#define SIMM21_A16_5 (UIMM6_8 + 1)
{21, 0, BFD_RELOC_ARC_S21H_PCREL, ARC_OPERAND_SIGNED
- | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_TRUNCATE,
+ | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL,
insert_simm21_a16_5, extract_simm21_a16_5},
/* SIMM25_A16_5 mask = 00000111111111102222222222003333. */
projects / external / binutils.git / commitdiff