#include <linux/module.h>
#include <linux/interrupt.h>
#include <linux/clk.h>
+ ++#include <linux/ctype.h>
#include <linux/device.h>
#include <linux/delay.h>
#include <linux/slab.h>
#include "imx-pcm.h"
/**
- -- * FSLSSI_I2S_RATES: sample rates supported by the I2S
- -- *
- -- * This driver currently only supports the SSI running in I2S slave mode,
- -- * which means the codec determines the sample rate. Therefore, we tell
- -- * ALSA that we support all rates and let the codec driver decide what rates
- -- * are really supported.
- -- */
- --#define FSLSSI_I2S_RATES SNDRV_PCM_RATE_CONTINUOUS
- --
- --/**
* FSLSSI_I2S_FORMATS: audio formats supported by the SSI
*
* The SSI has a limitation in that the samples must be in the same byte
* @dbg_stats: Debugging statistics
*
* @soc: SoC specific data
++ *
++ * @fifo_watermark: the FIFO watermark setting. Notifies DMA when
++ * there are @fifo_watermark or fewer words in TX fifo or
++ * @fifo_watermark or more empty words in RX fifo.
++ * @dma_maxburst: max number of words to transfer in one go. So far,
++ * this is always the same as fifo_watermark.
*/
struct fsl_ssi_private {
struct regmap *regs;
const struct fsl_ssi_soc_data *soc;
struct device *dev;
++
++ u32 fifo_watermark;
++ u32 dma_maxburst;
};
/*
regmap_write(regs, CCSR_SSI_SRCR, srcr);
regmap_write(regs, CCSR_SSI_SCR, scr);
-- /*
-- * Set the watermark for transmit FIFI 0 and receive FIFO 0. We don't
-- * use FIFO 1. We program the transmit water to signal a DMA transfer
-- * if there are only two (or fewer) elements left in the FIFO. Two
-- * elements equals one frame (left channel, right channel). This value,
-- * however, depends on the depth of the transmit buffer.
-- *
-- * We set the watermark on the same level as the DMA burstsize. For
-- * fiq it is probably better to use the biggest possible watermark
-- * size.
-- */
-- if (ssi_private->use_dma)
-- wm = ssi_private->fifo_depth - 2;
-- else
-- wm = ssi_private->fifo_depth;
++ wm = ssi_private->fifo_watermark;
regmap_write(regs, CCSR_SSI_SFCSR,
CCSR_SSI_SFCSR_TFWM0(wm) | CCSR_SSI_SFCSR_RFWM0(wm) |
.stream_name = "CPU-Playback",
.channels_min = 1,
.channels_max = 32,
- -- .rates = FSLSSI_I2S_RATES,
+ ++ .rates = SNDRV_PCM_RATE_CONTINUOUS,
.formats = FSLSSI_I2S_FORMATS,
},
.capture = {
.stream_name = "CPU-Capture",
.channels_min = 1,
.channels_max = 32,
- -- .rates = FSLSSI_I2S_RATES,
+ ++ .rates = SNDRV_PCM_RATE_CONTINUOUS,
.formats = FSLSSI_I2S_FORMATS,
},
.ops = &fsl_ssi_dai_ops,
*/
static void make_lowercase(char *s)
{
- -- char *p = s;
- -- char c;
- --
- -- while ((c = *p)) {
- -- if ((c >= 'A') && (c <= 'Z'))
- -- *p = c + ('a' - 'A');
- -- p++;
- -- }
+ ++ if (!s)
+ ++ return;
+ ++ for (; *s; s++)
+ ++ *s = tolower(*s);
}
static int fsl_ssi_imx_probe(struct platform_device *pdev,
dev_dbg(&pdev->dev, "could not get baud clock: %ld\n",
PTR_ERR(ssi_private->baudclk));
-- /*
-- * We have burstsize be "fifo_depth - 2" to match the SSI
-- * watermark setting in fsl_ssi_startup().
-- */
-- ssi_private->dma_params_tx.maxburst = ssi_private->fifo_depth - 2;
-- ssi_private->dma_params_rx.maxburst = ssi_private->fifo_depth - 2;
++ ssi_private->dma_params_tx.maxburst = ssi_private->dma_maxburst;
++ ssi_private->dma_params_rx.maxburst = ssi_private->dma_maxburst;
ssi_private->dma_params_tx.addr = ssi_private->ssi_phys + CCSR_SSI_STX0;
ssi_private->dma_params_rx.addr = ssi_private->ssi_phys + CCSR_SSI_SRX0;
/* Older 8610 DTs didn't have the fifo-depth property */
ssi_private->fifo_depth = 8;
++ /*
++ * Set the watermark for transmit FIFO 0 and receive FIFO 0. We don't
++ * use FIFO 1 but set the watermark appropriately nontheless.
++ * We program the transmit water to signal a DMA transfer
++ * if there are N elements left in the FIFO. For chips with 15-deep
++ * FIFOs, set watermark to 8. This allows the SSI to operate at a
++ * high data rate without channel slipping. Behavior is unchanged
++ * for the older chips with a fifo depth of only 8. A value of 4
++ * might be appropriate for the older chips, but is left at
++ * fifo_depth-2 until sombody has a chance to test.
++ *
++ * We set the watermark on the same level as the DMA burstsize. For
++ * fiq it is probably better to use the biggest possible watermark
++ * size.
++ */
++ switch (ssi_private->fifo_depth) {
++ case 15:
++ /*
++ * 2 samples is not enough when running at high data
++ * rates (like 48kHz @ 16 bits/channel, 16 channels)
++ * 8 seems to split things evenly and leave enough time
++ * for the DMA to fill the FIFO before it's over/under
++ * run.
++ */
++ ssi_private->fifo_watermark = 8;
++ ssi_private->dma_maxburst = 8;
++ break;
++ case 8:
++ default:
++ /*
++ * maintain old behavior for older chips.
++ * Keeping it the same because I don't have an older
++ * board to test with.
++ * I suspect this could be changed to be something to
++ * leave some more space in the fifo.
++ */
++ ssi_private->fifo_watermark = ssi_private->fifo_depth - 2;
++ ssi_private->dma_maxburst = ssi_private->fifo_depth - 2;
++ break;
++ }
++
dev_set_drvdata(&pdev->dev, ssi_private);
if (ssi_private->soc->imx) {