osd: add g12b revb to check osd shift workaround [1/1]

PD#SWPL-4582

Problem:
g12b revb fix osd blend shift issue

Solution:
add g12b revb to remove shift workaround

Verify:
verify by g12b revb

Change-Id: I6cefba0b5b5cce35d928edafdc359adff0165866
Signed-off-by: Pengcheng Chen <pengcheng.chen@amlogic.com>

diff --git a/drivers/amlogic/media/osd/osd_backup.c b/drivers/amlogic/media/osd/osd_backup.c
index 9ad324f..8209c6e 100644 (file)
--- a/drivers/amlogic/media/osd/osd_backup.c
+++ b/drivers/amlogic/media/osd/osd_backup.c
@@ -648,7 +648,7 @@ static struct reg_item osd3_afbcd_recovery_table_g12a[] = {
                0x0, 0x0000ffff, 1
        },
        {
-               VPU_MAFBC_PREFETCH_CFG_S1, 0x0, 3, 1
+               VPU_MAFBC_PREFETCH_CFG_S2, 0x0, 3, 1
        }
 };
 

diff --git a/drivers/amlogic/media/osd/osd_hw.c b/drivers/amlogic/media/osd/osd_hw.c
index 83d63dd..2d5b719 100644 (file)
--- a/drivers/amlogic/media/osd/osd_hw.c
+++ b/drivers/amlogic/media/osd/osd_hw.c
@@ -33,7 +33,7 @@
 #include <linux/fs.h>
 #include <linux/sysfs.h>
 #include <linux/uaccess.h>
-
+#include <linux/amlogic/cpu_version.h>
 /* Android Headers */
 
 /* Amlogic sync headers */
@@ -4624,12 +4624,8 @@ static void osd_update_disp_freescale_enable(u32 index)
        else
                vf_bank_len = 4;
 
-       if (osd_hw.hwc_enable && (index == OSD1)
-               && ((osd_hw.osd_meson_dev.cpu_id ==
-               __MESON_CPU_MAJOR_ID_G12A) ||
-               (osd_hw.osd_meson_dev.cpu_id ==
-               __MESON_CPU_MAJOR_ID_G12B)))
-               shift_workaround = 1;
+       if (osd_hw.hwc_enable && (index == OSD1))
+               shift_workaround = osd_hw.workaround_line;
 
 #ifndef NEW_PPS_PHASE
        if (osd_hw.bot_type == 1) {
@@ -6581,7 +6577,7 @@ static void osd_set_freescale(u32 index,
        struct layer_blend_reg_s *blend_reg;
        u32 width, height;
        u32 src_height;
-       u32 workaround_line = 1;
+       u32 workaround_line = osd_hw.workaround_line;
 
        layer_blend = &(blending->layer_blend);
        blend_reg = &(blending->blend_reg);
@@ -6766,12 +6762,12 @@ static void osd_setting_blend1_input(u32 index,
        /* for g12a blend shift issue */
 
        if (osd_hw.hdr_used)
-               workaround_line = 1;
+               workaround_line = osd_hw.workaround_line;
        else {
                if (blending->layer_cnt == 2)
                        workaround_line = 0;
                else
-                       workaround_line = 1;
+                       workaround_line = osd_hw.workaround_line;
        }
 
        layer_blend = &(blending->layer_blend);
@@ -8661,13 +8657,13 @@ void osd_init_hw(u32 logo_loaded, u32 osd_probe,
                osd_hw.disp_info.position_h = 1080;
                osd_hw.vinfo_width = 1920;
                osd_hw.vinfo_height = 1080;
+               osd_hw.workaround_line = 0;
                if ((osd_hw.osd_meson_dev.cpu_id ==
                        __MESON_CPU_MAJOR_ID_G12A) ||
-                       (osd_hw.osd_meson_dev.cpu_id ==
-                       __MESON_CPU_MAJOR_ID_G12B))
+                       ((osd_hw.osd_meson_dev.cpu_id ==
+                       __MESON_CPU_MAJOR_ID_G12B) &&
+                       is_meson_rev_a()))
                        osd_hw.workaround_line = 1;
-               else
-                       osd_hw.workaround_line = 0;
                for (idx = 0; idx < osd_hw.osd_meson_dev.osd_count; idx++) {
                        osd_hw.premult_en[idx] = 0;
                        osd_hw.osd_afbcd[idx].format = COLOR_INDEX_32_ABGR;