static u32 video_onoff_time;
static DEFINE_SPINLOCK(video2_onoff_lock);
static int video2_onoff_state = VIDEO_ENABLE_STATE_IDLE;
-static u32 hdmiin_frame_check;
-static u32 hdmiin_frame_check_cnt;
+static u32 frame_skip_check_cnt;
/*frame_detect_flag: 1 enable, 0 disable */
} else
vf_notify_provider_by_name("vdin0",
VFRAME_EVENT_RECEIVER_DISP_MODE, (void *)&req);
- if (req.disp_mode == VFRAME_DISP_MODE_OK)
+ if ((req.disp_mode == VFRAME_DISP_MODE_OK) ||
+ (req.disp_mode == VFRAME_DISP_MODE_NULL))
return false;
/*whether need to check pts??*/
video_vf_put(vf);
* quickly for display
*case2:input buffer all not OK
*/
- if (vf && hdmiin_frame_check &&
- (vf->source_type == VFRAME_SOURCE_TYPE_HDMI) &&
+ if (vf &&
+ ((vf->source_type == VFRAME_SOURCE_TYPE_HDMI) ||
+ (vf->source_type == VFRAME_SOURCE_TYPE_CVBS)) &&
(video_vf_disp_mode_get(vf) ==
VFRAME_DISP_MODE_UNKNOWN) &&
- (hdmiin_frame_check_cnt++ < 10))
+ (frame_skip_check_cnt++ < 10))
break;
else
- hdmiin_frame_check_cnt = 0;
+ frame_skip_check_cnt = 0;
vf = video_vf_get();
if (!vf) {
ATRACE_COUNTER(MODULE_NAME, __LINE__);
break;
}
- if (vf && hdmiin_frame_check && (vf->source_type ==
- VFRAME_SOURCE_TYPE_HDMI) &&
+ if (vf &&
+ ((vf->source_type == VFRAME_SOURCE_TYPE_HDMI) ||
+ (vf->source_type == VFRAME_SOURCE_TYPE_CVBS)) &&
video_vf_disp_mode_check(vf))
break;
force_blackout = 0;
module_param(next_peek_underflow, uint, 0664);
MODULE_PARM_DESC(skip, "\n Underflow count\n");
-module_param(hdmiin_frame_check, uint, 0664);
-MODULE_PARM_DESC(hdmiin_frame_check, "\n hdmiin_frame_check\n");
-
module_param(step_enable, uint, 0664);
MODULE_PARM_DESC(step_enable, "\n step_enable\n");
int en_4k_2_2k;
int en_4k_timing = 1;
bool hdmi_cec_en;
-int vdin_drop_frame_cnt = 1;
+int vdin_drop_frame_cnt = 2;
/* suspend_pddq_sel:
* 0: keep phy on when suspend(don't need phy init when
* resume), it doesn't work now because phy VDDIO_3.3V
#include "hdmi_rx_edid.h"
-#define RX_VER0 "ver.2019-04-09"
+#define RX_VER0 "ver.2019-04-16"
/*
*
*
static uint32_t modet_clk = 24000;
int hdcp_enc_mode;
/* top_irq_en bit[16:13] hdcp_sts */
-int top_intr_maskn_value = 1;
+int top_intr_maskn_value = 0x20000001;
+
bool hdcp_enable = 1;
int acr_mode;
int auto_aclk_mute = 2;
static const uint32_t phy_misci[][4] = {
/* 0xd7 0xd8 0xe0 0xe1 */
{ /* 24~45M */
- 0x3003707f, 0x00000080, 0x02218000, 0x00000010,
+ 0x3007707f, 0x00000080, 0x02218000, 0x00000010,
},
{ /* 45~74.5M */
- 0x3003707f, 0x00000080, 0x02218000, 0x00000010,
+ 0x3007707f, 0x00000080, 0x02218000, 0x00000010,
},
{ /* 77~155M */
- 0x3003707f, 0x00000080, 0x02218000, 0x00000010,
+ 0x3007707f, 0x00000080, 0x02218000, 0x00000010,
},
{ /* 155~340M */
- 0x3003707f, 0x00000080, 0x02218000, 0x00000010,
+ 0x3007707f, 0x00000080, 0x02218000, 0x00000010,
},
{ /* 340~525M */
- 0x3003707f, 0x007f0080, 0x02218000, 0x00000010,
+ 0x3007707f, 0x007f0080, 0x02218000, 0x00000010,
},
{ /* 525~600M */
- 0x3003707f, 0x007f8080, 0x02218000, 0x00000010,
+ 0x3007707f, 0x007f8080, 0x02218000, 0x00000010,
},
};
extern int eq_try_cnt;
extern int pll_rst_max;
extern int cdr_lock_level;
+extern int top_intr_maskn_value;
extern void rx_get_best_eq_setting(void);
extern int hbr_force_8ch;
extern void wr_reg_hhi(unsigned int offset, unsigned int val);
/* modify interrupt flow for isr loading */
/* top interrupt handler */
if (rx.chip_id >= CHIP_ID_TL1) {
- if (hdmirx_top_intr_stat & (1 << 29))
+ if (hdmirx_top_intr_stat & (1 << 29)) {
+ skip_frame(skip_frame_cnt);
if (log_level & 0x100)
rx_pr("[isr] sqofclk_fall\n");
+ }
if (hdmirx_top_intr_stat & (1 << 28))
if (log_level & 0x100)
rx_pr("[isr] sqofclk_rise\n");
return pr_var(hbr_force_8ch, index);
if (set_pr_var(tmpbuf, cdr_lock_level, value, &index, ret))
return pr_var(cdr_lock_level, index);
+ if (set_pr_var(tmpbuf, top_intr_maskn_value, value, &index, ret))
+ return pr_var(top_intr_maskn_value, index);
return 0;
}
pr_var(hdcp_enc_mode, i++);
pr_var(hbr_force_8ch, i++);
pr_var(cdr_lock_level, i++);
+ pr_var(top_intr_maskn_value, i++);
}
void skip_frame(unsigned int cnt)
p->disp_index[0] = 0;
vfe->vf.index_disp = p->disp_index[0];
- p->disp_mode[p->disp_index[p->skip_vf_num]] = VFRAME_DISP_MODE_OK;
+ if (p->disp_mode[p->disp_index[p->skip_vf_num]] !=
+ VFRAME_DISP_MODE_SKIP)
+ p->disp_mode[p->disp_index[p->skip_vf_num]] =
+ VFRAME_DISP_MODE_OK;
for (i = p->skip_vf_num - 1; i < VFRAME_DISP_MAX_NUM; i--)
p->disp_mode[p->disp_index[i]] = VFRAME_DISP_MODE_UNKNOWN;
}
-/*disp mode skip
- *skip_vf_num
- * 2:last last vframe, 1:last vframe
- * 0:current vframe
+/*skip all from current
+ *disp_index[i]:
+ *2:last last vframe, 1:last vframe
+ *0:current vframe
*/
void vdin_vf_disp_mode_skip(struct vf_pool *p)
{
unsigned int i;
-
- for (i = p->skip_vf_num - 1; i < VFRAME_DISP_MAX_NUM; i--)
- p->disp_mode[i] = VFRAME_DISP_MODE_SKIP;
+ for (i = 0; i <= p->skip_vf_num; i++)
+ p->disp_mode[p->disp_index[i]] = VFRAME_DISP_MODE_SKIP;
}