// dead, or because only a subregister is live at the def. If we
// don't do this the dead def will be incorrectly merged into the
// previous def.
- for (const MachineOperand &MO : MI.operands()) {
- if (!MO.isReg() || !MO.isDef()) continue;
+ for (const MachineOperand &MO : MI.all_defs()) {
Register Reg = MO.getReg();
if (Reg == 0) continue;
if (MI.isDebugInstr())
return;
- for (const MachineOperand &MO : MI.operands()) {
- if (MO.isReg() && MO.isDef() && MO.getReg().isPhysical()) {
+ for (const MachineOperand &MO : MI.all_defs()) {
+ if (MO.getReg().isPhysical()) {
for (auto &FwdReg : ForwardedRegWorklist)
if (TRI.regsOverlap(FwdReg.first, MO.getReg()))
Defs.insert(FwdReg.first);
break;
// Remove kills from ActiveDefsSet, these registers had short live ranges.
- for (const MachineOperand &MO : TIB->operands()) {
- if (!MO.isReg() || !MO.isUse() || !MO.isKill())
+ for (const MachineOperand &MO : TIB->all_uses()) {
+ if (!MO.isKill())
continue;
Register Reg = MO.getReg();
if (!Reg)
}
// Track local defs so we can update liveins.
- for (const MachineOperand &MO : TIB->operands()) {
- if (!MO.isReg() || !MO.isDef() || MO.isDead())
+ for (const MachineOperand &MO : TIB->all_defs()) {
+ if (MO.isDead())
continue;
Register Reg = MO.getReg();
if (!Reg || Reg.isVirtual())
// If the instruction has a true dependency, we can hide the false depdency
// behind it.
- for (MachineOperand &CurrMO : MI->operands()) {
- if (!CurrMO.isReg() || CurrMO.isDef() || CurrMO.isUndef() ||
- !OpRC->contains(CurrMO.getReg()))
+ for (MachineOperand &CurrMO : MI->all_uses()) {
+ if (CurrMO.isUndef() || !OpRC->contains(CurrMO.getReg()))
continue;
// We found a true dependency - replace the undef register with the true
// dependency.
return false;
// Examine each operand.
- for (const MachineOperand &MO : MI->operands()) {
- if (MO.isReg() && MO.isDef()) {
- Register Reg = MO.getReg();
- if (Reg.isPhysical()) {
- // Don't delete live physreg defs, or any reserved register defs.
- if (!LivePhysRegs.available(Reg) || MRI->isReserved(Reg))
- return false;
- } else {
- if (MO.isDead()) {
+ for (const MachineOperand &MO : MI->all_defs()) {
+ Register Reg = MO.getReg();
+ if (Reg.isPhysical()) {
+ // Don't delete live physreg defs, or any reserved register defs.
+ if (!LivePhysRegs.available(Reg) || MRI->isReserved(Reg))
+ return false;
+ } else {
+ if (MO.isDead()) {
#ifndef NDEBUG
- // Basic check on the register. All of them should be 'undef'.
- for (auto &U : MRI->use_nodbg_operands(Reg))
- assert(U.isUndef() && "'Undef' use on a 'dead' register is found!");
+ // Basic check on the register. All of them should be 'undef'.
+ for (auto &U : MRI->use_nodbg_operands(Reg))
+ assert(U.isUndef() && "'Undef' use on a 'dead' register is found!");
#endif
- continue;
- }
- for (const MachineInstr &Use : MRI->use_nodbg_instructions(Reg)) {
- if (&Use != MI)
- // This def has a non-debug use. Don't delete the instruction!
- return false;
- }
+ continue;
+ }
+ for (const MachineInstr &Use : MRI->use_nodbg_instructions(Reg)) {
+ if (&Use != MI)
+ // This def has a non-debug use. Don't delete the instruction!
+ return false;
}
}
}
return false;
// Instructions without side-effects are dead iff they only define dead vregs.
- for (const auto &MO : MI.operands()) {
- if (!MO.isReg() || !MO.isDef())
- continue;
-
+ for (const auto &MO : MI.all_defs()) {
Register Reg = MO.getReg();
if (Reg.isPhysical() || !MRI.use_nodbg_empty(Reg))
return false;
// The original operation may define implicit-defs alongside
// the value.
MachineBasicBlock *MBB = NC.getMemOperation()->getParent();
- for (const MachineOperand &MO : FaultingInstr->operands()) {
- if (!MO.isReg() || !MO.isDef())
- continue;
+ for (const MachineOperand &MO : FaultingInstr->all_defs()) {
Register Reg = MO.getReg();
if (!Reg || MBB->isLiveIn(Reg))
continue;
}
if (auto *DepMI = NC.getOnlyDependency()) {
- for (auto &MO : DepMI->operands()) {
- if (!MO.isReg() || !MO.getReg() || !MO.isDef() || MO.isDead())
+ for (auto &MO : DepMI->all_defs()) {
+ if (!MO.getReg() || MO.isDead())
continue;
if (!NC.getNotNullSucc()->isLiveIn(MO.getReg()))
NC.getNotNullSucc()->addLiveIn(MO.getReg());
}
static void getVDefInterval(const MachineInstr &MI, LiveIntervals &LIS) {
- for (const MachineOperand &MO : MI.operands())
- if (MO.isReg() && MO.isDef() && MO.getReg().isVirtual())
+ for (const MachineOperand &MO : MI.all_defs())
+ if (MO.getReg().isVirtual())
LIS.getInterval(MO.getReg());
}
if (!ParentVNI) {
LLVM_DEBUG(dbgs() << "\tadding <undef> flags: ");
- for (MachineOperand &MO : MI.operands())
- if (MO.isReg() && MO.isUse() && MO.getReg() == VirtReg.reg())
+ for (MachineOperand &MO : MI.all_uses())
+ if (MO.getReg() == VirtReg.reg())
MO.setIsUndef();
LLVM_DEBUG(dbgs() << UseIdx << '\t' << MI);
return true;
/// Collect all register defines (including aliases) for the given instruction.
static void collectRegDefs(const MachineInstr &MI, DefinedRegsSet &Regs,
const TargetRegisterInfo *TRI) {
- for (const MachineOperand &MO : MI.operands()) {
- if (MO.isReg() && MO.isDef() && MO.getReg() && MO.getReg().isPhysical()) {
+ for (const MachineOperand &MO : MI.all_defs()) {
+ if (MO.getReg() && MO.getReg().isPhysical()) {
Regs.insert(MO.getReg());
for (MCRegAliasIterator AI(MO.getReg(), TRI, true); AI.isValid(); ++AI)
Regs.insert(*AI);
return nullptr;
PartDefRegs.insert(LastDefReg);
- for (MachineOperand &MO : LastDef->operands()) {
- if (!MO.isReg() || !MO.isDef() || MO.getReg() == 0)
+ for (MachineOperand &MO : LastDef->all_defs()) {
+ if (MO.getReg() == 0)
continue;
Register DefReg = MO.getReg();
if (TRI->isSubRegister(Reg, DefReg)) {
if (LV)
for (MachineInstr &MI :
llvm::make_range(getFirstInstrTerminator(), instr_end())) {
- for (MachineOperand &MO : MI.operands()) {
- if (!MO.isReg() || MO.getReg() == 0 || !MO.isUse() || !MO.isKill() ||
- MO.isUndef())
+ for (MachineOperand &MO : MI.all_uses()) {
+ if (MO.getReg() == 0 || !MO.isKill() || MO.isUndef())
continue;
Register Reg = MO.getReg();
if (Reg.isPhysical() || LV->getVarInfo(Reg).removeKill(MI)) {
bool MachineCSE::PerformTrivialCopyPropagation(MachineInstr *MI,
MachineBasicBlock *MBB) {
bool Changed = false;
- for (MachineOperand &MO : MI->operands()) {
- if (!MO.isReg() || !MO.isUse())
- continue;
+ for (MachineOperand &MO : MI->all_uses()) {
Register Reg = MO.getReg();
if (!Reg.isVirtual())
continue;
PhysDefVector &PhysDefs,
bool &PhysUseDef) const {
// First, add all uses to PhysRefs.
- for (const MachineOperand &MO : MI->operands()) {
- if (!MO.isReg() || MO.isDef())
- continue;
+ for (const MachineOperand &MO : MI->all_uses()) {
Register Reg = MO.getReg();
if (!Reg)
continue;
// Heuristics #2: If the expression doesn't not use a vr and the only use
// of the redundant computation are copies, do not cse.
bool HasVRegUse = false;
- for (const MachineOperand &MO : MI->operands()) {
- if (MO.isReg() && MO.isUse() && MO.getReg().isVirtual()) {
+ for (const MachineOperand &MO : MI->all_uses()) {
+ if (MO.getReg().isVirtual()) {
HasVRegUse = true;
break;
}
// are tracked in the InstrIdxForVirtReg map depth is looked up in InstrDepth
for (auto *InstrPtr : InsInstrs) { // for each Use
unsigned IDepth = 0;
- for (const MachineOperand &MO : InstrPtr->operands()) {
+ for (const MachineOperand &MO : InstrPtr->all_uses()) {
// Check for virtual register operand.
- if (!(MO.isReg() && MO.getReg().isVirtual()))
- continue;
- if (!MO.isUse())
+ if (!MO.getReg().isVirtual())
continue;
unsigned DepthOp = 0;
unsigned LatencyOp = 0;
// Check each definition in NewRoot and compute the latency
unsigned NewRootLatency = 0;
- for (const MachineOperand &MO : NewRoot->operands()) {
+ for (const MachineOperand &MO : NewRoot->all_defs()) {
// Check for virtual register operand.
- if (!(MO.isReg() && MO.getReg().isVirtual()))
- continue;
- if (!MO.isDef())
+ if (!MO.getReg().isVirtual())
continue;
// Get the first instruction that uses MO
MachineRegisterInfo::reg_iterator RI = MRI->reg_begin(MO.getReg());
// Emit DBG_VALUEs for register definitions.
SmallVector<MachineOperand *, 4> RegDefs;
- for (MachineOperand &MO : MI.operands())
- if (MO.isReg() && MO.isDef() && MO.getReg())
+ for (MachineOperand &MO : MI.all_defs())
+ if (MO.getReg())
RegDefs.push_back(&MO);
for (MachineOperand *MO : RegDefs)
BuildMI(MBB, InsertBeforeIt, MI.getDebugLoc(), DbgValDesc,
if (State.first.isVirtual()) {
// Virtual register def -- we can just look up where this happens.
MachineInstr *Inst = MRI.def_begin(State.first)->getParent();
- for (auto &MO : Inst->operands()) {
- if (!MO.isReg() || !MO.isDef() || MO.getReg() != State.first)
+ for (auto &MO : Inst->all_defs()) {
+ if (MO.getReg() != State.first)
continue;
return ApplySubregisters({Inst->getDebugInstrNum(), MO.getOperandNo()});
}
auto RMII = CurInst->getReverseIterator();
auto PrevInstrs = make_range(RMII, CurInst->getParent()->instr_rend());
for (auto &ToExamine : PrevInstrs) {
- for (auto &MO : ToExamine.operands()) {
+ for (auto &MO : ToExamine.all_defs()) {
// Test for operand that defines something aliasing RegToSeek.
- if (!MO.isReg() || !MO.isDef() ||
- !TRI.regsOverlap(RegToSeek, MO.getReg()))
+ if (!TRI.regsOverlap(RegToSeek, MO.getReg()))
continue;
return ApplySubregisters(
if (!PhysRegClobbers.test(Def) && !TermRegs.test(Def)) {
bool Safe = true;
MachineInstr *MI = Candidate.MI;
- for (const MachineOperand &MO : MI->operands()) {
- if (!MO.isReg() || MO.isDef() || !MO.getReg())
+ for (const MachineOperand &MO : MI->all_uses()) {
+ if (!MO.getReg())
continue;
Register Reg = MO.getReg();
if (PhysRegDefs.test(Reg) ||
if (!BB->isLiveIn(Reg))
BB->addLiveIn(Reg);
for (MachineInstr &MI : *BB) {
- for (MachineOperand &MO : MI.operands()) {
- if (!MO.isReg() || !MO.getReg() || MO.isDef()) continue;
+ for (MachineOperand &MO : MI.all_uses()) {
+ if (!MO.getReg())
+ continue;
if (MO.getReg() == Reg || TRI->isSuperRegister(Reg, MO.getReg()))
MO.setIsKill(false);
}
if (!TII->isTriviallyReMaterializable(MI))
return false;
- for (const MachineOperand &MO : MI.operands()) {
- if (MO.isReg() && MO.isUse() && MO.getReg().isVirtual())
+ for (const MachineOperand &MO : MI.all_uses()) {
+ if (MO.getReg().isVirtual())
return false;
}
SmallVector<const MachineInstr*, 8> Work(1, MI);
do {
MI = Work.pop_back_val();
- for (const MachineOperand &MO : MI->operands()) {
- if (!MO.isReg() || !MO.isDef())
- continue;
+ for (const MachineOperand &MO : MI->all_defs()) {
Register Reg = MO.getReg();
if (!Reg.isVirtual())
continue;
// Clear the kill flags of any register this instruction defines,
// since they may need to be live throughout the entire loop
// rather than just live for part of it.
- for (MachineOperand &MO : MI->operands())
- if (MO.isReg() && MO.isDef() && !MO.isDead())
+ for (MachineOperand &MO : MI->all_defs())
+ if (!MO.isDead())
MRI->clearKillFlags(MO.getReg());
// Add to the CSE map.
const MachineInstr *MI = SU->getInstr();
if (MI->isPHI())
continue;
- for (const MachineOperand &MO : MI->operands())
- if (MO.isReg() && MO.isUse()) {
- Register Reg = MO.getReg();
- if (Reg.isVirtual())
- Uses.insert(Reg);
- else if (MRI.isAllocatable(Reg))
- for (MCRegUnitIterator Units(Reg.asMCReg(), TRI); Units.isValid();
- ++Units)
- Uses.insert(*Units);
- }
+ for (const MachineOperand &MO : MI->all_uses()) {
+ Register Reg = MO.getReg();
+ if (Reg.isVirtual())
+ Uses.insert(Reg);
+ else if (MRI.isAllocatable(Reg))
+ for (MCRegUnitIterator Units(Reg.asMCReg(), TRI); Units.isValid();
+ ++Units)
+ Uses.insert(*Units);
+ }
}
for (SUnit *SU : NS)
- for (const MachineOperand &MO : SU->getInstr()->operands())
- if (MO.isReg() && MO.isDef() && !MO.isDead()) {
+ for (const MachineOperand &MO : SU->getInstr()->all_defs())
+ if (!MO.isDead()) {
Register Reg = MO.getReg();
if (Reg.isVirtual()) {
if (!Uses.count(Reg))
if (!isLoopCarried(SSD, *Phi))
return false;
unsigned LoopReg = getLoopPhiReg(*Phi, Phi->getParent());
- for (MachineOperand &DMO : Def->operands()) {
- if (!DMO.isReg() || !DMO.isDef())
- continue;
+ for (MachineOperand &DMO : Def->all_defs()) {
if (DMO.getReg() == LoopReg)
return true;
}
void MachineSSAContext::appendBlockDefs(SmallVectorImpl<Register> &defs,
const MachineBasicBlock &block) {
for (const MachineInstr &instr : block.instrs()) {
- for (const MachineOperand &op : instr.operands()) {
- if (op.isReg() && op.isDef())
- defs.push_back(op.getReg());
- }
+ for (const MachineOperand &op : instr.all_defs())
+ defs.push_back(op.getReg());
}
}
// Ignore re-defs.
if (TrackLaneMasks) {
bool FoundDef = false;
- for (const MachineOperand &MO2 : MI.operands()) {
- if (MO2.isReg() && MO2.isDef() && MO2.getReg() == Reg && !MO2.isDead()) {
+ for (const MachineOperand &MO2 : MI.all_defs()) {
+ if (MO2.getReg() == Reg && !MO2.isDead()) {
FoundDef = true;
break;
}
// MI is cheap, we probably don't want to break the critical edge for it.
// However, if this would allow some definitions of its source operands
// to be sunk then it's probably worth it.
- for (const MachineOperand &MO : MI.operands()) {
- if (!MO.isReg() || !MO.isUse())
- continue;
+ for (const MachineOperand &MO : MI.all_uses()) {
Register Reg = MO.getReg();
if (Reg == 0)
continue;
// If the instruction to move defines a dead physical register which is live
// when leaving the basic block, don't move it because it could turn into a
// "zombie" define of that preg. E.g., EFLAGS. (<rdar://problem/8030636>)
- for (const MachineOperand &MO : MI.operands()) {
- if (!MO.isReg() || MO.isUse())
- continue;
+ for (const MachineOperand &MO : MI.all_defs()) {
Register Reg = MO.getReg();
if (Reg == 0 || !Reg.isPhysical())
continue;
// Collect debug users of any vreg that this inst defines.
SmallVector<MIRegs, 4> DbgUsersToSink;
- for (auto &MO : MI.operands()) {
- if (!MO.isReg() || !MO.isDef() || !MO.getReg().isVirtual())
+ for (auto &MO : MI.all_defs()) {
+ if (!MO.getReg().isVirtual())
continue;
if (!SeenDbgUsers.count(MO.getReg()))
continue;
// Note that we have to clear the kill flags for any register this instruction
// uses as we may sink over another instruction which currently kills the
// used registers.
- for (MachineOperand &MO : MI.operands()) {
- if (MO.isReg() && MO.isUse())
- RegsToClearKillFlags.insert(MO.getReg()); // Remember to clear kill flags.
- }
+ for (MachineOperand &MO : MI.all_uses())
+ RegsToClearKillFlags.insert(MO.getReg()); // Remember to clear kill flags.
return true;
}
SmallVector<MachineInstr *, 4> DbgDefUsers;
SmallVector<Register, 4> DbgUseRegs;
const MachineRegisterInfo &MRI = MI.getMF()->getRegInfo();
- for (auto &MO : MI.operands()) {
- if (!MO.isReg() || !MO.isDef() || !MO.getReg().isVirtual())
+ for (auto &MO : MI.all_defs()) {
+ if (!MO.getReg().isVirtual())
continue;
DbgUseRegs.push_back(MO.getReg());
for (auto &User : MRI.use_instructions(MO.getReg())) {
// recorded which reg units that DBG_VALUEs read, if this instruction
// writes any of those units then the corresponding DBG_VALUEs must sink.
MapVector<MachineInstr *, MIRegs::second_type> DbgValsToSinkMap;
- for (auto &MO : MI.operands()) {
- if (!MO.isReg() || !MO.isDef())
- continue;
-
+ for (auto &MO : MI.all_defs()) {
for (auto RI = MCRegUnitIterator(MO.getReg(), TRI); RI.isValid(); ++RI) {
for (const auto &MIRegs : SeenDbgInstrs.lookup(*RI)) {
auto &Regs = DbgValsToSinkMap[MIRegs.first];
template <>
bool llvm::GenericUniformityAnalysisImpl<MachineSSAContext>::hasDivergentDefs(
const MachineInstr &I) const {
- for (auto &op : I.operands()) {
- if (!op.isReg() || !op.isDef())
- continue;
+ for (auto &op : I.all_defs()) {
if (isDivergent(op.getReg()))
return true;
}
const auto &MRI = F.getRegInfo();
const auto &RBI = *F.getSubtarget().getRegBankInfo();
const auto &TRI = *MRI.getTargetRegisterInfo();
- for (auto &op : Instr.operands()) {
- if (!op.isReg() || !op.isDef())
- continue;
+ for (auto &op : Instr.all_defs()) {
if (!op.getReg().isVirtual())
continue;
assert(!op.getSubReg());
assert(!isAlwaysUniform(Instr));
if (Instr.isTerminator())
return;
- for (const MachineOperand &op : Instr.operands()) {
- if (!op.isReg() || !op.isDef())
- continue;
+ for (const MachineOperand &op : Instr.all_defs()) {
auto Reg = op.getReg();
if (isDivergent(Reg))
pushUsers(Reg);
propagateTemporalDivergence(const MachineInstr &I,
const MachineCycle &DefCycle) {
const auto &RegInfo = F.getRegInfo();
- for (auto &Op : I.operands()) {
- if (!Op.isReg() || !Op.isDef())
- continue;
+ for (auto &Op : I.all_defs()) {
if (!Op.getReg().isVirtual())
continue;
auto Reg = Op.getReg();
// stage difference for each use. Keep the maximum value.
for (MachineInstr *MI : Schedule.getInstructions()) {
int DefStage = Schedule.getStage(MI);
- for (const MachineOperand &Op : MI->operands()) {
- if (!Op.isReg() || !Op.isDef())
- continue;
-
+ for (const MachineOperand &Op : MI->all_defs()) {
Register Reg = Op.getReg();
unsigned MaxDiff = 0;
bool PhiIsSwapped = false;
continue;
}
bool used = true;
- for (const MachineOperand &MO : MI->operands()) {
- if (!MO.isReg() || !MO.isDef())
- continue;
+ for (const MachineOperand &MO : MI->all_defs()) {
Register reg = MO.getReg();
// Assume physical registers are used, unless they are marked dead.
if (reg.isPhysical()) {
!MI->isRegSequence() &&
!MI->isPHI())
return false;
- for (const MachineOperand &MO : MI->operands())
- if (MO.isReg() && MO.isUse() && MO.readsReg())
+ for (const MachineOperand &MO : MI->all_uses())
+ if (MO.readsReg())
return false;
return true;
}
auto isDefUndef = [this] (const MachineInstr &In, RegisterRef DR) -> bool {
// This instruction defines DR. Check if there is a use operand that
// would make DR live on entry to the instruction.
- for (const MachineOperand &Op : In.operands()) {
- if (!Op.isReg() || Op.getReg() == 0 || !Op.isUse() || Op.isUndef())
+ for (const MachineOperand &Op : In.all_uses()) {
+ if (Op.getReg() == 0 || Op.isUndef())
continue;
RegisterRef UR = makeRegRef(Op);
if (PRI.alias(DR, UR))
continue;
MI.clearKillInfo();
- for (auto &Op : MI.operands()) {
+ for (auto &Op : MI.all_defs()) {
// An implicit def of a super-register may not necessarily start a
// live range of it, since an implicit use could be used to keep parts
// of it live. Instead of analyzing the implicit operands, ignore
// implicit defs.
- if (!Op.isReg() || !Op.isDef() || Op.isImplicit())
+ if (Op.isImplicit())
continue;
Register R = Op.getReg();
if (!R.isPhysical())
for (MCPhysReg SR : TRI.subregs_inclusive(R))
Live.reset(SR);
}
- for (auto &Op : MI.operands()) {
- if (!Op.isReg() || !Op.isUse() || Op.isUndef())
+ for (auto &Op : MI.all_uses()) {
+ if (Op.isUndef())
continue;
Register R = Op.getReg();
if (!R.isPhysical())
// like ` = OP undef %X, %X` both operands need the same register assign
// so we should perform the normal assignment first.
if (HasUndefUse) {
- for (MachineOperand &MO : MI.uses()) {
- if (!MO.isReg() || !MO.isUse())
- continue;
+ for (MachineOperand &MO : MI.all_uses()) {
Register Reg = MO.getReg();
if (!Reg.isVirtual() || !shouldAllocateRegister(Reg))
continue;
// Free early clobbers.
if (HasEarlyClobber) {
- for (MachineOperand &MO : llvm::reverse(MI.operands())) {
- if (!MO.isReg() || !MO.isDef() || !MO.isEarlyClobber())
+ for (MachineOperand &MO : llvm::reverse(MI.all_defs())) {
+ if (!MO.isEarlyClobber())
continue;
assert(!MO.getSubReg() && "should be already handled in def processing");
static bool definesFullReg(const MachineInstr &MI, Register Reg) {
assert(!Reg.isPhysical() && "This code cannot handle physreg aliasing");
- for (const MachineOperand &Op : MI.operands()) {
- if (!Op.isReg() || !Op.isDef() || Op.getReg() != Reg)
+ for (const MachineOperand &Op : MI.all_defs()) {
+ if (Op.getReg() != Reg)
continue;
// Return true if we define the full register or don't care about the value
// inside other subregisters.
// is still part of the function (but about to be erased), mark all
// defs of DstReg in it as <undef>, so that shrinkToUses would
// ignore them.
- for (MachineOperand &MO : CopyMI->operands())
- if (MO.isReg() && MO.isDef() && MO.getReg() == DstReg)
+ for (MachineOperand &MO : CopyMI->all_defs())
+ if (MO.getReg() == DstReg)
MO.setIsUndef(true);
LIS->shrinkToUses(&DstLI);
LaneBitmask JoinVals::computeWriteLanes(const MachineInstr *DefMI, bool &Redef)
const {
LaneBitmask L;
- for (const MachineOperand &MO : DefMI->operands()) {
- if (!MO.isReg() || MO.getReg() != Reg || !MO.isDef())
+ for (const MachineOperand &MO : DefMI->all_defs()) {
+ if (MO.getReg() != Reg)
continue;
L |= TRI->getSubRegIndexLaneMask(
TRI->composeSubRegIndices(SubIdx, MO.getSubReg()));
LaneBitmask Lanes) const {
if (MI.isDebugOrPseudoInstr())
return false;
- for (const MachineOperand &MO : MI.operands()) {
- if (!MO.isReg() || MO.isDef() || MO.getReg() != Reg)
+ for (const MachineOperand &MO : MI.all_uses()) {
+ if (MO.getReg() != Reg)
continue;
if (!MO.readsReg())
continue;
ExitSU.setInstr(ExitMI);
// Add dependencies on the defs and uses of the instruction.
if (ExitMI) {
- for (const MachineOperand &MO : ExitMI->operands()) {
- if (!MO.isReg() || MO.isDef()) continue;
+ for (const MachineOperand &MO : ExitMI->all_uses()) {
Register Reg = MO.getReg();
if (Reg.isPhysical()) {
Uses.insert(PhysRegSUOper(&ExitSU, -1, Reg));
if (AllUsesCopied) {
LaneBitmask RemainingUses = LaneBitmask::getNone();
// Replace other (un-tied) uses of regB with LastCopiedReg.
- for (MachineOperand &MO : MI->operands()) {
- if (MO.isReg() && MO.getReg() == RegB && MO.isUse()) {
+ for (MachineOperand &MO : MI->all_uses()) {
+ if (MO.getReg() == RegB) {
if (MO.getSubReg() == SubRegB && !IsEarlyClobber) {
if (MO.isKill()) {
MO.setIsKill(false);
// regB is still used in this instruction, but a kill flag was
// removed from a different tied use of regB, so now we need to add
// a kill flag to one of the remaining uses of regB.
- for (MachineOperand &MO : MI->operands()) {
- if (MO.isReg() && MO.getReg() == RegB && MO.isUse()) {
+ for (MachineOperand &MO : MI->all_uses()) {
+ if (MO.getReg() == RegB) {
MO.setIsKill(true);
break;
}