spi: xilinx_spi: Fix spi reset
authorJiajie Chen <c@jia.je>
Mon, 27 Feb 2023 15:09:39 +0000 (23:09 +0800)
committerMichal Simek <michal.simek@amd.com>
Thu, 9 Mar 2023 12:15:00 +0000 (13:15 +0100)
It was incorrectly using an old priv->regs pointer, which was
initialized to zero. SPI resets won't happen on first call.

Signed-off-by: Jiajie Chen <c@jia.je>
Link: https://lore.kernel.org/r/20230227150938.211820-1-c@jia.je
Signed-off-by: Michal Simek <michal.simek@amd.com>
drivers/spi/xilinx_spi.c

index 4e9115d..9e6255a 100644 (file)
@@ -112,10 +112,9 @@ struct xilinx_spi_priv {
 static int xilinx_spi_probe(struct udevice *bus)
 {
        struct xilinx_spi_priv *priv = dev_get_priv(bus);
-       struct xilinx_spi_regs *regs = priv->regs;
-
-       priv->regs = (struct xilinx_spi_regs *)dev_read_addr(bus);
+       struct xilinx_spi_regs *regs;
 
+       regs = priv->regs = (struct xilinx_spi_regs *)dev_read_addr(bus);
        priv->fifo_depth = dev_read_u32_default(bus, "fifo-size", 0);
 
        writel(SPISSR_RESET_VALUE, &regs->srr);