clk: sunxi-ng: v3s: Fix incorrect number of hw_clks.
authorYunhao Tian <18373444@buaa.edu.cn>
Mon, 25 Nov 2019 12:58:32 +0000 (20:58 +0800)
committerMaxime Ripard <maxime@cerno.tech>
Mon, 9 Dec 2019 07:49:31 +0000 (08:49 +0100)
The hws field of sun8i_v3s_hw_clks has only 74
members. However, the number specified by CLK_NUMBER
is 77 (= CLK_I2S0 + 1). This leads to runtime segmentation
fault that is not always reproducible.

This patch fixes the problem by specifying correct clock number.

Signed-off-by: Yunhao Tian <18373444@buaa.edu.cn>
[Maxime: Also remove the CLK_NUMBER definition]
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
drivers/clk/sunxi-ng/ccu-sun8i-v3s.c
drivers/clk/sunxi-ng/ccu-sun8i-v3s.h

index 5c779ee..0e36ca3 100644 (file)
@@ -618,7 +618,7 @@ static struct clk_hw_onecell_data sun8i_v3s_hw_clks = {
                [CLK_MBUS]              = &mbus_clk.common.hw,
                [CLK_MIPI_CSI]          = &mipi_csi_clk.common.hw,
        },
-       .num    = CLK_NUMBER,
+       .num    = CLK_PLL_DDR1 + 1,
 };
 
 static struct clk_hw_onecell_data sun8i_v3_hw_clks = {
@@ -700,7 +700,7 @@ static struct clk_hw_onecell_data sun8i_v3_hw_clks = {
                [CLK_MBUS]              = &mbus_clk.common.hw,
                [CLK_MIPI_CSI]          = &mipi_csi_clk.common.hw,
        },
-       .num    = CLK_NUMBER,
+       .num    = CLK_I2S0 + 1,
 };
 
 static struct ccu_reset_map sun8i_v3s_ccu_resets[] = {
index b0160d3..108eeee 100644 (file)
@@ -51,6 +51,4 @@
 
 #define CLK_PLL_DDR1           74
 
-#define CLK_NUMBER             (CLK_I2S0 + 1)
-
 #endif /* _CCU_SUN8I_H3_H_ */