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dw-i2c: correct I2C FIFO size to 256 bytes
authorLi, Ning <ning.li@intel.com>
Fri, 18 May 2012 05:13:40 +0000 (13:13 +0800)
committerbuildbot <buildbot@intel.com>
Wed, 23 May 2012 01:35:07 +0000 (18:35 -0700)
BZ: 37123

I2C FIFO is set as 32 bytes in current driver. It will impact our
customer touchscreen driver implementation. Based on silicon team
feedback, need to correct I2C FIFO size to 256 bytes.
Meanwhile, correct one log description.

Change-Id: Icb07a9251cf24eeda76b1cbbf9f1d6ac83c506c5
Signed-off-by: Li, Ning <ning.li@intel.com>
Reviewed-on: http://android.intel.com:8080/49305
Reviewed-by: Yang, Bin <bin.yang@intel.com>
Reviewed-by: Du, Alek <alek.du@intel.com>
Reviewed-by: Chen, Jie D <jie.d.chen@intel.com>
Tested-by: Tang, HaifengX <haifengx.tang@intel.com>
Reviewed-by: buildbot <buildbot@intel.com>
Tested-by: buildbot <buildbot@intel.com>
drivers/i2c/busses/i2c-designware-core.c patch | blob | history
drivers/i2c/busses/i2c-designware-pcidrv.c patch | blob | history

diff --git a/drivers/i2c/busses/i2c-designware-core.c b/drivers/i2c/busses/i2c-designware-core.c
index 9452eb0..7e77703 100644 (file)
--- a/drivers/i2c/busses/i2c-designware-core.c
+++ b/drivers/i2c/busses/i2c-designware-core.c
@@ -321,7 +321,7 @@ i2c_dw_xfer_msg(struct dw_i2c_dev *dev)
        /* if fifo only has one byte, it is not safe */
        if ((dev->status & STATUS_WRITE_IN_PROGRESS) &&
                (dw_readl(dev, DW_IC_TXFLR) < 1)) {
-               dev_err(dev->dev, "TX FIFO overrun, addr: 0x%x.\n", addr);
+               dev_err(dev->dev, "TX FIFO underrun, addr: 0x%x.\n", addr);
                dev->msg_err = -EAGAIN;
        }
 
diff --git a/drivers/i2c/busses/i2c-designware-pcidrv.c b/drivers/i2c/busses/i2c-designware-pcidrv.c
index f5a52be..0468c88 100644 (file)
--- a/drivers/i2c/busses/i2c-designware-pcidrv.c
+++ b/drivers/i2c/busses/i2c-designware-pcidrv.c
@@ -133,48 +133,48 @@ static struct  dw_pci_controller  dw_pci_controllers[] = {
        [medfield_0] = {
                .bus_num     = 0,
                .bus_cfg   = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
-               .tx_fifo_depth = 32,
-               .rx_fifo_depth = 32,
+               .tx_fifo_depth = 256,
+               .rx_fifo_depth = 256,
                .clk_khz      = 17000,
                .scl_cfg = mfld_i2c_scl_cfg,
        },
        [medfield_1] = {
                .bus_num     = 1,
                .bus_cfg   = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_STD,
-               .tx_fifo_depth = 32,
-               .rx_fifo_depth = 32,
+               .tx_fifo_depth = 256,
+               .rx_fifo_depth = 256,
                .clk_khz      = 20500,
                .scl_cfg = mfld_i2c_scl_cfg,
        },
        [medfield_2] = {
                .bus_num     = 2,
                .bus_cfg   = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
-               .tx_fifo_depth = 32,
-               .rx_fifo_depth = 32,
+               .tx_fifo_depth = 256,
+               .rx_fifo_depth = 256,
                .clk_khz      = 17000,
                .scl_cfg = mfld_i2c_scl_cfg,
        },
        [medfield_3] = {
                .bus_num     = 3,
                .bus_cfg   = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_STD,
-               .tx_fifo_depth = 32,
-               .rx_fifo_depth = 32,
+               .tx_fifo_depth = 256,
+               .rx_fifo_depth = 256,
                .clk_khz      = 20500,
                .scl_cfg = mfld_i2c_scl_cfg,
        },
        [medfield_4] = {
                .bus_num     = 4,
                .bus_cfg   = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
-               .tx_fifo_depth = 32,
-               .rx_fifo_depth = 32,
+               .tx_fifo_depth = 256,
+               .rx_fifo_depth = 256,
                .clk_khz      = 17000,
                .scl_cfg = mfld_i2c_scl_cfg,
        },
        [medfield_5] = {
                .bus_num     = 5,
                .bus_cfg   = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
-               .tx_fifo_depth = 32,
-               .rx_fifo_depth = 32,
+               .tx_fifo_depth = 256,
+               .rx_fifo_depth = 256,
                .clk_khz      = 17000,
                .scl_cfg = mfld_i2c_scl_cfg,
        },
@@ -182,48 +182,48 @@ static struct  dw_pci_controller  dw_pci_controllers[] = {
        [cloverview_0] = {
                .bus_num     = 0,
                .bus_cfg   = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
-               .tx_fifo_depth = 32,
-               .rx_fifo_depth = 32,
+               .tx_fifo_depth = 256,
+               .rx_fifo_depth = 256,
                .clk_khz      = 17000,
                .scl_cfg = ctp_i2c_scl_cfg,
        },
        [cloverview_1] = {
                .bus_num     = 1,
                .bus_cfg   = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
-               .tx_fifo_depth = 32,
-               .rx_fifo_depth = 32,
+               .tx_fifo_depth = 256,
+               .rx_fifo_depth = 256,
                .clk_khz      = 17000,
                .scl_cfg = ctp_i2c_scl_cfg,
        },
        [cloverview_2] = {
                .bus_num     = 2,
                .bus_cfg   = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
-               .tx_fifo_depth = 32,
-               .rx_fifo_depth = 32,
+               .tx_fifo_depth = 256,
+               .rx_fifo_depth = 256,
                .clk_khz      = 17000,
                .scl_cfg = ctp_i2c_scl_cfg,
        },
        [cloverview_3] = {
                .bus_num     = 3,
                .bus_cfg   = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_STD,
-               .tx_fifo_depth = 32,
-               .rx_fifo_depth = 32,
+               .tx_fifo_depth = 256,
+               .rx_fifo_depth = 256,
                .clk_khz      = 20500,
                .scl_cfg = ctp_i2c_scl_cfg,
        },
        [cloverview_4] = {
                .bus_num     = 4,
                .bus_cfg   = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
-               .tx_fifo_depth = 32,
-               .rx_fifo_depth = 32,
+               .tx_fifo_depth = 256,
+               .rx_fifo_depth = 256,
                .clk_khz      = 17000,
                .scl_cfg = ctp_i2c_scl_cfg,
        },
        [cloverview_5] = {
                .bus_num     = 5,
                .bus_cfg   = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
-               .tx_fifo_depth = 32,
-               .rx_fifo_depth = 32,
+               .tx_fifo_depth = 256,
+               .rx_fifo_depth = 256,
                .clk_khz      = 17000,
                .scl_cfg = ctp_i2c_scl_cfg,
        },
Domain: System / Kernel;