arm64: dts: qcom: Fix ordering of 'clocks' & 'clock-names' for sdhci nodes

Since the Qualcomm sdhci-msm device-tree binding has been converted
to yaml format, 'make dtbs_check' reports a number of issues with
ordering of 'clocks' & 'clock-names' for sdhci nodes:

 arch/arm64/boot/dts/qcom/ipq8074-hk10-c2.dtb: sdhci@7824900:
  clock-names:0: 'iface' was expected

 arch/arm64/boot/dts/qcom/ipq8074-hk10-c2.dtb: sdhci@7824900:
  clock-names:1: 'core' was expected

 arch/arm64/boot/dts/qcom/ipq8074-hk10-c2.dtb: sdhci@7824900:
  clock-names:2: 'xo' was expected

Fix the same by updating the offending 'dts' files.

Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Rob Herring <robh@kernel.org>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220514215424.1007718-5-bhupesh.sharma@linaro.org

diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
index 3ad8255..46d2f05 100644 (file)
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -384,10 +384,10 @@
                                     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
                        interrupt-names = "hc_irq", "pwr_irq";
 
-                       clocks = <&xo>,
-                                <&gcc GCC_SDCC1_AHB_CLK>,
-                                <&gcc GCC_SDCC1_APPS_CLK>;
-                       clock-names = "xo", "iface", "core";
+                       clocks = <&gcc GCC_SDCC1_AHB_CLK>,
+                                <&gcc GCC_SDCC1_APPS_CLK>,
+                                <&xo>;
+                       clock-names = "iface", "core", "xo";
                        max-frequency = <384000000>;
                        mmc-ddr-1_8v;
                        mmc-hs200-1_8v;

diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi
index a5d3203..09f76d7 100644 (file)
--- a/arch/arm64/boot/dts/qcom/msm8916.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi
@@ -1472,10 +1472,10 @@
                        interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
                                     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
                        interrupt-names = "hc_irq", "pwr_irq";
-                       clocks = <&gcc GCC_SDCC1_APPS_CLK>,
-                                <&gcc GCC_SDCC1_AHB_CLK>,
+                       clocks = <&gcc GCC_SDCC1_AHB_CLK>,
+                                <&gcc GCC_SDCC1_APPS_CLK>,
                                 <&xo_board>;
-                       clock-names = "core", "iface", "xo";
+                       clock-names = "iface", "core", "xo";
                        mmc-ddr-1_8v;
                        bus-width = <8>;
                        non-removable;
@@ -1490,10 +1490,10 @@
                        interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
                                     <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
                        interrupt-names = "hc_irq", "pwr_irq";
-                       clocks = <&gcc GCC_SDCC2_APPS_CLK>,
-                                <&gcc GCC_SDCC2_AHB_CLK>,
+                       clocks = <&gcc GCC_SDCC2_AHB_CLK>,
+                                <&gcc GCC_SDCC2_APPS_CLK>,
                                 <&xo_board>;
-                       clock-names = "core", "iface", "xo";
+                       clock-names = "iface", "core", "xo";
                        bus-width = <4>;
                        status = "disabled";
                };

diff --git a/arch/arm64/boot/dts/qcom/msm8994.dtsi b/arch/arm64/boot/dts/qcom/msm8994.dtsi
index 99230e8..362960d 100644 (file)
--- a/arch/arm64/boot/dts/qcom/msm8994.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8994.dtsi
@@ -470,10 +470,10 @@
                                     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
                        interrupt-names = "hc_irq", "pwr_irq";
 
-                       clocks = <&gcc GCC_SDCC1_APPS_CLK>,
-                                <&gcc GCC_SDCC1_AHB_CLK>,
+                       clocks = <&gcc GCC_SDCC1_AHB_CLK>,
+                                <&gcc GCC_SDCC1_APPS_CLK>,
                                 <&xo_board>;
-                       clock-names = "core", "iface", "xo";
+                       clock-names = "iface", "core", "xo";
 
                        pinctrl-names = "default", "sleep";
                        pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>;
@@ -493,10 +493,10 @@
                                <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
                        interrupt-names = "hc_irq", "pwr_irq";
 
-                       clocks = <&gcc GCC_SDCC2_APPS_CLK>,
-                               <&gcc GCC_SDCC2_AHB_CLK>,
-                               <&xo_board>;
-                       clock-names = "core", "iface", "xo";
+                       clocks = <&gcc GCC_SDCC2_AHB_CLK>,
+                                <&gcc GCC_SDCC2_APPS_CLK>,
+                                <&xo_board>;
+                       clock-names = "iface", "core", "xo";
 
                        pinctrl-names = "default", "sleep";
                        pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on>;

diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi
index 8592d85..badfd93 100644 (file)
--- a/arch/arm64/boot/dts/qcom/qcs404.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi
@@ -815,10 +815,10 @@
                                     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
                        interrupt-names = "hc_irq", "pwr_irq";
 
-                       clocks = <&gcc GCC_SDCC1_APPS_CLK>,
-                                <&gcc GCC_SDCC1_AHB_CLK>,
+                       clocks = <&gcc GCC_SDCC1_AHB_CLK>,
+                                <&gcc GCC_SDCC1_APPS_CLK>,
                                 <&xo_board>;
-                       clock-names = "core", "iface", "xo";
+                       clock-names = "iface", "core", "xo";
 
                        status = "disabled";
                };

diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index f03f237..8dae9cd 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
@@ -704,10 +704,10 @@
                                        <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>;
                        interrupt-names = "hc_irq", "pwr_irq";
 
-                       clocks = <&gcc GCC_SDCC1_APPS_CLK>,
-                                <&gcc GCC_SDCC1_AHB_CLK>,
+                       clocks = <&gcc GCC_SDCC1_AHB_CLK>,
+                                <&gcc GCC_SDCC1_APPS_CLK>,
                                 <&rpmhcc RPMH_CXO_CLK>;
-                       clock-names = "core", "iface", "xo";
+                       clock-names = "iface", "core", "xo";
                        interconnects = <&aggre1_noc MASTER_EMMC 0 &mc_virt SLAVE_EBI1 0>,
                                        <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_EMMC_CFG 0>;
                        interconnect-names = "sdhc-ddr","cpu-sdhc";
@@ -2587,10 +2587,10 @@
                                        <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
                        interrupt-names = "hc_irq", "pwr_irq";
 
-                       clocks = <&gcc GCC_SDCC2_APPS_CLK>,
-                                <&gcc GCC_SDCC2_AHB_CLK>,
+                       clocks = <&gcc GCC_SDCC2_AHB_CLK>,
+                                <&gcc GCC_SDCC2_APPS_CLK>,
                                 <&rpmhcc RPMH_CXO_CLK>;
-                       clock-names = "core", "iface", "xo";
+                       clock-names = "iface", "core", "xo";
 
                        interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,
                                        <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>;

diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index af2f9e9..0a116e1 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -873,10 +873,10 @@
                                     <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH>;
                        interrupt-names = "hc_irq", "pwr_irq";
 
-                       clocks = <&gcc GCC_SDCC1_APPS_CLK>,
-                                <&gcc GCC_SDCC1_AHB_CLK>,
+                       clocks = <&gcc GCC_SDCC1_AHB_CLK>,
+                                <&gcc GCC_SDCC1_APPS_CLK>,
                                 <&rpmhcc RPMH_CXO_CLK>;
-                       clock-names = "core", "iface", "xo";
+                       clock-names = "iface", "core", "xo";
                        interconnects = <&aggre1_noc MASTER_SDCC_1 0 &mc_virt SLAVE_EBI1 0>,
                                        <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_1 0>;
                        interconnect-names = "sdhc-ddr","cpu-sdhc";
@@ -3042,10 +3042,10 @@
                                     <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
                        interrupt-names = "hc_irq", "pwr_irq";
 
-                       clocks = <&gcc GCC_SDCC2_APPS_CLK>,
-                                <&gcc GCC_SDCC2_AHB_CLK>,
+                       clocks = <&gcc GCC_SDCC2_AHB_CLK>,
+                                <&gcc GCC_SDCC2_APPS_CLK>,
                                 <&rpmhcc RPMH_CXO_CLK>;
-                       clock-names = "core", "iface", "xo";
+                       clock-names = "iface", "core", "xo";
                        interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,
                                        <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_2 0>;
                        interconnect-names = "sdhc-ddr","cpu-sdhc";

diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi
index d31e46d..17ef35e 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sdm630.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi
@@ -1287,10 +1287,12 @@
                        interrupt-names = "hc_irq", "pwr_irq";
 
                        bus-width = <4>;
-                       clocks = <&gcc GCC_SDCC2_APPS_CLK>,
-                                       <&gcc GCC_SDCC2_AHB_CLK>,
+
+                       clocks = <&gcc GCC_SDCC2_AHB_CLK>,
+                                       <&gcc GCC_SDCC2_APPS_CLK>,
                                        <&xo_board>;
-                       clock-names = "core", "iface", "xo";
+                       clock-names = "iface", "core", "xo";
+
 
                        interconnects = <&a2noc 3 &a2noc 10>,
                                        <&gnoc 0 &cnoc 28>;
@@ -1339,11 +1341,11 @@
                                        <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
                        interrupt-names = "hc_irq", "pwr_irq";
 
-                       clocks = <&gcc GCC_SDCC1_APPS_CLK>,
-                                <&gcc GCC_SDCC1_AHB_CLK>,
+                       clocks = <&gcc GCC_SDCC1_AHB_CLK>,
+                                <&gcc GCC_SDCC1_APPS_CLK>,
                                 <&xo_board>,
                                 <&gcc GCC_SDCC1_ICE_CORE_CLK>;
-                       clock-names = "core", "iface", "xo", "ice";
+                       clock-names = "iface", "core", "xo", "ice";
 
                        interconnects = <&a2noc 2 &a2noc 10>,
                                        <&gnoc 0 &cnoc 27>;