(define_expand "one_cmpl<mode>2"
[(set (match_operand:VDQ 0 "s_register_operand")
(not:VDQ (match_operand:VDQ 1 "s_register_operand")))]
- "ARM_HAVE_<MODE>_ARITH"
+ "ARM_HAVE_<MODE>_ARITH && !TARGET_REALLY_IWMMXT"
)
(define_expand "neg<mode>2"
[(set (match_operand:VDQWH 0 "s_register_operand" "")
(neg:VDQWH (match_operand:VDQWH 1 "s_register_operand" "")))]
- "ARM_HAVE_<MODE>_ARITH"
+ "ARM_HAVE_<MODE>_ARITH && !TARGET_REALLY_IWMMXT"
)
(define_expand "cadd<rot><mode>3"
[(set (match_operand:VDQX 0 "neon_perm_struct_or_reg_operand")
(unspec:VDQX [(match_operand:VDQX 1 "neon_perm_struct_or_reg_operand")]
UNSPEC_MISALIGNED_ACCESS))]
- "ARM_HAVE_<MODE>_LDST && !BYTES_BIG_ENDIAN && unaligned_access"
+ "ARM_HAVE_<MODE>_LDST && !BYTES_BIG_ENDIAN
+ && unaligned_access && !TARGET_REALLY_IWMMXT"
{
rtx adjust_mem;
/* This pattern is not permitted to fail during expansion: if both arguments
--- /dev/null
+/* PR target/99724 */
+/* { dg-do compile } */
+/* { dg-skip-if "Test is specific to the iWMMXt" { arm*-*-* } { "-mcpu=*" } { "-mcpu=iwmmxt" } } */
+/* { dg-skip-if "Test is specific to the iWMMXt" { arm*-*-* } { "-mabi=*" } { "-mabi=iwmmxt" } } */
+/* { dg-skip-if "Test is specific to the iWMMXt" { arm*-*-* } { "-march=*" } { "-march=iwmmxt" } } */
+/* { dg-skip-if "Test is specific to ARM mode" { arm*-*-* } { "-mthumb" } { "" } } */
+/* { dg-require-effective-target arm32 } */
+/* { dg-require-effective-target arm_iwmmxt_ok } */
+/* { dg-options "-O1 -mcpu=iwmmxt" } */
+
+typedef int V __attribute__((vector_size (8)));
+struct __attribute__((packed)) S { char a; V b; char c[7]; };
+
+void
+foo (V *x)
+{
+ *x = ~*x;
+}
+
+void
+bar (V *x)
+{
+ *x = -*x;
+}
+
+void
+baz (V *x, struct S *p)
+{
+ V y = p->b;
+ *x = y;
+}