amd: lower multi-component subdword SSBO loads in NIR
authorMarek Olšák <marek.olsak@amd.com>
Sun, 6 Nov 2022 20:58:47 +0000 (15:58 -0500)
committerMarge Bot <emma+marge@anholt.net>
Fri, 3 Mar 2023 03:27:40 +0000 (03:27 +0000)
because the hw and LLVM only support subdword single-component SSBO loads,
and ac_nir_to_llvm splits multi-component loads because of that, which is
inefficient.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19399>

src/amd/vulkan/radv_pipeline.c
src/gallium/drivers/radeonsi/si_shader_nir.c

index f16b217..d7bc407 100644 (file)
@@ -3185,7 +3185,7 @@ radv_postprocess_nir(struct radv_pipeline *pipeline,
    NIR_PASS(_, stage->nir, ac_nir_lower_subdword_loads,
             (ac_nir_lower_subdword_options) {
                .modes_1_comp = nir_var_mem_ubo,
-               .modes_N_comps = nir_var_mem_ubo
+               .modes_N_comps = nir_var_mem_ubo | nir_var_mem_ssbo
             });
 
    progress = false;
index 624e411..db2ac4c 100644 (file)
@@ -362,7 +362,7 @@ char *si_finalize_nir(struct pipe_screen *screen, void *nirptr)
    NIR_PASS_V(nir, ac_nir_lower_subdword_loads,
               (ac_nir_lower_subdword_options) {
                  .modes_1_comp = nir_var_mem_ubo,
-                 .modes_N_comps = nir_var_mem_ubo
+                 .modes_N_comps = nir_var_mem_ubo | nir_var_mem_ssbo
               });
    NIR_PASS_V(nir, nir_lower_explicit_io, nir_var_mem_shared, nir_address_format_32bit_offset);