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clk: ti: dra7xx: fix RNG clock parent
author
Tero Kristo
<t-kristo@ti.com>
Thu, 30 Apr 2020 08:36:40 +0000
(11:36 +0300)
committer
Stephen Boyd
<sboyd@kernel.org>
Thu, 14 May 2020 19:55:31 +0000
(12:55 -0700)
RNG is sourced from L4 clock. Add info for this for proper parenting of
the clock.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Link:
https://lkml.kernel.org/r/20200430083640.8621-4-t-kristo@ti.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
drivers/clk/ti/clk-7xx.c
patch
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diff --git
a/drivers/clk/ti/clk-7xx.c
b/drivers/clk/ti/clk-7xx.c
index
146d1d6
..
bf8fced
100644
(file)
--- a/
drivers/clk/ti/clk-7xx.c
+++ b/
drivers/clk/ti/clk-7xx.c
@@
-644,7
+644,7
@@
static const struct omap_clkctrl_reg_data dra7_l4sec_clkctrl_regs[] __initconst
{ DRA7_L4SEC_AES1_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
{ DRA7_L4SEC_AES2_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
{ DRA7_L4SEC_DES_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
- { DRA7_L4SEC_RNG_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_SOC_NONSEC, "" },
+ { DRA7_L4SEC_RNG_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_SOC_NONSEC, "
l4_root_clk_div
" },
{ DRA7_L4SEC_SHAM_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
{ 0 },
};