ARM: tegra: apalis_t30: reorder pcie properties
authorMarcel Ziswiler <marcel.ziswiler@toradex.com>
Fri, 31 Aug 2018 16:37:46 +0000 (18:37 +0200)
committerThierry Reding <treding@nvidia.com>
Wed, 26 Sep 2018 14:45:41 +0000 (16:45 +0200)
Reorder PCIe properties.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
arch/arm/boot/dts/tegra30-apalis.dtsi

index f13df31..fc279a0 100644 (file)
 
        pcie@3000 {
                avdd-pexa-supply = <&vdd2_reg>;
-               vdd-pexa-supply = <&vdd2_reg>;
                avdd-pexb-supply = <&vdd2_reg>;
-               vdd-pexb-supply = <&vdd2_reg>;
                avdd-pex-pll-supply = <&vdd2_reg>;
                avdd-plle-supply = <&ldo6_reg>;
-               vddio-pex-ctl-supply = <&sys_3v3_reg>;
                hvdd-pex-supply = <&sys_3v3_reg>;
+               vddio-pex-ctl-supply = <&sys_3v3_reg>;
+               vdd-pexa-supply = <&vdd2_reg>;
+               vdd-pexb-supply = <&vdd2_reg>;
 
                pci@1,0 {
                        nvidia,num-lanes = <4>;