pinctrl: pinctrl-imx: add imx51 pinctrl driver

ChangeLog v1->v2:
* change PIN_FUNC_ID base in binding doc to 0 from 1.

Acked-by: Shawn Guo <shawn.guo@linaro.org>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Dong Aisheng <dong.aisheng@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx51-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx51-pinctrl.txt
new file mode 100644 (file)
index 0000000..b96fa4c
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx51-pinctrl.txt
@@ -0,0 +1,787 @@
+* Freescale IMX51 IOMUX Controller
+
+Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
+and usage.
+
+Required properties:
+- compatible: "fsl,imx51-iomuxc"
+- fsl,pins: two integers array, represents a group of pins mux and config
+  setting. The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is a
+  pin working on a specific function, CONFIG is the pad setting value like
+  pull-up for this pin. Please refer to imx51 datasheet for the valid pad
+  config settings.
+
+CONFIG bits definition:
+PAD_CTL_HVE                    (1 << 13)
+PAD_CTL_HYS                    (1 << 8)
+PAD_CTL_PKE                    (1 << 7)
+PAD_CTL_PUE                    (1 << 6)
+PAD_CTL_PUS_100K_DOWN          (0 << 4)
+PAD_CTL_PUS_47K_UP             (1 << 4)
+PAD_CTL_PUS_100K_UP            (2 << 4)
+PAD_CTL_PUS_22K_UP             (3 << 4)
+PAD_CTL_ODE                    (1 << 3)
+PAD_CTL_DSE_LOW                        (0 << 1)
+PAD_CTL_DSE_MED                        (1 << 1)
+PAD_CTL_DSE_HIGH               (2 << 1)
+PAD_CTL_DSE_MAX                        (3 << 1)
+PAD_CTL_SRE_FAST               (1 << 0)
+PAD_CTL_SRE_SLOW               (0 << 0)
+
+See below for available PIN_FUNC_ID for imx51:
+MX51_PAD_EIM_D16__AUD4_RXFS                    0
+MX51_PAD_EIM_D16__AUD5_TXD                     1
+MX51_PAD_EIM_D16__EIM_D16                      2
+MX51_PAD_EIM_D16__GPIO2_0                      3
+MX51_PAD_EIM_D16__I2C1_SDA                     4
+MX51_PAD_EIM_D16__UART2_CTS                    5
+MX51_PAD_EIM_D16__USBH2_DATA0                  6
+MX51_PAD_EIM_D17__AUD5_RXD                     7
+MX51_PAD_EIM_D17__EIM_D17                      8
+MX51_PAD_EIM_D17__GPIO2_1                      9
+MX51_PAD_EIM_D17__UART2_RXD                    10
+MX51_PAD_EIM_D17__UART3_CTS                    11
+MX51_PAD_EIM_D17__USBH2_DATA1                  12
+MX51_PAD_EIM_D18__AUD5_TXC                     13
+MX51_PAD_EIM_D18__EIM_D18                      14
+MX51_PAD_EIM_D18__GPIO2_2                      15
+MX51_PAD_EIM_D18__UART2_TXD                    16
+MX51_PAD_EIM_D18__UART3_RTS                    17
+MX51_PAD_EIM_D18__USBH2_DATA2                  18
+MX51_PAD_EIM_D19__AUD4_RXC                     19
+MX51_PAD_EIM_D19__AUD5_TXFS                    20
+MX51_PAD_EIM_D19__EIM_D19                      21
+MX51_PAD_EIM_D19__GPIO2_3                      22
+MX51_PAD_EIM_D19__I2C1_SCL                     23
+MX51_PAD_EIM_D19__UART2_RTS                    24
+MX51_PAD_EIM_D19__USBH2_DATA3                  25
+MX51_PAD_EIM_D20__AUD4_TXD                     26
+MX51_PAD_EIM_D20__EIM_D20                      27
+MX51_PAD_EIM_D20__GPIO2_4                      28
+MX51_PAD_EIM_D20__SRTC_ALARM_DEB               29
+MX51_PAD_EIM_D20__USBH2_DATA4                  30
+MX51_PAD_EIM_D21__AUD4_RXD                     31
+MX51_PAD_EIM_D21__EIM_D21                      32
+MX51_PAD_EIM_D21__GPIO2_5                      33
+MX51_PAD_EIM_D21__SRTC_ALARM_DEB               34
+MX51_PAD_EIM_D21__USBH2_DATA5                  35
+MX51_PAD_EIM_D22__AUD4_TXC                     36
+MX51_PAD_EIM_D22__EIM_D22                      37
+MX51_PAD_EIM_D22__GPIO2_6                      38
+MX51_PAD_EIM_D22__USBH2_DATA6                  39
+MX51_PAD_EIM_D23__AUD4_TXFS                    40
+MX51_PAD_EIM_D23__EIM_D23                      41
+MX51_PAD_EIM_D23__GPIO2_7                      42
+MX51_PAD_EIM_D23__SPDIF_OUT1                   43
+MX51_PAD_EIM_D23__USBH2_DATA7                  44
+MX51_PAD_EIM_D24__AUD6_RXFS                    45
+MX51_PAD_EIM_D24__EIM_D24                      46
+MX51_PAD_EIM_D24__GPIO2_8                      47
+MX51_PAD_EIM_D24__I2C2_SDA                     48
+MX51_PAD_EIM_D24__UART3_CTS                    49
+MX51_PAD_EIM_D24__USBOTG_DATA0                 50
+MX51_PAD_EIM_D25__EIM_D25                      51
+MX51_PAD_EIM_D25__KEY_COL6                     52
+MX51_PAD_EIM_D25__UART2_CTS                    53
+MX51_PAD_EIM_D25__UART3_RXD                    54
+MX51_PAD_EIM_D25__USBOTG_DATA1                 55
+MX51_PAD_EIM_D26__EIM_D26                      56
+MX51_PAD_EIM_D26__KEY_COL7                     57
+MX51_PAD_EIM_D26__UART2_RTS                    58
+MX51_PAD_EIM_D26__UART3_TXD                    59
+MX51_PAD_EIM_D26__USBOTG_DATA2                 60
+MX51_PAD_EIM_D27__AUD6_RXC                     61
+MX51_PAD_EIM_D27__EIM_D27                      62
+MX51_PAD_EIM_D27__GPIO2_9                      63
+MX51_PAD_EIM_D27__I2C2_SCL                     64
+MX51_PAD_EIM_D27__UART3_RTS                    65
+MX51_PAD_EIM_D27__USBOTG_DATA3                 66
+MX51_PAD_EIM_D28__AUD6_TXD                     67
+MX51_PAD_EIM_D28__EIM_D28                      68
+MX51_PAD_EIM_D28__KEY_ROW4                     69
+MX51_PAD_EIM_D28__USBOTG_DATA4                 70
+MX51_PAD_EIM_D29__AUD6_RXD                     71
+MX51_PAD_EIM_D29__EIM_D29                      72
+MX51_PAD_EIM_D29__KEY_ROW5                     73
+MX51_PAD_EIM_D29__USBOTG_DATA5                 74
+MX51_PAD_EIM_D30__AUD6_TXC                     75
+MX51_PAD_EIM_D30__EIM_D30                      76
+MX51_PAD_EIM_D30__KEY_ROW6                     77
+MX51_PAD_EIM_D30__USBOTG_DATA6                 78
+MX51_PAD_EIM_D31__AUD6_TXFS                    79
+MX51_PAD_EIM_D31__EIM_D31                      80
+MX51_PAD_EIM_D31__KEY_ROW7                     81
+MX51_PAD_EIM_D31__USBOTG_DATA7                 82
+MX51_PAD_EIM_A16__EIM_A16                      83
+MX51_PAD_EIM_A16__GPIO2_10                     84
+MX51_PAD_EIM_A16__OSC_FREQ_SEL0                        85
+MX51_PAD_EIM_A17__EIM_A17                      86
+MX51_PAD_EIM_A17__GPIO2_11                     87
+MX51_PAD_EIM_A17__OSC_FREQ_SEL1                        88
+MX51_PAD_EIM_A18__BOOT_LPB0                    89
+MX51_PAD_EIM_A18__EIM_A18                      90
+MX51_PAD_EIM_A18__GPIO2_12                     91
+MX51_PAD_EIM_A19__BOOT_LPB1                    92
+MX51_PAD_EIM_A19__EIM_A19                      93
+MX51_PAD_EIM_A19__GPIO2_13                     94
+MX51_PAD_EIM_A20__BOOT_UART_SRC0               95
+MX51_PAD_EIM_A20__EIM_A20                      96
+MX51_PAD_EIM_A20__GPIO2_14                     97
+MX51_PAD_EIM_A21__BOOT_UART_SRC1               98
+MX51_PAD_EIM_A21__EIM_A21                      99
+MX51_PAD_EIM_A21__GPIO2_15                     100
+MX51_PAD_EIM_A22__EIM_A22                      101
+MX51_PAD_EIM_A22__GPIO2_16                     102
+MX51_PAD_EIM_A23__BOOT_HPN_EN                  103
+MX51_PAD_EIM_A23__EIM_A23                      104
+MX51_PAD_EIM_A23__GPIO2_17                     105
+MX51_PAD_EIM_A24__EIM_A24                      106
+MX51_PAD_EIM_A24__GPIO2_18                     107
+MX51_PAD_EIM_A24__USBH2_CLK                    108
+MX51_PAD_EIM_A25__DISP1_PIN4                   109
+MX51_PAD_EIM_A25__EIM_A25                      110
+MX51_PAD_EIM_A25__GPIO2_19                     111
+MX51_PAD_EIM_A25__USBH2_DIR                    112
+MX51_PAD_EIM_A26__CSI1_DATA_EN                 113
+MX51_PAD_EIM_A26__DISP2_EXT_CLK                        114
+MX51_PAD_EIM_A26__EIM_A26                      115
+MX51_PAD_EIM_A26__GPIO2_20                     116
+MX51_PAD_EIM_A26__USBH2_STP                    117
+MX51_PAD_EIM_A27__CSI2_DATA_EN                 118
+MX51_PAD_EIM_A27__DISP1_PIN1                   119
+MX51_PAD_EIM_A27__EIM_A27                      120
+MX51_PAD_EIM_A27__GPIO2_21                     121
+MX51_PAD_EIM_A27__USBH2_NXT                    122
+MX51_PAD_EIM_EB0__EIM_EB0                      123
+MX51_PAD_EIM_EB1__EIM_EB1                      124
+MX51_PAD_EIM_EB2__AUD5_RXFS                    125
+MX51_PAD_EIM_EB2__CSI1_D2                      126
+MX51_PAD_EIM_EB2__EIM_EB2                      127
+MX51_PAD_EIM_EB2__FEC_MDIO                     128
+MX51_PAD_EIM_EB2__GPIO2_22                     129
+MX51_PAD_EIM_EB2__GPT_CMPOUT1                  130
+MX51_PAD_EIM_EB3__AUD5_RXC                     131
+MX51_PAD_EIM_EB3__CSI1_D3                      132
+MX51_PAD_EIM_EB3__EIM_EB3                      133
+MX51_PAD_EIM_EB3__FEC_RDATA1                   134
+MX51_PAD_EIM_EB3__GPIO2_23                     135
+MX51_PAD_EIM_EB3__GPT_CMPOUT2                  136
+MX51_PAD_EIM_OE__EIM_OE                                137
+MX51_PAD_EIM_OE__GPIO2_24                      138
+MX51_PAD_EIM_CS0__EIM_CS0                      139
+MX51_PAD_EIM_CS0__GPIO2_25                     140
+MX51_PAD_EIM_CS1__EIM_CS1                      141
+MX51_PAD_EIM_CS1__GPIO2_26                     142
+MX51_PAD_EIM_CS2__AUD5_TXD                     143
+MX51_PAD_EIM_CS2__CSI1_D4                      144
+MX51_PAD_EIM_CS2__EIM_CS2                      145
+MX51_PAD_EIM_CS2__FEC_RDATA2                   146
+MX51_PAD_EIM_CS2__GPIO2_27                     147
+MX51_PAD_EIM_CS2__USBOTG_STP                   148
+MX51_PAD_EIM_CS3__AUD5_RXD                     149
+MX51_PAD_EIM_CS3__CSI1_D5                      150
+MX51_PAD_EIM_CS3__EIM_CS3                      151
+MX51_PAD_EIM_CS3__FEC_RDATA3                   152
+MX51_PAD_EIM_CS3__GPIO2_28                     153
+MX51_PAD_EIM_CS3__USBOTG_NXT                   154
+MX51_PAD_EIM_CS4__AUD5_TXC                     155
+MX51_PAD_EIM_CS4__CSI1_D6                      156
+MX51_PAD_EIM_CS4__EIM_CS4                      157
+MX51_PAD_EIM_CS4__FEC_RX_ER                    158
+MX51_PAD_EIM_CS4__GPIO2_29                     159
+MX51_PAD_EIM_CS4__USBOTG_CLK                   160
+MX51_PAD_EIM_CS5__AUD5_TXFS                    161
+MX51_PAD_EIM_CS5__CSI1_D7                      162
+MX51_PAD_EIM_CS5__DISP1_EXT_CLK                        163
+MX51_PAD_EIM_CS5__EIM_CS5                      164
+MX51_PAD_EIM_CS5__FEC_CRS                      165
+MX51_PAD_EIM_CS5__GPIO2_30                     166
+MX51_PAD_EIM_CS5__USBOTG_DIR                   167
+MX51_PAD_EIM_DTACK__EIM_DTACK                  168
+MX51_PAD_EIM_DTACK__GPIO2_31                   169
+MX51_PAD_EIM_LBA__EIM_LBA                      170
+MX51_PAD_EIM_LBA__GPIO3_1                      171
+MX51_PAD_EIM_CRE__EIM_CRE                      172
+MX51_PAD_EIM_CRE__GPIO3_2                      173
+MX51_PAD_DRAM_CS1__DRAM_CS1                    174
+MX51_PAD_NANDF_WE_B__GPIO3_3                   175
+MX51_PAD_NANDF_WE_B__NANDF_WE_B                        176
+MX51_PAD_NANDF_WE_B__PATA_DIOW                 177
+MX51_PAD_NANDF_WE_B__SD3_DATA0                 178
+MX51_PAD_NANDF_RE_B__GPIO3_4                   179
+MX51_PAD_NANDF_RE_B__NANDF_RE_B                        180
+MX51_PAD_NANDF_RE_B__PATA_DIOR                 181
+MX51_PAD_NANDF_RE_B__SD3_DATA1                 182
+MX51_PAD_NANDF_ALE__GPIO3_5                    183
+MX51_PAD_NANDF_ALE__NANDF_ALE                  184
+MX51_PAD_NANDF_ALE__PATA_BUFFER_EN             185
+MX51_PAD_NANDF_CLE__GPIO3_6                    186
+MX51_PAD_NANDF_CLE__NANDF_CLE                  187
+MX51_PAD_NANDF_CLE__PATA_RESET_B               188
+MX51_PAD_NANDF_WP_B__GPIO3_7                   189
+MX51_PAD_NANDF_WP_B__NANDF_WP_B                        190
+MX51_PAD_NANDF_WP_B__PATA_DMACK                        191
+MX51_PAD_NANDF_WP_B__SD3_DATA2                 192
+MX51_PAD_NANDF_RB0__ECSPI2_SS1                 193
+MX51_PAD_NANDF_RB0__GPIO3_8                    194
+MX51_PAD_NANDF_RB0__NANDF_RB0                  195
+MX51_PAD_NANDF_RB0__PATA_DMARQ                 196
+MX51_PAD_NANDF_RB0__SD3_DATA3                  197
+MX51_PAD_NANDF_RB1__CSPI_MOSI                  198
+MX51_PAD_NANDF_RB1__ECSPI2_RDY                 199
+MX51_PAD_NANDF_RB1__GPIO3_9                    200
+MX51_PAD_NANDF_RB1__NANDF_RB1                  201
+MX51_PAD_NANDF_RB1__PATA_IORDY                 202
+MX51_PAD_NANDF_RB1__SD4_CMD                    203
+MX51_PAD_NANDF_RB2__DISP2_WAIT                 204
+MX51_PAD_NANDF_RB2__ECSPI2_SCLK                        205
+MX51_PAD_NANDF_RB2__FEC_COL                    206
+MX51_PAD_NANDF_RB2__GPIO3_10                   207
+MX51_PAD_NANDF_RB2__NANDF_RB2                  208
+MX51_PAD_NANDF_RB2__USBH3_H3_DP                        209
+MX51_PAD_NANDF_RB2__USBH3_NXT                  210
+MX51_PAD_NANDF_RB3__DISP1_WAIT                 211
+MX51_PAD_NANDF_RB3__ECSPI2_MISO                        212
+MX51_PAD_NANDF_RB3__FEC_RX_CLK                 213
+MX51_PAD_NANDF_RB3__GPIO3_11                   214
+MX51_PAD_NANDF_RB3__NANDF_RB3                  215
+MX51_PAD_NANDF_RB3__USBH3_CLK                  216
+MX51_PAD_NANDF_RB3__USBH3_H3_DM                        217
+MX51_PAD_GPIO_NAND__GPIO_NAND                  218
+MX51_PAD_GPIO_NAND__PATA_INTRQ                 219
+MX51_PAD_NANDF_CS0__GPIO3_16                   220
+MX51_PAD_NANDF_CS0__NANDF_CS0                  221
+MX51_PAD_NANDF_CS1__GPIO3_17                   222
+MX51_PAD_NANDF_CS1__NANDF_CS1                  223
+MX51_PAD_NANDF_CS2__CSPI_SCLK                  224
+MX51_PAD_NANDF_CS2__FEC_TX_ER                  225
+MX51_PAD_NANDF_CS2__GPIO3_18                   226
+MX51_PAD_NANDF_CS2__NANDF_CS2                  227
+MX51_PAD_NANDF_CS2__PATA_CS_0                  228
+MX51_PAD_NANDF_CS2__SD4_CLK                    229
+MX51_PAD_NANDF_CS2__USBH3_H1_DP                        230
+MX51_PAD_NANDF_CS3__FEC_MDC                    231
+MX51_PAD_NANDF_CS3__GPIO3_19                   232
+MX51_PAD_NANDF_CS3__NANDF_CS3                  233
+MX51_PAD_NANDF_CS3__PATA_CS_1                  234
+MX51_PAD_NANDF_CS3__SD4_DAT0                   235
+MX51_PAD_NANDF_CS3__USBH3_H1_DM                        236
+MX51_PAD_NANDF_CS4__FEC_TDATA1                 237
+MX51_PAD_NANDF_CS4__GPIO3_20                   238
+MX51_PAD_NANDF_CS4__NANDF_CS4                  239
+MX51_PAD_NANDF_CS4__PATA_DA_0                  240
+MX51_PAD_NANDF_CS4__SD4_DAT1                   241
+MX51_PAD_NANDF_CS4__USBH3_STP                  242
+MX51_PAD_NANDF_CS5__FEC_TDATA2                 243
+MX51_PAD_NANDF_CS5__GPIO3_21                   244
+MX51_PAD_NANDF_CS5__NANDF_CS5                  245
+MX51_PAD_NANDF_CS5__PATA_DA_1                  246
+MX51_PAD_NANDF_CS5__SD4_DAT2                   247
+MX51_PAD_NANDF_CS5__USBH3_DIR                  248
+MX51_PAD_NANDF_CS6__CSPI_SS3                   249
+MX51_PAD_NANDF_CS6__FEC_TDATA3                 250
+MX51_PAD_NANDF_CS6__GPIO3_22                   251
+MX51_PAD_NANDF_CS6__NANDF_CS6                  252
+MX51_PAD_NANDF_CS6__PATA_DA_2                  253
+MX51_PAD_NANDF_CS6__SD4_DAT3                   254
+MX51_PAD_NANDF_CS7__FEC_TX_EN                  255
+MX51_PAD_NANDF_CS7__GPIO3_23                   256
+MX51_PAD_NANDF_CS7__NANDF_CS7                  257
+MX51_PAD_NANDF_CS7__SD3_CLK                    258
+MX51_PAD_NANDF_RDY_INT__ECSPI2_SS0             259
+MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK             260
+MX51_PAD_NANDF_RDY_INT__GPIO3_24               261
+MX51_PAD_NANDF_RDY_INT__NANDF_RDY_INT          262
+MX51_PAD_NANDF_RDY_INT__SD3_CMD                        263
+MX51_PAD_NANDF_D15__ECSPI2_MOSI                        264
+MX51_PAD_NANDF_D15__GPIO3_25                   265
+MX51_PAD_NANDF_D15__NANDF_D15                  266
+MX51_PAD_NANDF_D15__PATA_DATA15                        267
+MX51_PAD_NANDF_D15__SD3_DAT7                   268
+MX51_PAD_NANDF_D14__ECSPI2_SS3                 269
+MX51_PAD_NANDF_D14__GPIO3_26                   270
+MX51_PAD_NANDF_D14__NANDF_D14                  271
+MX51_PAD_NANDF_D14__PATA_DATA14                        272
+MX51_PAD_NANDF_D14__SD3_DAT6                   273
+MX51_PAD_NANDF_D13__ECSPI2_SS2                 274
+MX51_PAD_NANDF_D13__GPIO3_27                   275
+MX51_PAD_NANDF_D13__NANDF_D13                  276
+MX51_PAD_NANDF_D13__PATA_DATA13                        277
+MX51_PAD_NANDF_D13__SD3_DAT5                   278
+MX51_PAD_NANDF_D12__ECSPI2_SS1                 279
+MX51_PAD_NANDF_D12__GPIO3_28                   280
+MX51_PAD_NANDF_D12__NANDF_D12                  281
+MX51_PAD_NANDF_D12__PATA_DATA12                        282
+MX51_PAD_NANDF_D12__SD3_DAT4                   283
+MX51_PAD_NANDF_D11__FEC_RX_DV                  284
+MX51_PAD_NANDF_D11__GPIO3_29                   285
+MX51_PAD_NANDF_D11__NANDF_D11                  286
+MX51_PAD_NANDF_D11__PATA_DATA11                        287
+MX51_PAD_NANDF_D11__SD3_DATA3                  288
+MX51_PAD_NANDF_D10__GPIO3_30                   289
+MX51_PAD_NANDF_D10__NANDF_D10                  290
+MX51_PAD_NANDF_D10__PATA_DATA10                        291
+MX51_PAD_NANDF_D10__SD3_DATA2                  292
+MX51_PAD_NANDF_D9__FEC_RDATA0                  293
+MX51_PAD_NANDF_D9__GPIO3_31                    294
+MX51_PAD_NANDF_D9__NANDF_D9                    295
+MX51_PAD_NANDF_D9__PATA_DATA9                  296
+MX51_PAD_NANDF_D9__SD3_DATA1                   297
+MX51_PAD_NANDF_D8__FEC_TDATA0                  298
+MX51_PAD_NANDF_D8__GPIO4_0                     299
+MX51_PAD_NANDF_D8__NANDF_D8                    300
+MX51_PAD_NANDF_D8__PATA_DATA8                  301
+MX51_PAD_NANDF_D8__SD3_DATA0                   302
+MX51_PAD_NANDF_D7__GPIO4_1                     303
+MX51_PAD_NANDF_D7__NANDF_D7                    304
+MX51_PAD_NANDF_D7__PATA_DATA7                  305
+MX51_PAD_NANDF_D7__USBH3_DATA0                 306
+MX51_PAD_NANDF_D6__GPIO4_2                     307
+MX51_PAD_NANDF_D6__NANDF_D6                    308
+MX51_PAD_NANDF_D6__PATA_DATA6                  309
+MX51_PAD_NANDF_D6__SD4_LCTL                    310
+MX51_PAD_NANDF_D6__USBH3_DATA1                 311
+MX51_PAD_NANDF_D5__GPIO4_3                     312
+MX51_PAD_NANDF_D5__NANDF_D5                    313
+MX51_PAD_NANDF_D5__PATA_DATA5                  314
+MX51_PAD_NANDF_D5__SD4_WP                      315
+MX51_PAD_NANDF_D5__USBH3_DATA2                 316
+MX51_PAD_NANDF_D4__GPIO4_4                     317
+MX51_PAD_NANDF_D4__NANDF_D4                    318
+MX51_PAD_NANDF_D4__PATA_DATA4                  319
+MX51_PAD_NANDF_D4__SD4_CD                      320
+MX51_PAD_NANDF_D4__USBH3_DATA3                 321
+MX51_PAD_NANDF_D3__GPIO4_5                     322
+MX51_PAD_NANDF_D3__NANDF_D3                    323
+MX51_PAD_NANDF_D3__PATA_DATA3                  324
+MX51_PAD_NANDF_D3__SD4_DAT4                    325
+MX51_PAD_NANDF_D3__USBH3_DATA4                 326
+MX51_PAD_NANDF_D2__GPIO4_6                     327
+MX51_PAD_NANDF_D2__NANDF_D2                    328
+MX51_PAD_NANDF_D2__PATA_DATA2                  329
+MX51_PAD_NANDF_D2__SD4_DAT5                    330
+MX51_PAD_NANDF_D2__USBH3_DATA5                 331
+MX51_PAD_NANDF_D1__GPIO4_7                     332
+MX51_PAD_NANDF_D1__NANDF_D1                    333
+MX51_PAD_NANDF_D1__PATA_DATA1                  334
+MX51_PAD_NANDF_D1__SD4_DAT6                    335
+MX51_PAD_NANDF_D1__USBH3_DATA6                 336
+MX51_PAD_NANDF_D0__GPIO4_8                     337
+MX51_PAD_NANDF_D0__NANDF_D0                    338
+MX51_PAD_NANDF_D0__PATA_DATA0                  339
+MX51_PAD_NANDF_D0__SD4_DAT7                    340
+MX51_PAD_NANDF_D0__USBH3_DATA7                 341
+MX51_PAD_CSI1_D8__CSI1_D8                      342
+MX51_PAD_CSI1_D8__GPIO3_12                     343
+MX51_PAD_CSI1_D9__CSI1_D9                      344
+MX51_PAD_CSI1_D9__GPIO3_13                     345
+MX51_PAD_CSI1_D10__CSI1_D10                    346
+MX51_PAD_CSI1_D11__CSI1_D11                    347
+MX51_PAD_CSI1_D12__CSI1_D12                    348
+MX51_PAD_CSI1_D13__CSI1_D13                    349
+MX51_PAD_CSI1_D14__CSI1_D14                    350
+MX51_PAD_CSI1_D15__CSI1_D15                    351
+MX51_PAD_CSI1_D16__CSI1_D16                    352
+MX51_PAD_CSI1_D17__CSI1_D17                    353
+MX51_PAD_CSI1_D18__CSI1_D18                    354
+MX51_PAD_CSI1_D19__CSI1_D19                    355
+MX51_PAD_CSI1_VSYNC__CSI1_VSYNC                        356
+MX51_PAD_CSI1_VSYNC__GPIO3_14                  357
+MX51_PAD_CSI1_HSYNC__CSI1_HSYNC                        358
+MX51_PAD_CSI1_HSYNC__GPIO3_15                  359
+MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK              360
+MX51_PAD_CSI1_MCLK__CSI1_MCLK                  361
+MX51_PAD_CSI2_D12__CSI2_D12                    362
+MX51_PAD_CSI2_D12__GPIO4_9                     363
+MX51_PAD_CSI2_D13__CSI2_D13                    364
+MX51_PAD_CSI2_D13__GPIO4_10                    365
+MX51_PAD_CSI2_D14__CSI2_D14                    366
+MX51_PAD_CSI2_D15__CSI2_D15                    367
+MX51_PAD_CSI2_D16__CSI2_D16                    368
+MX51_PAD_CSI2_D17__CSI2_D17                    369
+MX51_PAD_CSI2_D18__CSI2_D18                    370
+MX51_PAD_CSI2_D18__GPIO4_11                    371
+MX51_PAD_CSI2_D19__CSI2_D19                    372
+MX51_PAD_CSI2_D19__GPIO4_12                    373
+MX51_PAD_CSI2_VSYNC__CSI2_VSYNC                        374
+MX51_PAD_CSI2_VSYNC__GPIO4_13                  375
+MX51_PAD_CSI2_HSYNC__CSI2_HSYNC                        376
+MX51_PAD_CSI2_HSYNC__GPIO4_14                  377
+MX51_PAD_CSI2_PIXCLK__CSI2_PIXCLK              378
+MX51_PAD_CSI2_PIXCLK__GPIO4_15                 379
+MX51_PAD_I2C1_CLK__GPIO4_16                    380
+MX51_PAD_I2C1_CLK__I2C1_CLK                    381
+MX51_PAD_I2C1_DAT__GPIO4_17                    382
+MX51_PAD_I2C1_DAT__I2C1_DAT                    383
+MX51_PAD_AUD3_BB_TXD__AUD3_TXD                 384
+MX51_PAD_AUD3_BB_TXD__GPIO4_18                 385
+MX51_PAD_AUD3_BB_RXD__AUD3_RXD                 386
+MX51_PAD_AUD3_BB_RXD__GPIO4_19                 387
+MX51_PAD_AUD3_BB_RXD__UART3_RXD                        388
+MX51_PAD_AUD3_BB_CK__AUD3_TXC                  389
+MX51_PAD_AUD3_BB_CK__GPIO4_20                  390
+MX51_PAD_AUD3_BB_FS__AUD3_TXFS                 391
+MX51_PAD_AUD3_BB_FS__GPIO4_21                  392
+MX51_PAD_AUD3_BB_FS__UART3_TXD                 393
+MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI               394
+MX51_PAD_CSPI1_MOSI__GPIO4_22                  395
+MX51_PAD_CSPI1_MOSI__I2C1_SDA                  396
+MX51_PAD_CSPI1_MISO__AUD4_RXD                  397
+MX51_PAD_CSPI1_MISO__ECSPI1_MISO               398
+MX51_PAD_CSPI1_MISO__GPIO4_23                  399
+MX51_PAD_CSPI1_SS0__AUD4_TXC                   400
+MX51_PAD_CSPI1_SS0__ECSPI1_SS0                 401
+MX51_PAD_CSPI1_SS0__GPIO4_24                   402
+MX51_PAD_CSPI1_SS1__AUD4_TXD                   403
+MX51_PAD_CSPI1_SS1__ECSPI1_SS1                 404
+MX51_PAD_CSPI1_SS1__GPIO4_25                   405
+MX51_PAD_CSPI1_RDY__AUD4_TXFS                  406
+MX51_PAD_CSPI1_RDY__ECSPI1_RDY                 407
+MX51_PAD_CSPI1_RDY__GPIO4_26                   408
+MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK               409
+MX51_PAD_CSPI1_SCLK__GPIO4_27                  410
+MX51_PAD_CSPI1_SCLK__I2C1_SCL                  411
+MX51_PAD_UART1_RXD__GPIO4_28                   412
+MX51_PAD_UART1_RXD__UART1_RXD                  413
+MX51_PAD_UART1_TXD__GPIO4_29                   414
+MX51_PAD_UART1_TXD__PWM2_PWMO                  415
+MX51_PAD_UART1_TXD__UART1_TXD                  416
+MX51_PAD_UART1_RTS__GPIO4_30                   417
+MX51_PAD_UART1_RTS__UART1_RTS                  418
+MX51_PAD_UART1_CTS__GPIO4_31                   419
+MX51_PAD_UART1_CTS__UART1_CTS                  420
+MX51_PAD_UART2_RXD__FIRI_TXD                   421
+MX51_PAD_UART2_RXD__GPIO1_20                   422
+MX51_PAD_UART2_RXD__UART2_RXD                  423
+MX51_PAD_UART2_TXD__FIRI_RXD                   424
+MX51_PAD_UART2_TXD__GPIO1_21                   425
+MX51_PAD_UART2_TXD__UART2_TXD                  426
+MX51_PAD_UART3_RXD__CSI1_D0                    427
+MX51_PAD_UART3_RXD__GPIO1_22                   428
+MX51_PAD_UART3_RXD__UART1_DTR                  429
+MX51_PAD_UART3_RXD__UART3_RXD                  430
+MX51_PAD_UART3_TXD__CSI1_D1                    431
+MX51_PAD_UART3_TXD__GPIO1_23                   432
+MX51_PAD_UART3_TXD__UART1_DSR                  433
+MX51_PAD_UART3_TXD__UART3_TXD                  434
+MX51_PAD_OWIRE_LINE__GPIO1_24                  435
+MX51_PAD_OWIRE_LINE__OWIRE_LINE                        436
+MX51_PAD_OWIRE_LINE__SPDIF_OUT                 437
+MX51_PAD_KEY_ROW0__KEY_ROW0                    438
+MX51_PAD_KEY_ROW1__KEY_ROW1                    439
+MX51_PAD_KEY_ROW2__KEY_ROW2                    440
+MX51_PAD_KEY_ROW3__KEY_ROW3                    441
+MX51_PAD_KEY_COL0__KEY_COL0                    442
+MX51_PAD_KEY_COL0__PLL1_BYP                    443
+MX51_PAD_KEY_COL1__KEY_COL1                    444
+MX51_PAD_KEY_COL1__PLL2_BYP                    445
+MX51_PAD_KEY_COL2__KEY_COL2                    446
+MX51_PAD_KEY_COL2__PLL3_BYP                    447
+MX51_PAD_KEY_COL3__KEY_COL3                    448
+MX51_PAD_KEY_COL4__I2C2_SCL                    449
+MX51_PAD_KEY_COL4__KEY_COL4                    450
+MX51_PAD_KEY_COL4__SPDIF_OUT1                  451
+MX51_PAD_KEY_COL4__UART1_RI                    452
+MX51_PAD_KEY_COL4__UART3_RTS                   453
+MX51_PAD_KEY_COL5__I2C2_SDA                    454
+MX51_PAD_KEY_COL5__KEY_COL5                    455
+MX51_PAD_KEY_COL5__UART1_DCD                   456
+MX51_PAD_KEY_COL5__UART3_CTS                   457
+MX51_PAD_USBH1_CLK__CSPI_SCLK                  458
+MX51_PAD_USBH1_CLK__GPIO1_25                   459
+MX51_PAD_USBH1_CLK__I2C2_SCL                   460
+MX51_PAD_USBH1_CLK__USBH1_CLK                  461
+MX51_PAD_USBH1_DIR__CSPI_MOSI                  462
+MX51_PAD_USBH1_DIR__GPIO1_26                   463
+MX51_PAD_USBH1_DIR__I2C2_SDA                   464
+MX51_PAD_USBH1_DIR__USBH1_DIR                  465
+MX51_PAD_USBH1_STP__CSPI_RDY                   466
+MX51_PAD_USBH1_STP__GPIO1_27                   467
+MX51_PAD_USBH1_STP__UART3_RXD                  468
+MX51_PAD_USBH1_STP__USBH1_STP                  469
+MX51_PAD_USBH1_NXT__CSPI_MISO                  470
+MX51_PAD_USBH1_NXT__GPIO1_28                   471
+MX51_PAD_USBH1_NXT__UART3_TXD                  472
+MX51_PAD_USBH1_NXT__USBH1_NXT                  473
+MX51_PAD_USBH1_DATA0__GPIO1_11                 474
+MX51_PAD_USBH1_DATA0__UART2_CTS                        475
+MX51_PAD_USBH1_DATA0__USBH1_DATA0              476
+MX51_PAD_USBH1_DATA1__GPIO1_12                 477
+MX51_PAD_USBH1_DATA1__UART2_RXD                        478
+MX51_PAD_USBH1_DATA1__USBH1_DATA1              479
+MX51_PAD_USBH1_DATA2__GPIO1_13                 480
+MX51_PAD_USBH1_DATA2__UART2_TXD                        481
+MX51_PAD_USBH1_DATA2__USBH1_DATA2              482
+MX51_PAD_USBH1_DATA3__GPIO1_14                 483
+MX51_PAD_USBH1_DATA3__UART2_RTS                        484
+MX51_PAD_USBH1_DATA3__USBH1_DATA3              485
+MX51_PAD_USBH1_DATA4__CSPI_SS0                 486
+MX51_PAD_USBH1_DATA4__GPIO1_15                 487
+MX51_PAD_USBH1_DATA4__USBH1_DATA4              488
+MX51_PAD_USBH1_DATA5__CSPI_SS1                 489
+MX51_PAD_USBH1_DATA5__GPIO1_16                 490
+MX51_PAD_USBH1_DATA5__USBH1_DATA5              491
+MX51_PAD_USBH1_DATA6__CSPI_SS3                 492
+MX51_PAD_USBH1_DATA6__GPIO1_17                 493
+MX51_PAD_USBH1_DATA6__USBH1_DATA6              494
+MX51_PAD_USBH1_DATA7__ECSPI1_SS3               495
+MX51_PAD_USBH1_DATA7__ECSPI2_SS3               496
+MX51_PAD_USBH1_DATA7__GPIO1_18                 497
+MX51_PAD_USBH1_DATA7__USBH1_DATA7              498
+MX51_PAD_DI1_PIN11__DI1_PIN11                  499
+MX51_PAD_DI1_PIN11__ECSPI1_SS2                 500
+MX51_PAD_DI1_PIN11__GPIO3_0                    501
+MX51_PAD_DI1_PIN12__DI1_PIN12                  502
+MX51_PAD_DI1_PIN12__GPIO3_1                    503
+MX51_PAD_DI1_PIN13__DI1_PIN13                  504
+MX51_PAD_DI1_PIN13__GPIO3_2                    505
+MX51_PAD_DI1_D0_CS__DI1_D0_CS                  506
+MX51_PAD_DI1_D0_CS__GPIO3_3                    507
+MX51_PAD_DI1_D1_CS__DI1_D1_CS                  508
+MX51_PAD_DI1_D1_CS__DISP1_PIN14                        509
+MX51_PAD_DI1_D1_CS__DISP1_PIN5                 510
+MX51_PAD_DI1_D1_CS__GPIO3_4                    511
+MX51_PAD_DISPB2_SER_DIN__DISP1_PIN1            512
+MX51_PAD_DISPB2_SER_DIN__DISPB2_SER_DIN                513
+MX51_PAD_DISPB2_SER_DIN__GPIO3_5               514
+MX51_PAD_DISPB2_SER_DIO__DISP1_PIN6            515
+MX51_PAD_DISPB2_SER_DIO__DISPB2_SER_DIO                516
+MX51_PAD_DISPB2_SER_DIO__GPIO3_6               517
+MX51_PAD_DISPB2_SER_CLK__DISP1_PIN17           518
+MX51_PAD_DISPB2_SER_CLK__DISP1_PIN7            519
+MX51_PAD_DISPB2_SER_CLK__DISPB2_SER_CLK                520
+MX51_PAD_DISPB2_SER_CLK__GPIO3_7               521
+MX51_PAD_DISPB2_SER_RS__DISP1_EXT_CLK          522
+MX51_PAD_DISPB2_SER_RS__DISP1_PIN16            523
+MX51_PAD_DISPB2_SER_RS__DISP1_PIN8             524
+MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS          525
+MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS          526
+MX51_PAD_DISPB2_SER_RS__GPIO3_8                        527
+MX51_PAD_DISP1_DAT0__DISP1_DAT0                        528
+MX51_PAD_DISP1_DAT1__DISP1_DAT1                        529
+MX51_PAD_DISP1_DAT2__DISP1_DAT2                        530
+MX51_PAD_DISP1_DAT3__DISP1_DAT3                        531
+MX51_PAD_DISP1_DAT4__DISP1_DAT4                        532
+MX51_PAD_DISP1_DAT5__DISP1_DAT5                        533
+MX51_PAD_DISP1_DAT6__BOOT_USB_SRC              534
+MX51_PAD_DISP1_DAT6__DISP1_DAT6                        535
+MX51_PAD_DISP1_DAT7__BOOT_EEPROM_CFG           536
+MX51_PAD_DISP1_DAT7__DISP1_DAT7                        537
+MX51_PAD_DISP1_DAT8__BOOT_SRC0                 538
+MX51_PAD_DISP1_DAT8__DISP1_DAT8                        539
+MX51_PAD_DISP1_DAT9__BOOT_SRC1                 540
+MX51_PAD_DISP1_DAT9__DISP1_DAT9                        541
+MX51_PAD_DISP1_DAT10__BOOT_SPARE_SIZE          542
+MX51_PAD_DISP1_DAT10__DISP1_DAT10              543
+MX51_PAD_DISP1_DAT11__BOOT_LPB_FREQ2           544
+MX51_PAD_DISP1_DAT11__DISP1_DAT11              545
+MX51_PAD_DISP1_DAT12__BOOT_MLC_SEL             546
+MX51_PAD_DISP1_DAT12__DISP1_DAT12              547
+MX51_PAD_DISP1_DAT13__BOOT_MEM_CTL0            548
+MX51_PAD_DISP1_DAT13__DISP1_DAT13              549
+MX51_PAD_DISP1_DAT14__BOOT_MEM_CTL1            550
+MX51_PAD_DISP1_DAT14__DISP1_DAT14              551
+MX51_PAD_DISP1_DAT15__BOOT_BUS_WIDTH           552
+MX51_PAD_DISP1_DAT15__DISP1_DAT15              553
+MX51_PAD_DISP1_DAT16__BOOT_PAGE_SIZE0          554
+MX51_PAD_DISP1_DAT16__DISP1_DAT16              555
+MX51_PAD_DISP1_DAT17__BOOT_PAGE_SIZE1          556
+MX51_PAD_DISP1_DAT17__DISP1_DAT17              557
+MX51_PAD_DISP1_DAT18__BOOT_WEIM_MUXED0         558
+MX51_PAD_DISP1_DAT18__DISP1_DAT18              559
+MX51_PAD_DISP1_DAT18__DISP2_PIN11              560
+MX51_PAD_DISP1_DAT18__DISP2_PIN5               561
+MX51_PAD_DISP1_DAT19__BOOT_WEIM_MUXED1         562
+MX51_PAD_DISP1_DAT19__DISP1_DAT19              563
+MX51_PAD_DISP1_DAT19__DISP2_PIN12              564
+MX51_PAD_DISP1_DAT19__DISP2_PIN6               565
+MX51_PAD_DISP1_DAT20__BOOT_MEM_TYPE0           566
+MX51_PAD_DISP1_DAT20__DISP1_DAT20              567
+MX51_PAD_DISP1_DAT20__DISP2_PIN13              568
+MX51_PAD_DISP1_DAT20__DISP2_PIN7               569
+MX51_PAD_DISP1_DAT21__BOOT_MEM_TYPE1           570
+MX51_PAD_DISP1_DAT21__DISP1_DAT21              571
+MX51_PAD_DISP1_DAT21__DISP2_PIN14              572
+MX51_PAD_DISP1_DAT21__DISP2_PIN8               573
+MX51_PAD_DISP1_DAT22__BOOT_LPB_FREQ0           574
+MX51_PAD_DISP1_DAT22__DISP1_DAT22              575
+MX51_PAD_DISP1_DAT22__DISP2_D0_CS              576
+MX51_PAD_DISP1_DAT22__DISP2_DAT16              577
+MX51_PAD_DISP1_DAT23__BOOT_LPB_FREQ1           578
+MX51_PAD_DISP1_DAT23__DISP1_DAT23              579
+MX51_PAD_DISP1_DAT23__DISP2_D1_CS              580
+MX51_PAD_DISP1_DAT23__DISP2_DAT17              581
+MX51_PAD_DISP1_DAT23__DISP2_SER_CS             582
+MX51_PAD_DI1_PIN3__DI1_PIN3                    583
+MX51_PAD_DI1_PIN2__DI1_PIN2                    584
+MX51_PAD_DI_GP2__DISP1_SER_CLK                 585
+MX51_PAD_DI_GP2__DISP2_WAIT                    586
+MX51_PAD_DI_GP3__CSI1_DATA_EN                  587
+MX51_PAD_DI_GP3__DISP1_SER_DIO                 588
+MX51_PAD_DI_GP3__FEC_TX_ER                     589
+MX51_PAD_DI2_PIN4__CSI2_DATA_EN                        590
+MX51_PAD_DI2_PIN4__DI2_PIN4                    591
+MX51_PAD_DI2_PIN4__FEC_CRS                     592
+MX51_PAD_DI2_PIN2__DI2_PIN2                    593
+MX51_PAD_DI2_PIN2__FEC_MDC                     594
+MX51_PAD_DI2_PIN3__DI2_PIN3                    595
+MX51_PAD_DI2_PIN3__FEC_MDIO                    596
+MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK            597
+MX51_PAD_DI2_DISP_CLK__FEC_RDATA1              598
+MX51_PAD_DI_GP4__DI2_PIN15                     599
+MX51_PAD_DI_GP4__DISP1_SER_DIN                 600
+MX51_PAD_DI_GP4__DISP2_PIN1                    601
+MX51_PAD_DI_GP4__FEC_RDATA2                    602
+MX51_PAD_DISP2_DAT0__DISP2_DAT0                        603
+MX51_PAD_DISP2_DAT0__FEC_RDATA3                        604
+MX51_PAD_DISP2_DAT0__KEY_COL6                  605
+MX51_PAD_DISP2_DAT0__UART3_RXD                 606
+MX51_PAD_DISP2_DAT0__USBH3_CLK                 607
+MX51_PAD_DISP2_DAT1__DISP2_DAT1                        608
+MX51_PAD_DISP2_DAT1__FEC_RX_ER                 609
+MX51_PAD_DISP2_DAT1__KEY_COL7                  610
+MX51_PAD_DISP2_DAT1__UART3_TXD                 611
+MX51_PAD_DISP2_DAT1__USBH3_DIR                 612
+MX51_PAD_DISP2_DAT2__DISP2_DAT2                        613
+MX51_PAD_DISP2_DAT3__DISP2_DAT3                        614
+MX51_PAD_DISP2_DAT4__DISP2_DAT4                        615
+MX51_PAD_DISP2_DAT5__DISP2_DAT5                        616
+MX51_PAD_DISP2_DAT6__DISP2_DAT6                        617
+MX51_PAD_DISP2_DAT6__FEC_TDATA1                        618
+MX51_PAD_DISP2_DAT6__GPIO1_19                  619
+MX51_PAD_DISP2_DAT6__KEY_ROW4                  620
+MX51_PAD_DISP2_DAT6__USBH3_STP                 621
+MX51_PAD_DISP2_DAT7__DISP2_DAT7                        622
+MX51_PAD_DISP2_DAT7__FEC_TDATA2                        623
+MX51_PAD_DISP2_DAT7__GPIO1_29                  624
+MX51_PAD_DISP2_DAT7__KEY_ROW5                  625
+MX51_PAD_DISP2_DAT7__USBH3_NXT                 626
+MX51_PAD_DISP2_DAT8__DISP2_DAT8                        627
+MX51_PAD_DISP2_DAT8__FEC_TDATA3                        628
+MX51_PAD_DISP2_DAT8__GPIO1_30                  629
+MX51_PAD_DISP2_DAT8__KEY_ROW6                  630
+MX51_PAD_DISP2_DAT8__USBH3_DATA0               631
+MX51_PAD_DISP2_DAT9__AUD6_RXC                  632
+MX51_PAD_DISP2_DAT9__DISP2_DAT9                        633
+MX51_PAD_DISP2_DAT9__FEC_TX_EN                 634
+MX51_PAD_DISP2_DAT9__GPIO1_31                  635
+MX51_PAD_DISP2_DAT9__USBH3_DATA1               636
+MX51_PAD_DISP2_DAT10__DISP2_DAT10              637
+MX51_PAD_DISP2_DAT10__DISP2_SER_CS             638
+MX51_PAD_DISP2_DAT10__FEC_COL                  639
+MX51_PAD_DISP2_DAT10__KEY_ROW7                 640
+MX51_PAD_DISP2_DAT10__USBH3_DATA2              641
+MX51_PAD_DISP2_DAT11__AUD6_TXD                 642
+MX51_PAD_DISP2_DAT11__DISP2_DAT11              643
+MX51_PAD_DISP2_DAT11__FEC_RX_CLK               644
+MX51_PAD_DISP2_DAT11__GPIO1_10                 645
+MX51_PAD_DISP2_DAT11__USBH3_DATA3              646
+MX51_PAD_DISP2_DAT12__AUD6_RXD                 647
+MX51_PAD_DISP2_DAT12__DISP2_DAT12              648
+MX51_PAD_DISP2_DAT12__FEC_RX_DV                        649
+MX51_PAD_DISP2_DAT12__USBH3_DATA4              650
+MX51_PAD_DISP2_DAT13__AUD6_TXC                 651
+MX51_PAD_DISP2_DAT13__DISP2_DAT13              652
+MX51_PAD_DISP2_DAT13__FEC_TX_CLK               653
+MX51_PAD_DISP2_DAT13__USBH3_DATA5              654
+MX51_PAD_DISP2_DAT14__AUD6_TXFS                        655
+MX51_PAD_DISP2_DAT14__DISP2_DAT14              656
+MX51_PAD_DISP2_DAT14__FEC_RDATA0               657
+MX51_PAD_DISP2_DAT14__USBH3_DATA6              658
+MX51_PAD_DISP2_DAT15__AUD6_RXFS                        659
+MX51_PAD_DISP2_DAT15__DISP1_SER_CS             660
+MX51_PAD_DISP2_DAT15__DISP2_DAT15              661
+MX51_PAD_DISP2_DAT15__FEC_TDATA0               662
+MX51_PAD_DISP2_DAT15__USBH3_DATA7              663
+MX51_PAD_SD1_CMD__AUD5_RXFS                    664
+MX51_PAD_SD1_CMD__CSPI_MOSI                    665
+MX51_PAD_SD1_CMD__SD1_CMD                      666
+MX51_PAD_SD1_CLK__AUD5_RXC                     667
+MX51_PAD_SD1_CLK__CSPI_SCLK                    668
+MX51_PAD_SD1_CLK__SD1_CLK                      669
+MX51_PAD_SD1_DATA0__AUD5_TXD                   670
+MX51_PAD_SD1_DATA0__CSPI_MISO                  671
+MX51_PAD_SD1_DATA0__SD1_DATA0                  672
+MX51_PAD_EIM_DA0__EIM_DA0                      673
+MX51_PAD_EIM_DA1__EIM_DA1                      674
+MX51_PAD_EIM_DA2__EIM_DA2                      675
+MX51_PAD_EIM_DA3__EIM_DA3                      676
+MX51_PAD_SD1_DATA1__AUD5_RXD                   677
+MX51_PAD_SD1_DATA1__SD1_DATA1                  678
+MX51_PAD_EIM_DA4__EIM_DA4                      679
+MX51_PAD_EIM_DA5__EIM_DA5                      680
+MX51_PAD_EIM_DA6__EIM_DA6                      681
+MX51_PAD_EIM_DA7__EIM_DA7                      682
+MX51_PAD_SD1_DATA2__AUD5_TXC                   683
+MX51_PAD_SD1_DATA2__SD1_DATA2                  684
+MX51_PAD_EIM_DA10__EIM_DA10                    685
+MX51_PAD_EIM_DA11__EIM_DA11                    686
+MX51_PAD_EIM_DA8__EIM_DA8                      687
+MX51_PAD_EIM_DA9__EIM_DA9                      688
+MX51_PAD_SD1_DATA3__AUD5_TXFS                  689
+MX51_PAD_SD1_DATA3__CSPI_SS1                   690
+MX51_PAD_SD1_DATA3__SD1_DATA3                  691
+MX51_PAD_GPIO1_0__CSPI_SS2                     692
+MX51_PAD_GPIO1_0__GPIO1_0                      693
+MX51_PAD_GPIO1_0__SD1_CD                       694
+MX51_PAD_GPIO1_1__CSPI_MISO                    695
+MX51_PAD_GPIO1_1__GPIO1_1                      696
+MX51_PAD_GPIO1_1__SD1_WP                       697
+MX51_PAD_EIM_DA12__EIM_DA12                    698
+MX51_PAD_EIM_DA13__EIM_DA13                    699
+MX51_PAD_EIM_DA14__EIM_DA14                    700
+MX51_PAD_EIM_DA15__EIM_DA15                    701
+MX51_PAD_SD2_CMD__CSPI_MOSI                    702
+MX51_PAD_SD2_CMD__I2C1_SCL                     703
+MX51_PAD_SD2_CMD__SD2_CMD                      704
+MX51_PAD_SD2_CLK__CSPI_SCLK                    705
+MX51_PAD_SD2_CLK__I2C1_SDA                     706
+MX51_PAD_SD2_CLK__SD2_CLK                      707
+MX51_PAD_SD2_DATA0__CSPI_MISO                  708
+MX51_PAD_SD2_DATA0__SD1_DAT4                   709
+MX51_PAD_SD2_DATA0__SD2_DATA0                  710
+MX51_PAD_SD2_DATA1__SD1_DAT5                   711
+MX51_PAD_SD2_DATA1__SD2_DATA1                  712
+MX51_PAD_SD2_DATA1__USBH3_H2_DP                        713
+MX51_PAD_SD2_DATA2__SD1_DAT6                   714
+MX51_PAD_SD2_DATA2__SD2_DATA2                  715
+MX51_PAD_SD2_DATA2__USBH3_H2_DM                        716
+MX51_PAD_SD2_DATA3__CSPI_SS2                   717
+MX51_PAD_SD2_DATA3__SD1_DAT7                   718
+MX51_PAD_SD2_DATA3__SD2_DATA3                  719
+MX51_PAD_GPIO1_2__CCM_OUT_2                    720
+MX51_PAD_GPIO1_2__GPIO1_2                      721
+MX51_PAD_GPIO1_2__I2C2_SCL                     722
+MX51_PAD_GPIO1_2__PLL1_BYP                     723
+MX51_PAD_GPIO1_2__PWM1_PWMO                    724
+MX51_PAD_GPIO1_3__GPIO1_3                      725
+MX51_PAD_GPIO1_3__I2C2_SDA                     726
+MX51_PAD_GPIO1_3__PLL2_BYP                     727
+MX51_PAD_GPIO1_3__PWM2_PWMO                    728
+MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ            729
+MX51_PAD_PMIC_INT_REQ__PMIC_PMU_IRQ_B          730
+MX51_PAD_GPIO1_4__DISP2_EXT_CLK                        731
+MX51_PAD_GPIO1_4__EIM_RDY                      732
+MX51_PAD_GPIO1_4__GPIO1_4                      733
+MX51_PAD_GPIO1_4__WDOG1_WDOG_B                 734
+MX51_PAD_GPIO1_5__CSI2_MCLK                    735
+MX51_PAD_GPIO1_5__DISP2_PIN16                  736
+MX51_PAD_GPIO1_5__GPIO1_5                      737
+MX51_PAD_GPIO1_5__WDOG2_WDOG_B                 738
+MX51_PAD_GPIO1_6__DISP2_PIN17                  739
+MX51_PAD_GPIO1_6__GPIO1_6                      740
+MX51_PAD_GPIO1_6__REF_EN_B                     741
+MX51_PAD_GPIO1_7__CCM_OUT_0                    742
+MX51_PAD_GPIO1_7__GPIO1_7                      743
+MX51_PAD_GPIO1_7__SD2_WP                       744
+MX51_PAD_GPIO1_7__SPDIF_OUT1                   745
+MX51_PAD_GPIO1_8__CSI2_DATA_EN                 746
+MX51_PAD_GPIO1_8__GPIO1_8                      747
+MX51_PAD_GPIO1_8__SD2_CD                       748
+MX51_PAD_GPIO1_8__USBH3_PWR                    749
+MX51_PAD_GPIO1_9__CCM_OUT_1                    750
+MX51_PAD_GPIO1_9__DISP2_D1_CS                  751
+MX51_PAD_GPIO1_9__DISP2_SER_CS                 752
+MX51_PAD_GPIO1_9__GPIO1_9                      753
+MX51_PAD_GPIO1_9__SD2_LCTL                     754
+MX51_PAD_GPIO1_9__USBH3_OC                     755

diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 173b71d..91c1f64 100644 (file)
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -31,6 +31,14 @@ config PINCTRL_IMX
        select PINMUX
        select PINCONF
 
+config PINCTRL_IMX51
+       bool "IMX51 pinctrl driver"
+       depends on OF
+       depends on SOC_IMX51
+       select PINCTRL_IMX
+       help
+         Say Y here to enable the imx51 pinctrl driver
+
 config PINCTRL_IMX53
        bool "IMX53 pinctrl driver"
        depends on OF

diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index da185de..515e32f 100644 (file)
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_PINCTRL)         += devicetree.o
 endif
 obj-$(CONFIG_GENERIC_PINCONF)  += pinconf-generic.o
 obj-$(CONFIG_PINCTRL_IMX)      += pinctrl-imx.o
+obj-$(CONFIG_PINCTRL_IMX51)    += pinctrl-imx51.o
 obj-$(CONFIG_PINCTRL_IMX53)    += pinctrl-imx53.o
 obj-$(CONFIG_PINCTRL_IMX6Q)    += pinctrl-imx6q.o
 obj-$(CONFIG_PINCTRL_PXA3xx)   += pinctrl-pxa3xx.o

diff --git a/drivers/pinctrl/pinctrl-imx51.c b/drivers/pinctrl/pinctrl-imx51.c
new file mode 100644 (file)
index 0000000..689b3c8
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-imx51.c
@@ -0,0 +1,1322 @@
+/*
+ * imx51 pinctrl driver based on imx pinmux core
+ *
+ * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ * Copyright (C) 2012 Linaro, Inc.
+ *
+ * Author: Dong Aisheng <dong.aisheng@linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/pinctrl.h>
+
+#include "pinctrl-imx.h"
+
+enum imx51_pads {
+       MX51_PAD_EIM_D16 = 1,
+       MX51_PAD_EIM_D17 = 2,
+       MX51_PAD_EIM_D18 = 3,
+       MX51_PAD_EIM_D19 = 4,
+       MX51_PAD_EIM_D20 = 5,
+       MX51_PAD_EIM_D21 = 6,
+       MX51_PAD_EIM_D22 = 7,
+       MX51_PAD_EIM_D23 = 8,
+       MX51_PAD_EIM_D24 = 9,
+       MX51_PAD_EIM_D25 = 10,
+       MX51_PAD_EIM_D26 = 11,
+       MX51_PAD_EIM_D27 = 12,
+       MX51_PAD_EIM_D28 = 13,
+       MX51_PAD_EIM_D29 = 14,
+       MX51_PAD_EIM_D30 = 15,
+       MX51_PAD_EIM_D31 = 16,
+       MX51_PAD_EIM_A16 = 17,
+       MX51_PAD_EIM_A17 = 18,
+       MX51_PAD_EIM_A18 = 19,
+       MX51_PAD_EIM_A19 = 20,
+       MX51_PAD_EIM_A20 = 21,
+       MX51_PAD_EIM_A21 = 22,
+       MX51_PAD_EIM_A22 = 23,
+       MX51_PAD_EIM_A23 = 24,
+       MX51_PAD_EIM_A24 = 25,
+       MX51_PAD_EIM_A25 = 26,
+       MX51_PAD_EIM_A26 = 27,
+       MX51_PAD_EIM_A27 = 28,
+       MX51_PAD_EIM_EB0 = 29,
+       MX51_PAD_EIM_EB1 = 30,
+       MX51_PAD_EIM_EB2 = 31,
+       MX51_PAD_EIM_EB3 = 32,
+       MX51_PAD_EIM_OE = 33,
+       MX51_PAD_EIM_CS0 = 34,
+       MX51_PAD_EIM_CS1 = 35,
+       MX51_PAD_EIM_CS2 = 36,
+       MX51_PAD_EIM_CS3 = 37,
+       MX51_PAD_EIM_CS4 = 38,
+       MX51_PAD_EIM_CS5 = 39,
+       MX51_PAD_EIM_DTACK = 40,
+       MX51_PAD_EIM_LBA = 41,
+       MX51_PAD_EIM_CRE = 42,
+       MX51_PAD_DRAM_CS1 = 43,
+       MX51_PAD_NANDF_WE_B = 44,
+       MX51_PAD_NANDF_RE_B = 45,
+       MX51_PAD_NANDF_ALE = 46,
+       MX51_PAD_NANDF_CLE = 47,
+       MX51_PAD_NANDF_WP_B = 48,
+       MX51_PAD_NANDF_RB0 = 49,
+       MX51_PAD_NANDF_RB1 = 50,
+       MX51_PAD_NANDF_RB2 = 51,
+       MX51_PAD_NANDF_RB3 = 52,
+       MX51_PAD_GPIO_NAND = 53,
+       MX51_PAD_NANDF_CS0 = 54,
+       MX51_PAD_NANDF_CS1 = 55,
+       MX51_PAD_NANDF_CS2 = 56,
+       MX51_PAD_NANDF_CS3 = 57,
+       MX51_PAD_NANDF_CS4 = 58,
+       MX51_PAD_NANDF_CS5 = 59,
+       MX51_PAD_NANDF_CS6 = 60,
+       MX51_PAD_NANDF_CS7 = 61,
+       MX51_PAD_NANDF_RDY_INT = 62,
+       MX51_PAD_NANDF_D15 = 63,
+       MX51_PAD_NANDF_D14 = 64,
+       MX51_PAD_NANDF_D13 = 65,
+       MX51_PAD_NANDF_D12 = 66,
+       MX51_PAD_NANDF_D11 = 67,
+       MX51_PAD_NANDF_D10 = 68,
+       MX51_PAD_NANDF_D9 = 69,
+       MX51_PAD_NANDF_D8 = 70,
+       MX51_PAD_NANDF_D7 = 71,
+       MX51_PAD_NANDF_D6 = 72,
+       MX51_PAD_NANDF_D5 = 73,
+       MX51_PAD_NANDF_D4 = 74,
+       MX51_PAD_NANDF_D3 = 75,
+       MX51_PAD_NANDF_D2 = 76,
+       MX51_PAD_NANDF_D1 = 77,
+       MX51_PAD_NANDF_D0 = 78,
+       MX51_PAD_CSI1_D8 = 79,
+       MX51_PAD_CSI1_D9 = 80,
+       MX51_PAD_CSI1_D10 = 81,
+       MX51_PAD_CSI1_D11 = 82,
+       MX51_PAD_CSI1_D12 = 83,
+       MX51_PAD_CSI1_D13 = 84,
+       MX51_PAD_CSI1_D14 = 85,
+       MX51_PAD_CSI1_D15 = 86,
+       MX51_PAD_CSI1_D16 = 87,
+       MX51_PAD_CSI1_D17 = 88,
+       MX51_PAD_CSI1_D18 = 89,
+       MX51_PAD_CSI1_D19 = 90,
+       MX51_PAD_CSI1_VSYNC = 91,
+       MX51_PAD_CSI1_HSYNC = 92,
+       MX51_PAD_CSI1_PIXCLK = 93,
+       MX51_PAD_CSI1_MCLK = 94,
+       MX51_PAD_CSI2_D12 = 95,
+       MX51_PAD_CSI2_D13 = 96,
+       MX51_PAD_CSI2_D14 = 97,
+       MX51_PAD_CSI2_D15 = 98,
+       MX51_PAD_CSI2_D16 = 99,
+       MX51_PAD_CSI2_D17 = 100,
+       MX51_PAD_CSI2_D18 = 101,
+       MX51_PAD_CSI2_D19 = 102,
+       MX51_PAD_CSI2_VSYNC = 103,
+       MX51_PAD_CSI2_HSYNC = 104,
+       MX51_PAD_CSI2_PIXCLK = 105,
+       MX51_PAD_I2C1_CLK = 106,
+       MX51_PAD_I2C1_DAT = 107,
+       MX51_PAD_AUD3_BB_TXD = 108,
+       MX51_PAD_AUD3_BB_RXD = 109,
+       MX51_PAD_AUD3_BB_CK = 110,
+       MX51_PAD_AUD3_BB_FS = 111,
+       MX51_PAD_CSPI1_MOSI = 112,
+       MX51_PAD_CSPI1_MISO = 113,
+       MX51_PAD_CSPI1_SS0 = 114,
+       MX51_PAD_CSPI1_SS1 = 115,
+       MX51_PAD_CSPI1_RDY = 116,
+       MX51_PAD_CSPI1_SCLK = 117,
+       MX51_PAD_UART1_RXD = 118,
+       MX51_PAD_UART1_TXD = 119,
+       MX51_PAD_UART1_RTS = 120,
+       MX51_PAD_UART1_CTS = 121,
+       MX51_PAD_UART2_RXD = 122,
+       MX51_PAD_UART2_TXD = 123,
+       MX51_PAD_UART3_RXD = 124,
+       MX51_PAD_UART3_TXD = 125,
+       MX51_PAD_OWIRE_LINE = 126,
+       MX51_PAD_KEY_ROW0 = 127,
+       MX51_PAD_KEY_ROW1 = 128,
+       MX51_PAD_KEY_ROW2 = 129,
+       MX51_PAD_KEY_ROW3 = 130,
+       MX51_PAD_KEY_COL0 = 131,
+       MX51_PAD_KEY_COL1 = 132,
+       MX51_PAD_KEY_COL2 = 133,
+       MX51_PAD_KEY_COL3 = 134,
+       MX51_PAD_KEY_COL4 = 135,
+       MX51_PAD_KEY_COL5 = 136,
+       MX51_PAD_USBH1_CLK = 137,
+       MX51_PAD_USBH1_DIR = 138,
+       MX51_PAD_USBH1_STP = 139,
+       MX51_PAD_USBH1_NXT = 140,
+       MX51_PAD_USBH1_DATA0 = 141,
+       MX51_PAD_USBH1_DATA1 = 142,
+       MX51_PAD_USBH1_DATA2 = 143,
+       MX51_PAD_USBH1_DATA3 = 144,
+       MX51_PAD_USBH1_DATA4 = 145,
+       MX51_PAD_USBH1_DATA5 = 146,
+       MX51_PAD_USBH1_DATA6 = 147,
+       MX51_PAD_USBH1_DATA7 = 148,
+       MX51_PAD_DI1_PIN11 = 149,
+       MX51_PAD_DI1_PIN12 = 150,
+       MX51_PAD_DI1_PIN13 = 151,
+       MX51_PAD_DI1_D0_CS = 152,
+       MX51_PAD_DI1_D1_CS = 153,
+       MX51_PAD_DISPB2_SER_DIN = 154,
+       MX51_PAD_DISPB2_SER_DIO = 155,
+       MX51_PAD_DISPB2_SER_CLK = 156,
+       MX51_PAD_DISPB2_SER_RS = 157,
+       MX51_PAD_DISP1_DAT0 = 158,
+       MX51_PAD_DISP1_DAT1 = 159,
+       MX51_PAD_DISP1_DAT2 = 160,
+       MX51_PAD_DISP1_DAT3 = 161,
+       MX51_PAD_DISP1_DAT4 = 162,
+       MX51_PAD_DISP1_DAT5 = 163,
+       MX51_PAD_DISP1_DAT6 = 164,
+       MX51_PAD_DISP1_DAT7 = 165,
+       MX51_PAD_DISP1_DAT8 = 166,
+       MX51_PAD_DISP1_DAT9 = 167,
+       MX51_PAD_DISP1_DAT10 = 168,
+       MX51_PAD_DISP1_DAT11 = 169,
+       MX51_PAD_DISP1_DAT12 = 170,
+       MX51_PAD_DISP1_DAT13 = 171,
+       MX51_PAD_DISP1_DAT14 = 172,
+       MX51_PAD_DISP1_DAT15 = 173,
+       MX51_PAD_DISP1_DAT16 = 174,
+       MX51_PAD_DISP1_DAT17 = 175,
+       MX51_PAD_DISP1_DAT18 = 176,
+       MX51_PAD_DISP1_DAT19 = 177,
+       MX51_PAD_DISP1_DAT20 = 178,
+       MX51_PAD_DISP1_DAT21 = 179,
+       MX51_PAD_DISP1_DAT22 = 180,
+       MX51_PAD_DISP1_DAT23 = 181,
+       MX51_PAD_DI1_PIN3 = 182,
+       MX51_PAD_DI1_PIN2 = 183,
+       MX51_PAD_DI_GP2 = 184,
+       MX51_PAD_DI_GP3 = 185,
+       MX51_PAD_DI2_PIN4 = 186,
+       MX51_PAD_DI2_PIN2 = 187,
+       MX51_PAD_DI2_PIN3 = 188,
+       MX51_PAD_DI2_DISP_CLK = 189,
+       MX51_PAD_DI_GP4 = 190,
+       MX51_PAD_DISP2_DAT0 = 191,
+       MX51_PAD_DISP2_DAT1 = 192,
+       MX51_PAD_DISP2_DAT2 = 193,
+       MX51_PAD_DISP2_DAT3 = 194,
+       MX51_PAD_DISP2_DAT4 = 195,
+       MX51_PAD_DISP2_DAT5 = 196,
+       MX51_PAD_DISP2_DAT6 = 197,
+       MX51_PAD_DISP2_DAT7 = 198,
+       MX51_PAD_DISP2_DAT8 = 199,
+       MX51_PAD_DISP2_DAT9 = 200,
+       MX51_PAD_DISP2_DAT10 = 201,
+       MX51_PAD_DISP2_DAT11 = 202,
+       MX51_PAD_DISP2_DAT12 = 203,
+       MX51_PAD_DISP2_DAT13 = 204,
+       MX51_PAD_DISP2_DAT14 = 205,
+       MX51_PAD_DISP2_DAT15 = 206,
+       MX51_PAD_SD1_CMD = 207,
+       MX51_PAD_SD1_CLK = 208,
+       MX51_PAD_SD1_DATA0 = 209,
+       MX51_PAD_EIM_DA0 = 210,
+       MX51_PAD_EIM_DA1 = 211,
+       MX51_PAD_EIM_DA2 = 212,
+       MX51_PAD_EIM_DA3 = 213,
+       MX51_PAD_SD1_DATA1 = 214,
+       MX51_PAD_EIM_DA4 = 215,
+       MX51_PAD_EIM_DA5 = 216,
+       MX51_PAD_EIM_DA6 = 217,
+       MX51_PAD_EIM_DA7 = 218,
+       MX51_PAD_SD1_DATA2 = 219,
+       MX51_PAD_EIM_DA10 = 220,
+       MX51_PAD_EIM_DA11 = 221,
+       MX51_PAD_EIM_DA8 = 222,
+       MX51_PAD_EIM_DA9 = 223,
+       MX51_PAD_SD1_DATA3 = 224,
+       MX51_PAD_GPIO1_0 = 225,
+       MX51_PAD_GPIO1_1 = 226,
+       MX51_PAD_EIM_DA12 = 227,
+       MX51_PAD_EIM_DA13 = 228,
+       MX51_PAD_EIM_DA14 = 229,
+       MX51_PAD_EIM_DA15 = 230,
+       MX51_PAD_SD2_CMD = 231,
+       MX51_PAD_SD2_CLK = 232,
+       MX51_PAD_SD2_DATA0 = 233,
+       MX51_PAD_SD2_DATA1 = 234,
+       MX51_PAD_SD2_DATA2 = 235,
+       MX51_PAD_SD2_DATA3 = 236,
+       MX51_PAD_GPIO1_2 = 237,
+       MX51_PAD_GPIO1_3 = 238,
+       MX51_PAD_PMIC_INT_REQ = 239,
+       MX51_PAD_GPIO1_4 = 240,
+       MX51_PAD_GPIO1_5 = 241,
+       MX51_PAD_GPIO1_6 = 242,
+       MX51_PAD_GPIO1_7 = 243,
+       MX51_PAD_GPIO1_8 = 244,
+       MX51_PAD_GPIO1_9 = 245,
+};
+
+/* imx51 register maps */
+static struct imx_pin_reg imx51_pin_regs[] = {
+       IMX_PIN_REG(MX51_PAD_EIM_D16, 0x3f0, 0x05c, 5, 0x000, 0), /* MX51_PAD_EIM_D16__AUD4_RXFS */
+       IMX_PIN_REG(MX51_PAD_EIM_D16, 0x3f0, 0x05c, 7, 0x8d8, 0), /* MX51_PAD_EIM_D16__AUD5_TXD */
+       IMX_PIN_REG(MX51_PAD_EIM_D16, 0x3f0, 0x05c, 0, 0x000, 0), /* MX51_PAD_EIM_D16__EIM_D16 */
+       IMX_PIN_REG(MX51_PAD_EIM_D16, 0x3f0, 0x05c, 1, 0x000, 0), /* MX51_PAD_EIM_D16__GPIO2_0 */
+       IMX_PIN_REG(MX51_PAD_EIM_D16, 0x3f0, 0x05c, 4, 0x9b4, 0), /* MX51_PAD_EIM_D16__I2C1_SDA */
+       IMX_PIN_REG(MX51_PAD_EIM_D16, 0x3f0, 0x05c, 3, 0x000, 0), /* MX51_PAD_EIM_D16__UART2_CTS */
+       IMX_PIN_REG(MX51_PAD_EIM_D16, 0x3f0, 0x05c, 2, 0x000, 0), /* MX51_PAD_EIM_D16__USBH2_DATA0 */
+       IMX_PIN_REG(MX51_PAD_EIM_D17, 0x3f4, 0x060, 7, 0x8d4, 0), /* MX51_PAD_EIM_D17__AUD5_RXD */
+       IMX_PIN_REG(MX51_PAD_EIM_D17, 0x3f4, 0x060, 0, 0x000, 0), /* MX51_PAD_EIM_D17__EIM_D17 */
+       IMX_PIN_REG(MX51_PAD_EIM_D17, 0x3f4, 0x060, 1, 0x000, 0), /* MX51_PAD_EIM_D17__GPIO2_1 */
+       IMX_PIN_REG(MX51_PAD_EIM_D17, 0x3f4, 0x060, 3, 0x9ec, 0), /* MX51_PAD_EIM_D17__UART2_RXD */
+       IMX_PIN_REG(MX51_PAD_EIM_D17, 0x3f4, 0x060, 4, 0x000, 0), /* MX51_PAD_EIM_D17__UART3_CTS */
+       IMX_PIN_REG(MX51_PAD_EIM_D17, 0x3f4, 0x060, 2, 0x000, 0), /* MX51_PAD_EIM_D17__USBH2_DATA1 */
+       IMX_PIN_REG(MX51_PAD_EIM_D18, 0x3f8, 0x064, 7, 0x8e4, 0), /* MX51_PAD_EIM_D18__AUD5_TXC */
+       IMX_PIN_REG(MX51_PAD_EIM_D18, 0x3f8, 0x064, 0, 0x000, 0), /* MX51_PAD_EIM_D18__EIM_D18 */
+       IMX_PIN_REG(MX51_PAD_EIM_D18, 0x3f8, 0x064, 1, 0x000, 0), /* MX51_PAD_EIM_D18__GPIO2_2 */
+       IMX_PIN_REG(MX51_PAD_EIM_D18, 0x3f8, 0x064, 3, 0x000, 0), /* MX51_PAD_EIM_D18__UART2_TXD */
+       IMX_PIN_REG(MX51_PAD_EIM_D18, 0x3f8, 0x064, 4, 0x9f0, 1), /* MX51_PAD_EIM_D18__UART3_RTS */
+       IMX_PIN_REG(MX51_PAD_EIM_D18, 0x3f8, 0x064, 2, 0x000, 0), /* MX51_PAD_EIM_D18__USBH2_DATA2 */
+       IMX_PIN_REG(MX51_PAD_EIM_D19, 0x3fc, 0x068, 5, 0x000, 0), /* MX51_PAD_EIM_D19__AUD4_RXC */
+       IMX_PIN_REG(MX51_PAD_EIM_D19, 0x3fc, 0x068, 7, 0x8e8, 0), /* MX51_PAD_EIM_D19__AUD5_TXFS */
+       IMX_PIN_REG(MX51_PAD_EIM_D19, 0x3fc, 0x068, 0, 0x000, 0), /* MX51_PAD_EIM_D19__EIM_D19 */
+       IMX_PIN_REG(MX51_PAD_EIM_D19, 0x3fc, 0x068, 1, 0x000, 0), /* MX51_PAD_EIM_D19__GPIO2_3 */
+       IMX_PIN_REG(MX51_PAD_EIM_D19, 0x3fc, 0x068, 4, 0x9b0, 0), /* MX51_PAD_EIM_D19__I2C1_SCL */
+       IMX_PIN_REG(MX51_PAD_EIM_D19, 0x3fc, 0x068, 3, 0x9e8, 1), /* MX51_PAD_EIM_D19__UART2_RTS */
+       IMX_PIN_REG(MX51_PAD_EIM_D19, 0x3fc, 0x068, 2, 0x000, 0), /* MX51_PAD_EIM_D19__USBH2_DATA3 */
+       IMX_PIN_REG(MX51_PAD_EIM_D20, 0x400, 0x06c, 5, 0x8c8, 0), /* MX51_PAD_EIM_D20__AUD4_TXD */
+       IMX_PIN_REG(MX51_PAD_EIM_D20, 0x400, 0x06c, 0, 0x000, 0), /* MX51_PAD_EIM_D20__EIM_D20 */
+       IMX_PIN_REG(MX51_PAD_EIM_D20, 0x400, 0x06c, 1, 0x000, 0), /* MX51_PAD_EIM_D20__GPIO2_4 */
+       IMX_PIN_REG(MX51_PAD_EIM_D20, 0x400, 0x06c, 4, 0x000, 0), /* MX51_PAD_EIM_D20__SRTC_ALARM_DEB */
+       IMX_PIN_REG(MX51_PAD_EIM_D20, 0x400, 0x06c, 2, 0x000, 0), /* MX51_PAD_EIM_D20__USBH2_DATA4 */
+       IMX_PIN_REG(MX51_PAD_EIM_D21, 0x404, 0x070, 5, 0x8c4, 0), /* MX51_PAD_EIM_D21__AUD4_RXD */
+       IMX_PIN_REG(MX51_PAD_EIM_D21, 0x404, 0x070, 0, 0x000, 0), /* MX51_PAD_EIM_D21__EIM_D21 */
+       IMX_PIN_REG(MX51_PAD_EIM_D21, 0x404, 0x070, 1, 0x000, 0), /* MX51_PAD_EIM_D21__GPIO2_5 */
+       IMX_PIN_REG(MX51_PAD_EIM_D21, 0x404, 0x070, 3, 0x000, 0), /* MX51_PAD_EIM_D21__SRTC_ALARM_DEB */
+       IMX_PIN_REG(MX51_PAD_EIM_D21, 0x404, 0x070, 2, 0x000, 0), /* MX51_PAD_EIM_D21__USBH2_DATA5 */
+       IMX_PIN_REG(MX51_PAD_EIM_D22, 0x408, 0x074, 5, 0x8cc, 0), /* MX51_PAD_EIM_D22__AUD4_TXC */
+       IMX_PIN_REG(MX51_PAD_EIM_D22, 0x408, 0x074, 0, 0x000, 0), /* MX51_PAD_EIM_D22__EIM_D22 */
+       IMX_PIN_REG(MX51_PAD_EIM_D22, 0x408, 0x074, 1, 0x000, 0), /* MX51_PAD_EIM_D22__GPIO2_6 */
+       IMX_PIN_REG(MX51_PAD_EIM_D22, 0x408, 0x074, 2, 0x000, 0), /* MX51_PAD_EIM_D22__USBH2_DATA6 */
+       IMX_PIN_REG(MX51_PAD_EIM_D23, 0x40c, 0x078, 5, 0x8d0, 0), /* MX51_PAD_EIM_D23__AUD4_TXFS */
+       IMX_PIN_REG(MX51_PAD_EIM_D23, 0x40c, 0x078, 0, 0x000, 0), /* MX51_PAD_EIM_D23__EIM_D23 */
+       IMX_PIN_REG(MX51_PAD_EIM_D23, 0x40c, 0x078, 1, 0x000, 0), /* MX51_PAD_EIM_D23__GPIO2_7 */
+       IMX_PIN_REG(MX51_PAD_EIM_D23, 0x40c, 0x078, 4, 0x000, 0), /* MX51_PAD_EIM_D23__SPDIF_OUT1 */
+       IMX_PIN_REG(MX51_PAD_EIM_D23, 0x40c, 0x078, 2, 0x000, 0), /* MX51_PAD_EIM_D23__USBH2_DATA7 */
+       IMX_PIN_REG(MX51_PAD_EIM_D24, 0x410, 0x07c, 5, 0x8f8, 0), /* MX51_PAD_EIM_D24__AUD6_RXFS */
+       IMX_PIN_REG(MX51_PAD_EIM_D24, 0x410, 0x07c, 0, 0x000, 0), /* MX51_PAD_EIM_D24__EIM_D24 */
+       IMX_PIN_REG(MX51_PAD_EIM_D24, 0x410, 0x07c, 1, 0x000, 0), /* MX51_PAD_EIM_D24__GPIO2_8 */
+       IMX_PIN_REG(MX51_PAD_EIM_D24, 0x410, 0x07c, 4, 0x9bc, 0), /* MX51_PAD_EIM_D24__I2C2_SDA */
+       IMX_PIN_REG(MX51_PAD_EIM_D24, 0x410, 0x07c, 3, 0x000, 0), /* MX51_PAD_EIM_D24__UART3_CTS */
+       IMX_PIN_REG(MX51_PAD_EIM_D24, 0x410, 0x07c, 2, 0x000, 0), /* MX51_PAD_EIM_D24__USBOTG_DATA0 */
+       IMX_PIN_REG(MX51_PAD_EIM_D25, 0x414, 0x080, 0, 0x000, 0), /* MX51_PAD_EIM_D25__EIM_D25 */
+       IMX_PIN_REG(MX51_PAD_EIM_D25, 0x414, 0x080, 1, 0x9c8, 0), /* MX51_PAD_EIM_D25__KEY_COL6 */
+       IMX_PIN_REG(MX51_PAD_EIM_D25, 0x414, 0x080, 4, 0x000, 0), /* MX51_PAD_EIM_D25__UART2_CTS */
+       IMX_PIN_REG(MX51_PAD_EIM_D25, 0x414, 0x080, 3, 0x9f4, 0), /* MX51_PAD_EIM_D25__UART3_RXD */
+       IMX_PIN_REG(MX51_PAD_EIM_D25, 0x414, 0x080, 2, 0x000, 0), /* MX51_PAD_EIM_D25__USBOTG_DATA1 */
+       IMX_PIN_REG(MX51_PAD_EIM_D26, 0x418, 0x084, 0, 0x000, 0), /* MX51_PAD_EIM_D26__EIM_D26 */
+       IMX_PIN_REG(MX51_PAD_EIM_D26, 0x418, 0x084, 1, 0x9cc, 0), /* MX51_PAD_EIM_D26__KEY_COL7 */
+       IMX_PIN_REG(MX51_PAD_EIM_D26, 0x418, 0x084, 4, 0x9e8, 3), /* MX51_PAD_EIM_D26__UART2_RTS */
+       IMX_PIN_REG(MX51_PAD_EIM_D26, 0x418, 0x084, 3, 0x000, 0), /* MX51_PAD_EIM_D26__UART3_TXD */
+       IMX_PIN_REG(MX51_PAD_EIM_D26, 0x418, 0x084, 2, 0x000, 0), /* MX51_PAD_EIM_D26__USBOTG_DATA2 */
+       IMX_PIN_REG(MX51_PAD_EIM_D27, 0x41c, 0x088, 5, 0x8f4, 0), /* MX51_PAD_EIM_D27__AUD6_RXC */
+       IMX_PIN_REG(MX51_PAD_EIM_D27, 0x41c, 0x088, 0, 0x000, 0), /* MX51_PAD_EIM_D27__EIM_D27 */
+       IMX_PIN_REG(MX51_PAD_EIM_D27, 0x41c, 0x088, 1, 0x000, 0), /* MX51_PAD_EIM_D27__GPIO2_9 */
+       IMX_PIN_REG(MX51_PAD_EIM_D27, 0x41c, 0x088, 4, 0x9b8, 0), /* MX51_PAD_EIM_D27__I2C2_SCL */
+       IMX_PIN_REG(MX51_PAD_EIM_D27, 0x41c, 0x088, 3, 0x9f0, 3), /* MX51_PAD_EIM_D27__UART3_RTS */
+       IMX_PIN_REG(MX51_PAD_EIM_D27, 0x41c, 0x088, 2, 0x000, 0), /* MX51_PAD_EIM_D27__USBOTG_DATA3 */
+       IMX_PIN_REG(MX51_PAD_EIM_D28, 0x420, 0x08c, 5, 0x8f0, 0), /* MX51_PAD_EIM_D28__AUD6_TXD */
+       IMX_PIN_REG(MX51_PAD_EIM_D28, 0x420, 0x08c, 0, 0x000, 0), /* MX51_PAD_EIM_D28__EIM_D28 */
+       IMX_PIN_REG(MX51_PAD_EIM_D28, 0x420, 0x08c, 1, 0x9d0, 0), /* MX51_PAD_EIM_D28__KEY_ROW4 */
+       IMX_PIN_REG(MX51_PAD_EIM_D28, 0x420, 0x08c, 2, 0x000, 0), /* MX51_PAD_EIM_D28__USBOTG_DATA4 */
+       IMX_PIN_REG(MX51_PAD_EIM_D29, 0x424, 0x090, 5, 0x8ec, 0), /* MX51_PAD_EIM_D29__AUD6_RXD */
+       IMX_PIN_REG(MX51_PAD_EIM_D29, 0x424, 0x090, 0, 0x000, 0), /* MX51_PAD_EIM_D29__EIM_D29 */
+       IMX_PIN_REG(MX51_PAD_EIM_D29, 0x424, 0x090, 1, 0x9d4, 0), /* MX51_PAD_EIM_D29__KEY_ROW5 */
+       IMX_PIN_REG(MX51_PAD_EIM_D29, 0x424, 0x090, 2, 0x000, 0), /* MX51_PAD_EIM_D29__USBOTG_DATA5 */
+       IMX_PIN_REG(MX51_PAD_EIM_D30, 0x428, 0x094, 5, 0x8fc, 0), /* MX51_PAD_EIM_D30__AUD6_TXC */
+       IMX_PIN_REG(MX51_PAD_EIM_D30, 0x428, 0x094, 0, 0x000, 0), /* MX51_PAD_EIM_D30__EIM_D30 */
+       IMX_PIN_REG(MX51_PAD_EIM_D30, 0x428, 0x094, 1, 0x9d8, 0), /* MX51_PAD_EIM_D30__KEY_ROW6 */
+       IMX_PIN_REG(MX51_PAD_EIM_D30, 0x428, 0x094, 2, 0x000, 0), /* MX51_PAD_EIM_D30__USBOTG_DATA6 */
+       IMX_PIN_REG(MX51_PAD_EIM_D31, 0x42c, 0x098, 5, 0x900, 0), /* MX51_PAD_EIM_D31__AUD6_TXFS */
+       IMX_PIN_REG(MX51_PAD_EIM_D31, 0x42c, 0x098, 0, 0x000, 0), /* MX51_PAD_EIM_D31__EIM_D31 */
+       IMX_PIN_REG(MX51_PAD_EIM_D31, 0x42c, 0x098, 1, 0x9dc, 0), /* MX51_PAD_EIM_D31__KEY_ROW7 */
+       IMX_PIN_REG(MX51_PAD_EIM_D31, 0x42c, 0x098, 2, 0x000, 0), /* MX51_PAD_EIM_D31__USBOTG_DATA7 */
+       IMX_PIN_REG(MX51_PAD_EIM_A16, 0x430, 0x09c, 0, 0x000, 0), /* MX51_PAD_EIM_A16__EIM_A16 */
+       IMX_PIN_REG(MX51_PAD_EIM_A16, 0x430, 0x09c, 1, 0x000, 0), /* MX51_PAD_EIM_A16__GPIO2_10 */
+       IMX_PIN_REG(MX51_PAD_EIM_A16, 0x430, 0x09c, 7, 0x000, 0), /* MX51_PAD_EIM_A16__OSC_FREQ_SEL0 */
+       IMX_PIN_REG(MX51_PAD_EIM_A17, 0x434, 0x0a0, 0, 0x000, 0), /* MX51_PAD_EIM_A17__EIM_A17 */
+       IMX_PIN_REG(MX51_PAD_EIM_A17, 0x434, 0x0a0, 1, 0x000, 0), /* MX51_PAD_EIM_A17__GPIO2_11 */
+       IMX_PIN_REG(MX51_PAD_EIM_A17, 0x434, 0x0a0, 7, 0x000, 0), /* MX51_PAD_EIM_A17__OSC_FREQ_SEL1 */
+       IMX_PIN_REG(MX51_PAD_EIM_A18, 0x438, 0x0a4, 7, 0x000, 0), /* MX51_PAD_EIM_A18__BOOT_LPB0 */
+       IMX_PIN_REG(MX51_PAD_EIM_A18, 0x438, 0x0a4, 0, 0x000, 0), /* MX51_PAD_EIM_A18__EIM_A18 */
+       IMX_PIN_REG(MX51_PAD_EIM_A18, 0x438, 0x0a4, 1, 0x000, 0), /* MX51_PAD_EIM_A18__GPIO2_12 */
+       IMX_PIN_REG(MX51_PAD_EIM_A19, 0x43c, 0x0a8, 7, 0x000, 0), /* MX51_PAD_EIM_A19__BOOT_LPB1 */
+       IMX_PIN_REG(MX51_PAD_EIM_A19, 0x43c, 0x0a8, 0, 0x000, 0), /* MX51_PAD_EIM_A19__EIM_A19 */
+       IMX_PIN_REG(MX51_PAD_EIM_A19, 0x43c, 0x0a8, 1, 0x000, 0), /* MX51_PAD_EIM_A19__GPIO2_13 */
+       IMX_PIN_REG(MX51_PAD_EIM_A20, 0x440, 0x0ac, 7, 0x000, 0), /* MX51_PAD_EIM_A20__BOOT_UART_SRC0 */
+       IMX_PIN_REG(MX51_PAD_EIM_A20, 0x440, 0x0ac, 0, 0x000, 0), /* MX51_PAD_EIM_A20__EIM_A20 */
+       IMX_PIN_REG(MX51_PAD_EIM_A20, 0x440, 0x0ac, 1, 0x000, 0), /* MX51_PAD_EIM_A20__GPIO2_14 */
+       IMX_PIN_REG(MX51_PAD_EIM_A21, 0x444, 0x0b0, 7, 0x000, 0), /* MX51_PAD_EIM_A21__BOOT_UART_SRC1 */
+       IMX_PIN_REG(MX51_PAD_EIM_A21, 0x444, 0x0b0, 0, 0x000, 0), /* MX51_PAD_EIM_A21__EIM_A21 */
+       IMX_PIN_REG(MX51_PAD_EIM_A21, 0x444, 0x0b0, 1, 0x000, 0), /* MX51_PAD_EIM_A21__GPIO2_15 */
+       IMX_PIN_REG(MX51_PAD_EIM_A22, 0x448, 0x0b4, 0, 0x000, 0), /* MX51_PAD_EIM_A22__EIM_A22 */
+       IMX_PIN_REG(MX51_PAD_EIM_A22, 0x448, 0x0b4, 1, 0x000, 0), /* MX51_PAD_EIM_A22__GPIO2_16 */
+       IMX_PIN_REG(MX51_PAD_EIM_A23, 0x44c, 0x0b8, 7, 0x000, 0), /* MX51_PAD_EIM_A23__BOOT_HPN_EN */
+       IMX_PIN_REG(MX51_PAD_EIM_A23, 0x44c, 0x0b8, 0, 0x000, 0), /* MX51_PAD_EIM_A23__EIM_A23 */
+       IMX_PIN_REG(MX51_PAD_EIM_A23, 0x44c, 0x0b8, 1, 0x000, 0), /* MX51_PAD_EIM_A23__GPIO2_17 */
+       IMX_PIN_REG(MX51_PAD_EIM_A24, 0x450, 0x0bc, 0, 0x000, 0), /* MX51_PAD_EIM_A24__EIM_A24 */
+       IMX_PIN_REG(MX51_PAD_EIM_A24, 0x450, 0x0bc, 1, 0x000, 0), /* MX51_PAD_EIM_A24__GPIO2_18 */
+       IMX_PIN_REG(MX51_PAD_EIM_A24, 0x450, 0x0bc, 2, 0x000, 0), /* MX51_PAD_EIM_A24__USBH2_CLK */
+       IMX_PIN_REG(MX51_PAD_EIM_A25, 0x454, 0x0c0, 6, 0x000, 0), /* MX51_PAD_EIM_A25__DISP1_PIN4 */
+       IMX_PIN_REG(MX51_PAD_EIM_A25, 0x454, 0x0c0, 0, 0x000, 0), /* MX51_PAD_EIM_A25__EIM_A25 */
+       IMX_PIN_REG(MX51_PAD_EIM_A25, 0x454, 0x0c0, 1, 0x000, 0), /* MX51_PAD_EIM_A25__GPIO2_19 */
+       IMX_PIN_REG(MX51_PAD_EIM_A25, 0x454, 0x0c0, 2, 0x000, 0), /* MX51_PAD_EIM_A25__USBH2_DIR */
+       IMX_PIN_REG(MX51_PAD_EIM_A26, 0x458, 0x0c4, 5, 0x9a0, 0), /* MX51_PAD_EIM_A26__CSI1_DATA_EN */
+       IMX_PIN_REG(MX51_PAD_EIM_A26, 0x458, 0x0c4, 6, 0x908, 0), /* MX51_PAD_EIM_A26__DISP2_EXT_CLK */
+       IMX_PIN_REG(MX51_PAD_EIM_A26, 0x458, 0x0c4, 0, 0x000, 0), /* MX51_PAD_EIM_A26__EIM_A26 */
+       IMX_PIN_REG(MX51_PAD_EIM_A26, 0x458, 0x0c4, 1, 0x000, 0), /* MX51_PAD_EIM_A26__GPIO2_20 */
+       IMX_PIN_REG(MX51_PAD_EIM_A26, 0x458, 0x0c4, 2, 0x000, 0), /* MX51_PAD_EIM_A26__USBH2_STP */
+       IMX_PIN_REG(MX51_PAD_EIM_A27, 0x45c, 0x0c8, 5, 0x99c, 0), /* MX51_PAD_EIM_A27__CSI2_DATA_EN */
+       IMX_PIN_REG(MX51_PAD_EIM_A27, 0x45c, 0x0c8, 6, 0x9a4, 0), /* MX51_PAD_EIM_A27__DISP1_PIN1 */
+       IMX_PIN_REG(MX51_PAD_EIM_A27, 0x45c, 0x0c8, 0, 0x000, 0), /* MX51_PAD_EIM_A27__EIM_A27 */
+       IMX_PIN_REG(MX51_PAD_EIM_A27, 0x45c, 0x0c8, 1, 0x000, 0), /* MX51_PAD_EIM_A27__GPIO2_21 */
+       IMX_PIN_REG(MX51_PAD_EIM_A27, 0x45c, 0x0c8, 2, 0x000, 0), /* MX51_PAD_EIM_A27__USBH2_NXT */
+       IMX_PIN_REG(MX51_PAD_EIM_EB0, 0x460, 0x0cc, 0, 0x000, 0), /* MX51_PAD_EIM_EB0__EIM_EB0 */
+       IMX_PIN_REG(MX51_PAD_EIM_EB1, 0x464, 0x0d0, 0, 0x000, 0), /* MX51_PAD_EIM_EB1__EIM_EB1 */
+       IMX_PIN_REG(MX51_PAD_EIM_EB2, 0x468, 0x0d4, 6, 0x8e0, 0), /* MX51_PAD_EIM_EB2__AUD5_RXFS */
+       IMX_PIN_REG(MX51_PAD_EIM_EB2, 0x468, 0x0d4, 5, 0x000, 0), /* MX51_PAD_EIM_EB2__CSI1_D2 */
+       IMX_PIN_REG(MX51_PAD_EIM_EB2, 0x468, 0x0d4, 0, 0x000, 0), /* MX51_PAD_EIM_EB2__EIM_EB2 */
+       IMX_PIN_REG(MX51_PAD_EIM_EB2, 0x468, 0x0d4, 3, 0x954, 0), /* MX51_PAD_EIM_EB2__FEC_MDIO */
+       IMX_PIN_REG(MX51_PAD_EIM_EB2, 0x468, 0x0d4, 1, 0x000, 0), /* MX51_PAD_EIM_EB2__GPIO2_22 */
+       IMX_PIN_REG(MX51_PAD_EIM_EB2, 0x468, 0x0d4, 7, 0x000, 0), /* MX51_PAD_EIM_EB2__GPT_CMPOUT1 */
+       IMX_PIN_REG(MX51_PAD_EIM_EB3, 0x46c, 0x0d8, 6, 0x8dc, 0), /* MX51_PAD_EIM_EB3__AUD5_RXC */
+       IMX_PIN_REG(MX51_PAD_EIM_EB3, 0x46c, 0x0d8, 5, 0x000, 0), /* MX51_PAD_EIM_EB3__CSI1_D3 */
+       IMX_PIN_REG(MX51_PAD_EIM_EB3, 0x46c, 0x0d8, 0, 0x000, 0), /* MX51_PAD_EIM_EB3__EIM_EB3 */
+       IMX_PIN_REG(MX51_PAD_EIM_EB3, 0x46c, 0x0d8, 3, 0x95c, 0), /* MX51_PAD_EIM_EB3__FEC_RDATA1 */
+       IMX_PIN_REG(MX51_PAD_EIM_EB3, 0x46c, 0x0d8, 1, 0x000, 0), /* MX51_PAD_EIM_EB3__GPIO2_23 */
+       IMX_PIN_REG(MX51_PAD_EIM_EB3, 0x46c, 0x0d8, 7, 0x000, 0), /* MX51_PAD_EIM_EB3__GPT_CMPOUT2 */
+       IMX_PIN_REG(MX51_PAD_EIM_OE, 0x470, 0x0dc, 0, 0x000, 0), /* MX51_PAD_EIM_OE__EIM_OE */
+       IMX_PIN_REG(MX51_PAD_EIM_OE, 0x470, 0x0dc, 1, 0x000, 0), /* MX51_PAD_EIM_OE__GPIO2_24 */
+       IMX_PIN_REG(MX51_PAD_EIM_CS0, 0x474, 0x0e0, 0, 0x000, 0), /* MX51_PAD_EIM_CS0__EIM_CS0 */
+       IMX_PIN_REG(MX51_PAD_EIM_CS0, 0x474, 0x0e0, 1, 0x000, 0), /* MX51_PAD_EIM_CS0__GPIO2_25 */
+       IMX_PIN_REG(MX51_PAD_EIM_CS1, 0x478, 0x0e4, 0, 0x000, 0), /* MX51_PAD_EIM_CS1__EIM_CS1 */
+       IMX_PIN_REG(MX51_PAD_EIM_CS1, 0x478, 0x0e4, 1, 0x000, 0), /* MX51_PAD_EIM_CS1__GPIO2_26 */
+       IMX_PIN_REG(MX51_PAD_EIM_CS2, 0x47c, 0x0e8, 6, 0x8d8, 1), /* MX51_PAD_EIM_CS2__AUD5_TXD */
+       IMX_PIN_REG(MX51_PAD_EIM_CS2, 0x47c, 0x0e8, 5, 0x000, 0), /* MX51_PAD_EIM_CS2__CSI1_D4 */
+       IMX_PIN_REG(MX51_PAD_EIM_CS2, 0x47c, 0x0e8, 0, 0x000, 0), /* MX51_PAD_EIM_CS2__EIM_CS2 */
+       IMX_PIN_REG(MX51_PAD_EIM_CS2, 0x47c, 0x0e8, 3, 0x960, 0), /* MX51_PAD_EIM_CS2__FEC_RDATA2 */
+       IMX_PIN_REG(MX51_PAD_EIM_CS2, 0x47c, 0x0e8, 1, 0x000, 0), /* MX51_PAD_EIM_CS2__GPIO2_27 */
+       IMX_PIN_REG(MX51_PAD_EIM_CS2, 0x47c, 0x0e8, 2, 0x000, 0), /* MX51_PAD_EIM_CS2__USBOTG_STP */
+       IMX_PIN_REG(MX51_PAD_EIM_CS3, 0x480, 0x0ec, 6, 0x8d4, 1), /* MX51_PAD_EIM_CS3__AUD5_RXD */
+       IMX_PIN_REG(MX51_PAD_EIM_CS3, 0x480, 0x0ec, 5, 0x000, 0), /* MX51_PAD_EIM_CS3__CSI1_D5 */
+       IMX_PIN_REG(MX51_PAD_EIM_CS3, 0x480, 0x0ec, 0, 0x000, 0), /* MX51_PAD_EIM_CS3__EIM_CS3 */
+       IMX_PIN_REG(MX51_PAD_EIM_CS3, 0x480, 0x0ec, 3, 0x964, 0), /* MX51_PAD_EIM_CS3__FEC_RDATA3 */
+       IMX_PIN_REG(MX51_PAD_EIM_CS3, 0x480, 0x0ec, 1, 0x000, 0), /* MX51_PAD_EIM_CS3__GPIO2_28 */
+       IMX_PIN_REG(MX51_PAD_EIM_CS3, 0x480, 0x0ec, 2, 0x000, 0), /* MX51_PAD_EIM_CS3__USBOTG_NXT */
+       IMX_PIN_REG(MX51_PAD_EIM_CS4, 0x484, 0x0f0, 6, 0x8e4, 1), /* MX51_PAD_EIM_CS4__AUD5_TXC */
+       IMX_PIN_REG(MX51_PAD_EIM_CS4, 0x484, 0x0f0, 5, 0x000, 0), /* MX51_PAD_EIM_CS4__CSI1_D6 */
+       IMX_PIN_REG(MX51_PAD_EIM_CS4, 0x484, 0x0f0, 0, 0x000, 0), /* MX51_PAD_EIM_CS4__EIM_CS4 */
+       IMX_PIN_REG(MX51_PAD_EIM_CS4, 0x484, 0x0f0, 3, 0x970, 0), /* MX51_PAD_EIM_CS4__FEC_RX_ER */
+       IMX_PIN_REG(MX51_PAD_EIM_CS4, 0x484, 0x0f0, 1, 0x000, 0), /* MX51_PAD_EIM_CS4__GPIO2_29 */
+       IMX_PIN_REG(MX51_PAD_EIM_CS4, 0x484, 0x0f0, 2, 0x000, 0), /* MX51_PAD_EIM_CS4__USBOTG_CLK */
+       IMX_PIN_REG(MX51_PAD_EIM_CS5, 0x488, 0x0f4, 6, 0x8e8, 1), /* MX51_PAD_EIM_CS5__AUD5_TXFS */
+       IMX_PIN_REG(MX51_PAD_EIM_CS5, 0x488, 0x0f4, 5, 0x000, 0), /* MX51_PAD_EIM_CS5__CSI1_D7 */
+       IMX_PIN_REG(MX51_PAD_EIM_CS5, 0x488, 0x0f4, 4, 0x904, 0), /* MX51_PAD_EIM_CS5__DISP1_EXT_CLK */
+       IMX_PIN_REG(MX51_PAD_EIM_CS5, 0x488, 0x0f4, 0, 0x000, 0), /* MX51_PAD_EIM_CS5__EIM_CS5 */
+       IMX_PIN_REG(MX51_PAD_EIM_CS5, 0x488, 0x0f4, 3, 0x950, 0), /* MX51_PAD_EIM_CS5__FEC_CRS */
+       IMX_PIN_REG(MX51_PAD_EIM_CS5, 0x488, 0x0f4, 1, 0x000, 0), /* MX51_PAD_EIM_CS5__GPIO2_30 */
+       IMX_PIN_REG(MX51_PAD_EIM_CS5, 0x488, 0x0f4, 2, 0x000, 0), /* MX51_PAD_EIM_CS5__USBOTG_DIR */
+       IMX_PIN_REG(MX51_PAD_EIM_DTACK, 0x48c, 0x0f8, 0, 0x000, 0), /* MX51_PAD_EIM_DTACK__EIM_DTACK */
+       IMX_PIN_REG(MX51_PAD_EIM_DTACK, 0x48c, 0x0f8, 1, 0x000, 0), /* MX51_PAD_EIM_DTACK__GPIO2_31 */
+       IMX_PIN_REG(MX51_PAD_EIM_LBA, 0x494, 0x0fc, 0, 0x000, 0), /* MX51_PAD_EIM_LBA__EIM_LBA */
+       IMX_PIN_REG(MX51_PAD_EIM_LBA, 0x494, 0x0fc, 1, 0x978, 0), /* MX51_PAD_EIM_LBA__GPIO3_1 */
+       IMX_PIN_REG(MX51_PAD_EIM_CRE, 0x4a0, 0x100, 0, 0x000, 0), /* MX51_PAD_EIM_CRE__EIM_CRE */
+       IMX_PIN_REG(MX51_PAD_EIM_CRE, 0x4a0, 0x100, 1, 0x97c, 0), /* MX51_PAD_EIM_CRE__GPIO3_2 */
+       IMX_PIN_REG(MX51_PAD_DRAM_CS1, 0x4d0, 0x104, 0, 0x000, 0), /* MX51_PAD_DRAM_CS1__DRAM_CS1 */
+       IMX_PIN_REG(MX51_PAD_NANDF_WE_B, 0x4e4, 0x108, 3, 0x980, 0), /* MX51_PAD_NANDF_WE_B__GPIO3_3 */
+       IMX_PIN_REG(MX51_PAD_NANDF_WE_B, 0x4e4, 0x108, 0, 0x000, 0), /* MX51_PAD_NANDF_WE_B__NANDF_WE_B */
+       IMX_PIN_REG(MX51_PAD_NANDF_WE_B, 0x4e4, 0x108, 1, 0x000, 0), /* MX51_PAD_NANDF_WE_B__PATA_DIOW */
+       IMX_PIN_REG(MX51_PAD_NANDF_WE_B, 0x4e4, 0x108, 2, 0x93c, 0), /* MX51_PAD_NANDF_WE_B__SD3_DATA0 */
+       IMX_PIN_REG(MX51_PAD_NANDF_RE_B, 0x4e8, 0x10c, 3, 0x984, 0), /* MX51_PAD_NANDF_RE_B__GPIO3_4 */
+       IMX_PIN_REG(MX51_PAD_NANDF_RE_B, 0x4e8, 0x10c, 0, 0x000, 0), /* MX51_PAD_NANDF_RE_B__NANDF_RE_B */
+       IMX_PIN_REG(MX51_PAD_NANDF_RE_B, 0x4e8, 0x10c, 1, 0x000, 0), /* MX51_PAD_NANDF_RE_B__PATA_DIOR */
+       IMX_PIN_REG(MX51_PAD_NANDF_RE_B, 0x4e8, 0x10c, 2, 0x940, 0), /* MX51_PAD_NANDF_RE_B__SD3_DATA1 */
+       IMX_PIN_REG(MX51_PAD_NANDF_ALE, 0x4ec, 0x110, 3, 0x988, 0), /* MX51_PAD_NANDF_ALE__GPIO3_5 */
+       IMX_PIN_REG(MX51_PAD_NANDF_ALE, 0x4ec, 0x110, 0, 0x000, 0), /* MX51_PAD_NANDF_ALE__NANDF_ALE */
+       IMX_PIN_REG(MX51_PAD_NANDF_ALE, 0x4ec, 0x110, 1, 0x000, 0), /* MX51_PAD_NANDF_ALE__PATA_BUFFER_EN */
+       IMX_PIN_REG(MX51_PAD_NANDF_CLE, 0x4f0, 0x114, 3, 0x98c, 0), /* MX51_PAD_NANDF_CLE__GPIO3_6 */
+       IMX_PIN_REG(MX51_PAD_NANDF_CLE, 0x4f0, 0x114, 0, 0x000, 0), /* MX51_PAD_NANDF_CLE__NANDF_CLE */
+       IMX_PIN_REG(MX51_PAD_NANDF_CLE, 0x4f0, 0x114, 1, 0x000, 0), /* MX51_PAD_NANDF_CLE__PATA_RESET_B */
+       IMX_PIN_REG(MX51_PAD_NANDF_WP_B, 0x4f4, 0x118, 3, 0x990, 0), /* MX51_PAD_NANDF_WP_B__GPIO3_7 */
+       IMX_PIN_REG(MX51_PAD_NANDF_WP_B, 0x4f4, 0x118, 0, 0x000, 0), /* MX51_PAD_NANDF_WP_B__NANDF_WP_B */
+       IMX_PIN_REG(MX51_PAD_NANDF_WP_B, 0x4f4, 0x118, 1, 0x000, 0), /* MX51_PAD_NANDF_WP_B__PATA_DMACK */
+       IMX_PIN_REG(MX51_PAD_NANDF_WP_B, 0x4f4, 0x118, 2, 0x944, 0), /* MX51_PAD_NANDF_WP_B__SD3_DATA2 */
+       IMX_PIN_REG(MX51_PAD_NANDF_RB0, 0x4f8, 0x11c, 5, 0x930, 0), /* MX51_PAD_NANDF_RB0__ECSPI2_SS1 */
+       IMX_PIN_REG(MX51_PAD_NANDF_RB0, 0x4f8, 0x11c, 3, 0x994, 0), /* MX51_PAD_NANDF_RB0__GPIO3_8 */
+       IMX_PIN_REG(MX51_PAD_NANDF_RB0, 0x4f8, 0x11c, 0, 0x000, 0), /* MX51_PAD_NANDF_RB0__NANDF_RB0 */
+       IMX_PIN_REG(MX51_PAD_NANDF_RB0, 0x4f8, 0x11c, 1, 0x000, 0), /* MX51_PAD_NANDF_RB0__PATA_DMARQ */
+       IMX_PIN_REG(MX51_PAD_NANDF_RB0, 0x4f8, 0x11c, 2, 0x948, 0), /* MX51_PAD_NANDF_RB0__SD3_DATA3 */
+       IMX_PIN_REG(MX51_PAD_NANDF_RB1, 0x4fc, 0x120, 6, 0x91c, 0), /* MX51_PAD_NANDF_RB1__CSPI_MOSI */
+       IMX_PIN_REG(MX51_PAD_NANDF_RB1, 0x4fc, 0x120, 2, 0x000, 0), /* MX51_PAD_NANDF_RB1__ECSPI2_RDY */
+       IMX_PIN_REG(MX51_PAD_NANDF_RB1, 0x4fc, 0x120, 3, 0x000, 0), /* MX51_PAD_NANDF_RB1__GPIO3_9 */
+       IMX_PIN_REG(MX51_PAD_NANDF_RB1, 0x4fc, 0x120, 0, 0x000, 0), /* MX51_PAD_NANDF_RB1__NANDF_RB1 */
+       IMX_PIN_REG(MX51_PAD_NANDF_RB1, 0x4fc, 0x120, 1, 0x000, 0), /* MX51_PAD_NANDF_RB1__PATA_IORDY */
+       IMX_PIN_REG(MX51_PAD_NANDF_RB1, 0x4fc, 0x120, 5, 0x000, 0), /* MX51_PAD_NANDF_RB1__SD4_CMD */
+       IMX_PIN_REG(MX51_PAD_NANDF_RB2, 0x500, 0x124, 5, 0x9a8, 0), /* MX51_PAD_NANDF_RB2__DISP2_WAIT */
+       IMX_PIN_REG(MX51_PAD_NANDF_RB2, 0x500, 0x124, 2, 0x000, 0), /* MX51_PAD_NANDF_RB2__ECSPI2_SCLK */
+       IMX_PIN_REG(MX51_PAD_NANDF_RB2, 0x500, 0x124, 1, 0x94c, 0), /* MX51_PAD_NANDF_RB2__FEC_COL */
+       IMX_PIN_REG(MX51_PAD_NANDF_RB2, 0x500, 0x124, 3, 0x000, 0), /* MX51_PAD_NANDF_RB2__GPIO3_10 */
+       IMX_PIN_REG(MX51_PAD_NANDF_RB2, 0x500, 0x124, 0, 0x000, 0), /* MX51_PAD_NANDF_RB2__NANDF_RB2 */
+       IMX_PIN_REG(MX51_PAD_NANDF_RB2, 0x500, 0x124, 7, 0x000, 0), /* MX51_PAD_NANDF_RB2__USBH3_H3_DP */
+       IMX_PIN_REG(MX51_PAD_NANDF_RB2, 0x500, 0x124, 6, 0xa20, 0), /* MX51_PAD_NANDF_RB2__USBH3_NXT */
+       IMX_PIN_REG(MX51_PAD_NANDF_RB3, 0x504, 0x128, 5, 0x000, 0), /* MX51_PAD_NANDF_RB3__DISP1_WAIT */
+       IMX_PIN_REG(MX51_PAD_NANDF_RB3, 0x504, 0x128, 2, 0x000, 0), /* MX51_PAD_NANDF_RB3__ECSPI2_MISO */
+       IMX_PIN_REG(MX51_PAD_NANDF_RB3, 0x504, 0x128, 1, 0x968, 0), /* MX51_PAD_NANDF_RB3__FEC_RX_CLK */
+       IMX_PIN_REG(MX51_PAD_NANDF_RB3, 0x504, 0x128, 3, 0x000, 0), /* MX51_PAD_NANDF_RB3__GPIO3_11 */
+       IMX_PIN_REG(MX51_PAD_NANDF_RB3, 0x504, 0x128, 0, 0x000, 0), /* MX51_PAD_NANDF_RB3__NANDF_RB3 */
+       IMX_PIN_REG(MX51_PAD_NANDF_RB3, 0x504, 0x128, 6, 0x9f8, 0), /* MX51_PAD_NANDF_RB3__USBH3_CLK */
+       IMX_PIN_REG(MX51_PAD_NANDF_RB3, 0x504, 0x128, 7, 0x000, 0), /* MX51_PAD_NANDF_RB3__USBH3_H3_DM */
+       IMX_PIN_REG(MX51_PAD_GPIO_NAND, 0x514, 0x12c, 0, 0x998, 0), /* MX51_PAD_GPIO_NAND__GPIO_NAND */
+       IMX_PIN_REG(MX51_PAD_GPIO_NAND, 0x514, 0x12c, 1, 0x000, 0), /* MX51_PAD_GPIO_NAND__PATA_INTRQ */
+       IMX_PIN_REG(MX51_PAD_NANDF_CS0, 0x518, 0x130, 3, 0x000, 0), /* MX51_PAD_NANDF_CS0__GPIO3_16 */
+       IMX_PIN_REG(MX51_PAD_NANDF_CS0, 0x518, 0x130, 0, 0x000, 0), /* MX51_PAD_NANDF_CS0__NANDF_CS0 */
+       IMX_PIN_REG(MX51_PAD_NANDF_CS1, 0x51c, 0x134, 3, 0x000, 0), /* MX51_PAD_NANDF_CS1__GPIO3_17 */
+       IMX_PIN_REG(MX51_PAD_NANDF_CS1, 0x51c, 0x134, 0, 0x000, 0), /* MX51_PAD_NANDF_CS1__NANDF_CS1 */
+       IMX_PIN_REG(MX51_PAD_NANDF_CS2, 0x520, 0x138, 6, 0x914, 0), /* MX51_PAD_NANDF_CS2__CSPI_SCLK */
+       IMX_PIN_REG(MX51_PAD_NANDF_CS2, 0x520, 0x138, 2, 0x000, 0), /* MX51_PAD_NANDF_CS2__FEC_TX_ER */
+       IMX_PIN_REG(MX51_PAD_NANDF_CS2, 0x520, 0x138, 3, 0x000, 0), /* MX51_PAD_NANDF_CS2__GPIO3_18 */
+       IMX_PIN_REG(MX51_PAD_NANDF_CS2, 0x520, 0x138, 0, 0x000, 0), /* MX51_PAD_NANDF_CS2__NANDF_CS2 */
+       IMX_PIN_REG(MX51_PAD_NANDF_CS2, 0x520, 0x138, 1, 0x000, 0), /* MX51_PAD_NANDF_CS2__PATA_CS_0 */
+       IMX_PIN_REG(MX51_PAD_NANDF_CS2, 0x520, 0x138, 5, 0x000, 0), /* MX51_PAD_NANDF_CS2__SD4_CLK */
+       IMX_PIN_REG(MX51_PAD_NANDF_CS2, 0x520, 0x138, 7, 0x000, 0), /* MX51_PAD_NANDF_CS2__USBH3_H1_DP */
+       IMX_PIN_REG(MX51_PAD_NANDF_CS3, 0x524, 0x13c, 2, 0x000, 0), /* MX51_PAD_NANDF_CS3__FEC_MDC */
+       IMX_PIN_REG(MX51_PAD_NANDF_CS3, 0x524, 0x13c, 3, 0x000, 0), /* MX51_PAD_NANDF_CS3__GPIO3_19 */
+       IMX_PIN_REG(MX51_PAD_NANDF_CS3, 0x524, 0x13c, 0, 0x000, 0), /* MX51_PAD_NANDF_CS3__NANDF_CS3 */
+       IMX_PIN_REG(MX51_PAD_NANDF_CS3, 0x524, 0x13c, 1, 0x000, 0), /* MX51_PAD_NANDF_CS3__PATA_CS_1 */
+       IMX_PIN_REG(MX51_PAD_NANDF_CS3, 0x524, 0x13c, 5, 0x000, 0), /* MX51_PAD_NANDF_CS3__SD4_DAT0 */
+       IMX_PIN_REG(MX51_PAD_NANDF_CS3, 0x524, 0x13c, 7, 0x000, 0), /* MX51_PAD_NANDF_CS3__USBH3_H1_DM */
+       IMX_PIN_REG(MX51_PAD_NANDF_CS4, 0x528, 0x140, 2, 0x000, 0), /* MX51_PAD_NANDF_CS4__FEC_TDATA1 */
+       IMX_PIN_REG(MX51_PAD_NANDF_CS4, 0x528, 0x140, 3, 0x000, 0), /* MX51_PAD_NANDF_CS4__GPIO3_20 */
+       IMX_PIN_REG(MX51_PAD_NANDF_CS4, 0x528, 0x140, 0, 0x000, 0), /* MX51_PAD_NANDF_CS4__NANDF_CS4 */
+       IMX_PIN_REG(MX51_PAD_NANDF_CS4, 0x528, 0x140, 1, 0x000, 0), /* MX51_PAD_NANDF_CS4__PATA_DA_0 */
+       IMX_PIN_REG(MX51_PAD_NANDF_CS4, 0x528, 0x140, 5, 0x000, 0), /* MX51_PAD_NANDF_CS4__SD4_DAT1 */
+       IMX_PIN_REG(MX51_PAD_NANDF_CS4, 0x528, 0x140, 7, 0xa24, 0), /* MX51_PAD_NANDF_CS4__USBH3_STP */
+       IMX_PIN_REG(MX51_PAD_NANDF_CS5, 0x52c, 0x144, 2, 0x000, 0), /* MX51_PAD_NANDF_CS5__FEC_TDATA2 */
+       IMX_PIN_REG(MX51_PAD_NANDF_CS5, 0x52c, 0x144, 3, 0x000, 0), /* MX51_PAD_NANDF_CS5__GPIO3_21 */
+       IMX_PIN_REG(MX51_PAD_NANDF_CS5, 0x52c, 0x144, 0, 0x000, 0), /* MX51_PAD_NANDF_CS5__NANDF_CS5 */
+       IMX_PIN_REG(MX51_PAD_NANDF_CS5, 0x52c, 0x144, 1, 0x000, 0), /* MX51_PAD_NANDF_CS5__PATA_DA_1 */
+       IMX_PIN_REG(MX51_PAD_NANDF_CS5, 0x52c, 0x144, 5, 0x000, 0), /* MX51_PAD_NANDF_CS5__SD4_DAT2 */
+       IMX_PIN_REG(MX51_PAD_NANDF_CS5, 0x52c, 0x144, 7, 0xa1c, 0), /* MX51_PAD_NANDF_CS5__USBH3_DIR */
+       IMX_PIN_REG(MX51_PAD_NANDF_CS6, 0x530, 0x148, 7, 0x928, 0), /* MX51_PAD_NANDF_CS6__CSPI_SS3 */
+       IMX_PIN_REG(MX51_PAD_NANDF_CS6, 0x530, 0x148, 2, 0x000, 0), /* MX51_PAD_NANDF_CS6__FEC_TDATA3 */
+       IMX_PIN_REG(MX51_PAD_NANDF_CS6, 0x530, 0x148, 3, 0x000, 0), /* MX51_PAD_NANDF_CS6__GPIO3_22 */
+       IMX_PIN_REG(MX51_PAD_NANDF_CS6, 0x530, 0x148, 0, 0x000, 0), /* MX51_PAD_NANDF_CS6__NANDF_CS6 */
+       IMX_PIN_REG(MX51_PAD_NANDF_CS6, 0x530, 0x148, 1, 0x000, 0), /* MX51_PAD_NANDF_CS6__PATA_DA_2 */
+       IMX_PIN_REG(MX51_PAD_NANDF_CS6, 0x530, 0x148, 5, 0x000, 0), /* MX51_PAD_NANDF_CS6__SD4_DAT3 */
+       IMX_PIN_REG(MX51_PAD_NANDF_CS7, 0x534, 0x14c, 1, 0x000, 0), /* MX51_PAD_NANDF_CS7__FEC_TX_EN */
+       IMX_PIN_REG(MX51_PAD_NANDF_CS7, 0x534, 0x14c, 3, 0x000, 0), /* MX51_PAD_NANDF_CS7__GPIO3_23 */
+       IMX_PIN_REG(MX51_PAD_NANDF_CS7, 0x534, 0x14c, 0, 0x000, 0), /* MX51_PAD_NANDF_CS7__NANDF_CS7 */
+       IMX_PIN_REG(MX51_PAD_NANDF_CS7, 0x534, 0x14c, 5, 0x000, 0), /* MX51_PAD_NANDF_CS7__SD3_CLK */
+       IMX_PIN_REG(MX51_PAD_NANDF_RDY_INT, 0x538, 0x150, 2, 0x000, 0), /* MX51_PAD_NANDF_RDY_INT__ECSPI2_SS0 */
+       IMX_PIN_REG(MX51_PAD_NANDF_RDY_INT, 0x538, 0x150, 1, 0x974, 0), /* MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK */
+       IMX_PIN_REG(MX51_PAD_NANDF_RDY_INT, 0x538, 0x150, 3, 0x000, 0), /* MX51_PAD_NANDF_RDY_INT__GPIO3_24 */
+       IMX_PIN_REG(MX51_PAD_NANDF_RDY_INT, 0x538, 0x150, 0, 0x938, 0), /* MX51_PAD_NANDF_RDY_INT__NANDF_RDY_INT */
+       IMX_PIN_REG(MX51_PAD_NANDF_RDY_INT, 0x538, 0x150, 5, 0x000, 0), /* MX51_PAD_NANDF_RDY_INT__SD3_CMD */
+       IMX_PIN_REG(MX51_PAD_NANDF_D15, 0x53c, 0x154, 2, 0x000, 0), /* MX51_PAD_NANDF_D15__ECSPI2_MOSI */
+       IMX_PIN_REG(MX51_PAD_NANDF_D15, 0x53c, 0x154, 3, 0x000, 0), /* MX51_PAD_NANDF_D15__GPIO3_25 */
+       IMX_PIN_REG(MX51_PAD_NANDF_D15, 0x53c, 0x154, 0, 0x000, 0), /* MX51_PAD_NANDF_D15__NANDF_D15 */
+       IMX_PIN_REG(MX51_PAD_NANDF_D15, 0x53c, 0x154, 1, 0x000, 0), /* MX51_PAD_NANDF_D15__PATA_DATA15 */
+       IMX_PIN_REG(MX51_PAD_NANDF_D15, 0x53c, 0x154, 5, 0x000, 0), /* MX51_PAD_NANDF_D15__SD3_DAT7 */
+       IMX_PIN_REG(MX51_PAD_NANDF_D14, 0x540, 0x158, 2, 0x934, 0), /* MX51_PAD_NANDF_D14__ECSPI2_SS3 */
+       IMX_PIN_REG(MX51_PAD_NANDF_D14, 0x540, 0x158, 3, 0x000, 0), /* MX51_PAD_NANDF_D14__GPIO3_26 */
+       IMX_PIN_REG(MX51_PAD_NANDF_D14, 0x540, 0x158, 0, 0x000, 0), /* MX51_PAD_NANDF_D14__NANDF_D14 */
+       IMX_PIN_REG(MX51_PAD_NANDF_D14, 0x540, 0x158, 1, 0x000, 0), /* MX51_PAD_NANDF_D14__PATA_DATA14 */
+       IMX_PIN_REG(MX51_PAD_NANDF_D14, 0x540, 0x158, 5, 0x000, 0), /* MX51_PAD_NANDF_D14__SD3_DAT6 */
+       IMX_PIN_REG(MX51_PAD_NANDF_D13, 0x544, 0x15c, 2, 0x000, 0), /* MX51_PAD_NANDF_D13__ECSPI2_SS2 */
+       IMX_PIN_REG(MX51_PAD_NANDF_D13, 0x544, 0x15c, 3, 0x000, 0), /* MX51_PAD_NANDF_D13__GPIO3_27 */
+       IMX_PIN_REG(MX51_PAD_NANDF_D13, 0x544, 0x15c, 0, 0x000, 0), /* MX51_PAD_NANDF_D13__NANDF_D13 */
+       IMX_PIN_REG(MX51_PAD_NANDF_D13, 0x544, 0x15c, 1, 0x000, 0), /* MX51_PAD_NANDF_D13__PATA_DATA13 */
+       IMX_PIN_REG(MX51_PAD_NANDF_D13, 0x544, 0x15c, 5, 0x000, 0), /* MX51_PAD_NANDF_D13__SD3_DAT5 */
+       IMX_PIN_REG(MX51_PAD_NANDF_D12, 0x548, 0x160, 2, 0x930, 1), /* MX51_PAD_NANDF_D12__ECSPI2_SS1 */
+       IMX_PIN_REG(MX51_PAD_NANDF_D12, 0x548, 0x160, 3, 0x000, 0), /* MX51_PAD_NANDF_D12__GPIO3_28 */
+       IMX_PIN_REG(MX51_PAD_NANDF_D12, 0x548, 0x160, 0, 0x000, 0), /* MX51_PAD_NANDF_D12__NANDF_D12 */
+       IMX_PIN_REG(MX51_PAD_NANDF_D12, 0x548, 0x160, 1, 0x000, 0), /* MX51_PAD_NANDF_D12__PATA_DATA12 */
+       IMX_PIN_REG(MX51_PAD_NANDF_D12, 0x548, 0x160, 5, 0x000, 0), /* MX51_PAD_NANDF_D12__SD3_DAT4 */
+       IMX_PIN_REG(MX51_PAD_NANDF_D11, 0x54c, 0x164, 2, 0x96c, 0), /* MX51_PAD_NANDF_D11__FEC_RX_DV */
+       IMX_PIN_REG(MX51_PAD_NANDF_D11, 0x54c, 0x164, 3, 0x000, 0), /* MX51_PAD_NANDF_D11__GPIO3_29 */
+       IMX_PIN_REG(MX51_PAD_NANDF_D11, 0x54c, 0x164, 0, 0x000, 0), /* MX51_PAD_NANDF_D11__NANDF_D11 */
+       IMX_PIN_REG(MX51_PAD_NANDF_D11, 0x54c, 0x164, 1, 0x000, 0), /* MX51_PAD_NANDF_D11__PATA_DATA11 */
+       IMX_PIN_REG(MX51_PAD_NANDF_D11, 0x54c, 0x164, 5, 0x948, 1), /* MX51_PAD_NANDF_D11__SD3_DATA3 */
+       IMX_PIN_REG(MX51_PAD_NANDF_D10, 0x550, 0x168, 3, 0x000, 0), /* MX51_PAD_NANDF_D10__GPIO3_30 */
+       IMX_PIN_REG(MX51_PAD_NANDF_D10, 0x550, 0x168, 0, 0x000, 0), /* MX51_PAD_NANDF_D10__NANDF_D10 */
+       IMX_PIN_REG(MX51_PAD_NANDF_D10, 0x550, 0x168, 1, 0x000, 0), /* MX51_PAD_NANDF_D10__PATA_DATA10 */
+       IMX_PIN_REG(MX51_PAD_NANDF_D10, 0x550, 0x168, 5, 0x944, 1), /* MX51_PAD_NANDF_D10__SD3_DATA2 */
+       IMX_PIN_REG(MX51_PAD_NANDF_D9, 0x554, 0x16c, 2, 0x958, 0), /* MX51_PAD_NANDF_D9__FEC_RDATA0 */
+       IMX_PIN_REG(MX51_PAD_NANDF_D9, 0x554, 0x16c, 3, 0x000, 0), /* MX51_PAD_NANDF_D9__GPIO3_31 */
+       IMX_PIN_REG(MX51_PAD_NANDF_D9, 0x554, 0x16c, 0, 0x000, 0), /* MX51_PAD_NANDF_D9__NANDF_D9 */
+       IMX_PIN_REG(MX51_PAD_NANDF_D9, 0x554, 0x16c, 1, 0x000, 0), /* MX51_PAD_NANDF_D9__PATA_DATA9 */
+       IMX_PIN_REG(MX51_PAD_NANDF_D9, 0x554, 0x16c, 5, 0x940, 1), /* MX51_PAD_NANDF_D9__SD3_DATA1 */
+       IMX_PIN_REG(MX51_PAD_NANDF_D8, 0x558, 0x170, 2, 0x000, 0), /* MX51_PAD_NANDF_D8__FEC_TDATA0 */
+       IMX_PIN_REG(MX51_PAD_NANDF_D8, 0x558, 0x170, 3, 0x000, 0), /* MX51_PAD_NANDF_D8__GPIO4_0 */
+       IMX_PIN_REG(MX51_PAD_NANDF_D8, 0x558, 0x170, 0, 0x000, 0), /* MX51_PAD_NANDF_D8__NANDF_D8 */
+       IMX_PIN_REG(MX51_PAD_NANDF_D8, 0x558, 0x170, 1, 0x000, 0), /* MX51_PAD_NANDF_D8__PATA_DATA8 */
+       IMX_PIN_REG(MX51_PAD_NANDF_D8, 0x558, 0x170, 5, 0x93c, 1), /* MX51_PAD_NANDF_D8__SD3_DATA0 */
+       IMX_PIN_REG(MX51_PAD_NANDF_D7, 0x55c, 0x174, 3, 0x000, 0), /* MX51_PAD_NANDF_D7__GPIO4_1 */
+       IMX_PIN_REG(MX51_PAD_NANDF_D7, 0x55c, 0x174, 0, 0x000, 0), /* MX51_PAD_NANDF_D7__NANDF_D7 */
+       IMX_PIN_REG(MX51_PAD_NANDF_D7, 0x55c, 0x174, 1, 0x000, 0), /* MX51_PAD_NANDF_D7__PATA_DATA7 */
+       IMX_PIN_REG(MX51_PAD_NANDF_D7, 0x55c, 0x174, 5, 0x9fc, 0), /* MX51_PAD_NANDF_D7__USBH3_DATA0 */
+       IMX_PIN_REG(MX51_PAD_NANDF_D6, 0x560, 0x178, 3, 0x000, 0), /* MX51_PAD_NANDF_D6__GPIO4_2 */
+       IMX_PIN_REG(MX51_PAD_NANDF_D6, 0x560, 0x178, 0, 0x000, 0), /* MX51_PAD_NANDF_D6__NANDF_D6 */
+       IMX_PIN_REG(MX51_PAD_NANDF_D6, 0x560, 0x178, 1, 0x000, 0), /* MX51_PAD_NANDF_D6__PATA_DATA6 */
+       IMX_PIN_REG(MX51_PAD_NANDF_D6, 0x560, 0x178, 2, 0x000, 0), /* MX51_PAD_NANDF_D6__SD4_LCTL */
+       IMX_PIN_REG(MX51_PAD_NANDF_D6, 0x560, 0x178, 5, 0xa00, 0), /* MX51_PAD_NANDF_D6__USBH3_DATA1 */
+       IMX_PIN_REG(MX51_PAD_NANDF_D5, 0x564, 0x17c, 3, 0x000, 0), /* MX51_PAD_NANDF_D5__GPIO4_3 */
+       IMX_PIN_REG(MX51_PAD_NANDF_D5, 0x564, 0x17c, 0, 0x000, 0), /* MX51_PAD_NANDF_D5__NANDF_D5 */
+       IMX_PIN_REG(MX51_PAD_NANDF_D5, 0x564, 0x17c, 1, 0x000, 0), /* MX51_PAD_NANDF_D5__PATA_DATA5 */
+       IMX_PIN_REG(MX51_PAD_NANDF_D5, 0x564, 0x17c, 2, 0x000, 0), /* MX51_PAD_NANDF_D5__SD4_WP */
+       IMX_PIN_REG(MX51_PAD_NANDF_D5, 0x564, 0x17c, 5, 0xa04, 0), /* MX51_PAD_NANDF_D5__USBH3_DATA2 */
+       IMX_PIN_REG(MX51_PAD_NANDF_D4, 0x568, 0x180, 3, 0x000, 0), /* MX51_PAD_NANDF_D4__GPIO4_4 */
+       IMX_PIN_REG(MX51_PAD_NANDF_D4, 0x568, 0x180, 0, 0x000, 0), /* MX51_PAD_NANDF_D4__NANDF_D4 */
+       IMX_PIN_REG(MX51_PAD_NANDF_D4, 0x568, 0x180, 1, 0x000, 0), /* MX51_PAD_NANDF_D4__PATA_DATA4 */
+       IMX_PIN_REG(MX51_PAD_NANDF_D4, 0x568, 0x180, 2, 0x000, 0), /* MX51_PAD_NANDF_D4__SD4_CD */
+       IMX_PIN_REG(MX51_PAD_NANDF_D4, 0x568, 0x180, 5, 0xa08, 0), /* MX51_PAD_NANDF_D4__USBH3_DATA3 */
+       IMX_PIN_REG(MX51_PAD_NANDF_D3, 0x56c, 0x184, 3, 0x000, 0), /* MX51_PAD_NANDF_D3__GPIO4_5 */
+       IMX_PIN_REG(MX51_PAD_NANDF_D3, 0x56c, 0x184, 0, 0x000, 0), /* MX51_PAD_NANDF_D3__NANDF_D3 */
+       IMX_PIN_REG(MX51_PAD_NANDF_D3, 0x56c, 0x184, 1, 0x000, 0), /* MX51_PAD_NANDF_D3__PATA_DATA3 */
+       IMX_PIN_REG(MX51_PAD_NANDF_D3, 0x56c, 0x184, 2, 0x000, 0), /* MX51_PAD_NANDF_D3__SD4_DAT4 */
+       IMX_PIN_REG(MX51_PAD_NANDF_D3, 0x56c, 0x184, 5, 0xa0c, 0), /* MX51_PAD_NANDF_D3__USBH3_DATA4 */
+       IMX_PIN_REG(MX51_PAD_NANDF_D2, 0x570, 0x188, 3, 0x000, 0), /* MX51_PAD_NANDF_D2__GPIO4_6 */
+       IMX_PIN_REG(MX51_PAD_NANDF_D2, 0x570, 0x188, 0, 0x000, 0), /* MX51_PAD_NANDF_D2__NANDF_D2 */
+       IMX_PIN_REG(MX51_PAD_NANDF_D2, 0x570, 0x188, 1, 0x000, 0), /* MX51_PAD_NANDF_D2__PATA_DATA2 */
+       IMX_PIN_REG(MX51_PAD_NANDF_D2, 0x570, 0x188, 2, 0x000, 0), /* MX51_PAD_NANDF_D2__SD4_DAT5 */
+       IMX_PIN_REG(MX51_PAD_NANDF_D2, 0x570, 0x188, 5, 0xa10, 0), /* MX51_PAD_NANDF_D2__USBH3_DATA5 */
+       IMX_PIN_REG(MX51_PAD_NANDF_D1, 0x574, 0x18c, 3, 0x000, 0), /* MX51_PAD_NANDF_D1__GPIO4_7 */
+       IMX_PIN_REG(MX51_PAD_NANDF_D1, 0x574, 0x18c, 0, 0x000, 0), /* MX51_PAD_NANDF_D1__NANDF_D1 */
+       IMX_PIN_REG(MX51_PAD_NANDF_D1, 0x574, 0x18c, 1, 0x000, 0), /* MX51_PAD_NANDF_D1__PATA_DATA1 */
+       IMX_PIN_REG(MX51_PAD_NANDF_D1, 0x574, 0x18c, 2, 0x000, 0), /* MX51_PAD_NANDF_D1__SD4_DAT6 */
+       IMX_PIN_REG(MX51_PAD_NANDF_D1, 0x574, 0x18c, 5, 0xa14, 0), /* MX51_PAD_NANDF_D1__USBH3_DATA6 */
+       IMX_PIN_REG(MX51_PAD_NANDF_D0, 0x578, 0x190, 3, 0x000, 0), /* MX51_PAD_NANDF_D0__GPIO4_8 */
+       IMX_PIN_REG(MX51_PAD_NANDF_D0, 0x578, 0x190, 0, 0x000, 0), /* MX51_PAD_NANDF_D0__NANDF_D0 */
+       IMX_PIN_REG(MX51_PAD_NANDF_D0, 0x578, 0x190, 1, 0x000, 0), /* MX51_PAD_NANDF_D0__PATA_DATA0 */
+       IMX_PIN_REG(MX51_PAD_NANDF_D0, 0x578, 0x190, 2, 0x000, 0), /* MX51_PAD_NANDF_D0__SD4_DAT7 */
+       IMX_PIN_REG(MX51_PAD_NANDF_D0, 0x578, 0x190, 5, 0xa18, 0), /* MX51_PAD_NANDF_D0__USBH3_DATA7 */
+       IMX_PIN_REG(MX51_PAD_CSI1_D8, 0x57c, 0x194, 0, 0x000, 0), /* MX51_PAD_CSI1_D8__CSI1_D8 */
+       IMX_PIN_REG(MX51_PAD_CSI1_D8, 0x57c, 0x194, 3, 0x998, 1), /* MX51_PAD_CSI1_D8__GPIO3_12 */
+       IMX_PIN_REG(MX51_PAD_CSI1_D9, 0x580, 0x198, 0, 0x000, 0), /* MX51_PAD_CSI1_D9__CSI1_D9 */
+       IMX_PIN_REG(MX51_PAD_CSI1_D9, 0x580, 0x198, 3, 0x000, 0), /* MX51_PAD_CSI1_D9__GPIO3_13 */
+       IMX_PIN_REG(MX51_PAD_CSI1_D10, 0x584, 0x19c, 0, 0x000, 0), /* MX51_PAD_CSI1_D10__CSI1_D10 */
+       IMX_PIN_REG(MX51_PAD_CSI1_D11, 0x588, 0x1a0, 0, 0x000, 0), /* MX51_PAD_CSI1_D11__CSI1_D11 */
+       IMX_PIN_REG(MX51_PAD_CSI1_D12, 0x58c, 0x1a4, 0, 0x000, 0), /* MX51_PAD_CSI1_D12__CSI1_D12 */
+       IMX_PIN_REG(MX51_PAD_CSI1_D13, 0x590, 0x1a8, 0, 0x000, 0), /* MX51_PAD_CSI1_D13__CSI1_D13 */
+       IMX_PIN_REG(MX51_PAD_CSI1_D14, 0x594, 0x1ac, 0, 0x000, 0), /* MX51_PAD_CSI1_D14__CSI1_D14 */
+       IMX_PIN_REG(MX51_PAD_CSI1_D15, 0x598, 0x1b0, 0, 0x000, 0), /* MX51_PAD_CSI1_D15__CSI1_D15 */
+       IMX_PIN_REG(MX51_PAD_CSI1_D16, 0x59c, 0x1b4, 0, 0x000, 0), /* MX51_PAD_CSI1_D16__CSI1_D16 */
+       IMX_PIN_REG(MX51_PAD_CSI1_D17, 0x5a0, 0x1b8, 0, 0x000, 0), /* MX51_PAD_CSI1_D17__CSI1_D17 */
+       IMX_PIN_REG(MX51_PAD_CSI1_D18, 0x5a4, 0x1bc, 0, 0x000, 0), /* MX51_PAD_CSI1_D18__CSI1_D18 */
+       IMX_PIN_REG(MX51_PAD_CSI1_D19, 0x5a8, 0x1c0, 0, 0x000, 0), /* MX51_PAD_CSI1_D19__CSI1_D19 */
+       IMX_PIN_REG(MX51_PAD_CSI1_VSYNC, 0x5ac, 0x1c4, 0, 0x000, 0), /* MX51_PAD_CSI1_VSYNC__CSI1_VSYNC */
+       IMX_PIN_REG(MX51_PAD_CSI1_VSYNC, 0x5ac, 0x1c4, 3, 0x000, 0), /* MX51_PAD_CSI1_VSYNC__GPIO3_14 */
+       IMX_PIN_REG(MX51_PAD_CSI1_HSYNC, 0x5b0, 0x1c8, 0, 0x000, 0), /* MX51_PAD_CSI1_HSYNC__CSI1_HSYNC */
+       IMX_PIN_REG(MX51_PAD_CSI1_HSYNC, 0x5b0, 0x1c8, 3, 0x000, 0), /* MX51_PAD_CSI1_HSYNC__GPIO3_15 */
+       IMX_PIN_REG(MX51_PAD_CSI1_PIXCLK, 0x5b4, NO_MUX, 0, 0x000, 0), /* MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK */
+       IMX_PIN_REG(MX51_PAD_CSI1_MCLK, 0x5b8, NO_MUX, 0, 0x000, 0), /* MX51_PAD_CSI1_MCLK__CSI1_MCLK */
+       IMX_PIN_REG(MX51_PAD_CSI2_D12, 0x5bc, 0x1cc, 0, 0x000, 0), /* MX51_PAD_CSI2_D12__CSI2_D12 */
+       IMX_PIN_REG(MX51_PAD_CSI2_D12, 0x5bc, 0x1cc, 3, 0x000, 0), /* MX51_PAD_CSI2_D12__GPIO4_9 */
+       IMX_PIN_REG(MX51_PAD_CSI2_D13, 0x5c0, 0x1d0, 0, 0x000, 0), /* MX51_PAD_CSI2_D13__CSI2_D13 */
+       IMX_PIN_REG(MX51_PAD_CSI2_D13, 0x5c0, 0x1d0, 3, 0x000, 0), /* MX51_PAD_CSI2_D13__GPIO4_10 */
+       IMX_PIN_REG(MX51_PAD_CSI2_D14, 0x5c4, 0x1d4, 0, 0x000, 0), /* MX51_PAD_CSI2_D14__CSI2_D14 */
+       IMX_PIN_REG(MX51_PAD_CSI2_D15, 0x5c8, 0x1d8, 0, 0x000, 0), /* MX51_PAD_CSI2_D15__CSI2_D15 */
+       IMX_PIN_REG(MX51_PAD_CSI2_D16, 0x5cc, 0x1dc, 0, 0x000, 0), /* MX51_PAD_CSI2_D16__CSI2_D16 */
+       IMX_PIN_REG(MX51_PAD_CSI2_D17, 0x5d0, 0x1e0, 0, 0x000, 0), /* MX51_PAD_CSI2_D17__CSI2_D17 */
+       IMX_PIN_REG(MX51_PAD_CSI2_D18, 0x5d4, 0x1e4, 0, 0x000, 0), /* MX51_PAD_CSI2_D18__CSI2_D18 */
+       IMX_PIN_REG(MX51_PAD_CSI2_D18, 0x5d4, 0x1e4, 3, 0x000, 0), /* MX51_PAD_CSI2_D18__GPIO4_11 */
+       IMX_PIN_REG(MX51_PAD_CSI2_D19, 0x5d8, 0x1e8, 0, 0x000, 0), /* MX51_PAD_CSI2_D19__CSI2_D19 */
+       IMX_PIN_REG(MX51_PAD_CSI2_D19, 0x5d8, 0x1e8, 3, 0x000, 0), /* MX51_PAD_CSI2_D19__GPIO4_12 */
+       IMX_PIN_REG(MX51_PAD_CSI2_VSYNC, 0x5dc, 0x1ec, 0, 0x000, 0), /* MX51_PAD_CSI2_VSYNC__CSI2_VSYNC */
+       IMX_PIN_REG(MX51_PAD_CSI2_VSYNC, 0x5dc, 0x1ec, 3, 0x000, 0), /* MX51_PAD_CSI2_VSYNC__GPIO4_13 */
+       IMX_PIN_REG(MX51_PAD_CSI2_HSYNC, 0x5e0, 0x1f0, 0, 0x000, 0), /* MX51_PAD_CSI2_HSYNC__CSI2_HSYNC */
+       IMX_PIN_REG(MX51_PAD_CSI2_HSYNC, 0x5e0, 0x1f0, 3, 0x000, 0), /* MX51_PAD_CSI2_HSYNC__GPIO4_14 */
+       IMX_PIN_REG(MX51_PAD_CSI2_PIXCLK, 0x5e4, 0x1f4, 0, 0x000, 0), /* MX51_PAD_CSI2_PIXCLK__CSI2_PIXCLK */
+       IMX_PIN_REG(MX51_PAD_CSI2_PIXCLK, 0x5e4, 0x1f4, 3, 0x000, 0), /* MX51_PAD_CSI2_PIXCLK__GPIO4_15 */
+       IMX_PIN_REG(MX51_PAD_I2C1_CLK, 0x5e8, 0x1f8, 3, 0x000, 0), /* MX51_PAD_I2C1_CLK__GPIO4_16 */
+       IMX_PIN_REG(MX51_PAD_I2C1_CLK, 0x5e8, 0x1f8, 0, 0x000, 0), /* MX51_PAD_I2C1_CLK__I2C1_CLK */
+       IMX_PIN_REG(MX51_PAD_I2C1_DAT, 0x5ec, 0x1fc, 3, 0x000, 0), /* MX51_PAD_I2C1_DAT__GPIO4_17 */
+       IMX_PIN_REG(MX51_PAD_I2C1_DAT, 0x5ec, 0x1fc, 0, 0x000, 0), /* MX51_PAD_I2C1_DAT__I2C1_DAT */
+       IMX_PIN_REG(MX51_PAD_AUD3_BB_TXD, 0x5f0, 0x200, 0, 0x000, 0), /* MX51_PAD_AUD3_BB_TXD__AUD3_TXD */
+       IMX_PIN_REG(MX51_PAD_AUD3_BB_TXD, 0x5f0, 0x200, 3, 0x000, 0), /* MX51_PAD_AUD3_BB_TXD__GPIO4_18 */
+       IMX_PIN_REG(MX51_PAD_AUD3_BB_RXD, 0x5f4, 0x204, 0, 0x000, 0), /* MX51_PAD_AUD3_BB_RXD__AUD3_RXD */
+       IMX_PIN_REG(MX51_PAD_AUD3_BB_RXD, 0x5f4, 0x204, 3, 0x000, 0), /* MX51_PAD_AUD3_BB_RXD__GPIO4_19 */
+       IMX_PIN_REG(MX51_PAD_AUD3_BB_RXD, 0x5f4, 0x204, 1, 0x9f4, 2), /* MX51_PAD_AUD3_BB_RXD__UART3_RXD */
+       IMX_PIN_REG(MX51_PAD_AUD3_BB_CK, 0x5f8, 0x208, 0, 0x000, 0), /* MX51_PAD_AUD3_BB_CK__AUD3_TXC */
+       IMX_PIN_REG(MX51_PAD_AUD3_BB_CK, 0x5f8, 0x208, 3, 0x000, 0), /* MX51_PAD_AUD3_BB_CK__GPIO4_20 */
+       IMX_PIN_REG(MX51_PAD_AUD3_BB_FS, 0x5fc, 0x20c, 0, 0x000, 0), /* MX51_PAD_AUD3_BB_FS__AUD3_TXFS */
+       IMX_PIN_REG(MX51_PAD_AUD3_BB_FS, 0x5fc, 0x20c, 3, 0x000, 0), /* MX51_PAD_AUD3_BB_FS__GPIO4_21 */
+       IMX_PIN_REG(MX51_PAD_AUD3_BB_FS, 0x5fc, 0x20c, 1, 0x000, 0), /* MX51_PAD_AUD3_BB_FS__UART3_TXD */
+       IMX_PIN_REG(MX51_PAD_CSPI1_MOSI, 0x600, 0x210, 0, 0x000, 0), /* MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI */
+       IMX_PIN_REG(MX51_PAD_CSPI1_MOSI, 0x600, 0x210, 3, 0x000, 0), /* MX51_PAD_CSPI1_MOSI__GPIO4_22 */
+       IMX_PIN_REG(MX51_PAD_CSPI1_MOSI, 0x600, 0x210, 1, 0x9b4, 1), /* MX51_PAD_CSPI1_MOSI__I2C1_SDA */
+       IMX_PIN_REG(MX51_PAD_CSPI1_MISO, 0x604, 0x214, 1, 0x8c4, 1), /* MX51_PAD_CSPI1_MISO__AUD4_RXD */
+       IMX_PIN_REG(MX51_PAD_CSPI1_MISO, 0x604, 0x214, 0, 0x000, 0), /* MX51_PAD_CSPI1_MISO__ECSPI1_MISO */
+       IMX_PIN_REG(MX51_PAD_CSPI1_MISO, 0x604, 0x214, 3, 0x000, 0), /* MX51_PAD_CSPI1_MISO__GPIO4_23 */
+       IMX_PIN_REG(MX51_PAD_CSPI1_SS0, 0x608, 0x218, 1, 0x8cc, 1), /* MX51_PAD_CSPI1_SS0__AUD4_TXC */
+       IMX_PIN_REG(MX51_PAD_CSPI1_SS0, 0x608, 0x218, 0, 0x000, 0), /* MX51_PAD_CSPI1_SS0__ECSPI1_SS0 */
+       IMX_PIN_REG(MX51_PAD_CSPI1_SS0, 0x608, 0x218, 3, 0x000, 0), /* MX51_PAD_CSPI1_SS0__GPIO4_24 */
+       IMX_PIN_REG(MX51_PAD_CSPI1_SS1, 0x60c, 0x21c, 1, 0x8c8, 1), /* MX51_PAD_CSPI1_SS1__AUD4_TXD */
+       IMX_PIN_REG(MX51_PAD_CSPI1_SS1, 0x60c, 0x21c, 0, 0x000, 0), /* MX51_PAD_CSPI1_SS1__ECSPI1_SS1 */
+       IMX_PIN_REG(MX51_PAD_CSPI1_SS1, 0x60c, 0x21c, 3, 0x000, 0), /* MX51_PAD_CSPI1_SS1__GPIO4_25 */
+       IMX_PIN_REG(MX51_PAD_CSPI1_RDY, 0x610, 0x220, 1, 0x8d0, 1), /* MX51_PAD_CSPI1_RDY__AUD4_TXFS */
+       IMX_PIN_REG(MX51_PAD_CSPI1_RDY, 0x610, 0x220, 0, 0x000, 0), /* MX51_PAD_CSPI1_RDY__ECSPI1_RDY */
+       IMX_PIN_REG(MX51_PAD_CSPI1_RDY, 0x610, 0x220, 3, 0x000, 0), /* MX51_PAD_CSPI1_RDY__GPIO4_26 */
+       IMX_PIN_REG(MX51_PAD_CSPI1_SCLK, 0x614, 0x224, 0, 0x000, 0), /* MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK */
+       IMX_PIN_REG(MX51_PAD_CSPI1_SCLK, 0x614, 0x224, 3, 0x000, 0), /* MX51_PAD_CSPI1_SCLK__GPIO4_27 */
+       IMX_PIN_REG(MX51_PAD_CSPI1_SCLK, 0x614, 0x224, 1, 0x9b0, 1), /* MX51_PAD_CSPI1_SCLK__I2C1_SCL */
+       IMX_PIN_REG(MX51_PAD_UART1_RXD, 0x618, 0x228, 3, 0x000, 0), /* MX51_PAD_UART1_RXD__GPIO4_28 */
+       IMX_PIN_REG(MX51_PAD_UART1_RXD, 0x618, 0x228, 0, 0x9e4, 0), /* MX51_PAD_UART1_RXD__UART1_RXD */
+       IMX_PIN_REG(MX51_PAD_UART1_TXD, 0x61c, 0x22c, 3, 0x000, 0), /* MX51_PAD_UART1_TXD__GPIO4_29 */
+       IMX_PIN_REG(MX51_PAD_UART1_TXD, 0x61c, 0x22c, 1, 0x000, 0), /* MX51_PAD_UART1_TXD__PWM2_PWMO */
+       IMX_PIN_REG(MX51_PAD_UART1_TXD, 0x61c, 0x22c, 0, 0x000, 0), /* MX51_PAD_UART1_TXD__UART1_TXD */
+       IMX_PIN_REG(MX51_PAD_UART1_RTS, 0x620, 0x230, 3, 0x000, 0), /* MX51_PAD_UART1_RTS__GPIO4_30 */
+       IMX_PIN_REG(MX51_PAD_UART1_RTS, 0x620, 0x230, 0, 0x9e0, 0), /* MX51_PAD_UART1_RTS__UART1_RTS */
+       IMX_PIN_REG(MX51_PAD_UART1_CTS, 0x624, 0x234, 3, 0x000, 0), /* MX51_PAD_UART1_CTS__GPIO4_31 */
+       IMX_PIN_REG(MX51_PAD_UART1_CTS, 0x624, 0x234, 0, 0x000, 0), /* MX51_PAD_UART1_CTS__UART1_CTS */
+       IMX_PIN_REG(MX51_PAD_UART2_RXD, 0x628, 0x238, 1, 0x000, 0), /* MX51_PAD_UART2_RXD__FIRI_TXD */
+       IMX_PIN_REG(MX51_PAD_UART2_RXD, 0x628, 0x238, 3, 0x000, 0), /* MX51_PAD_UART2_RXD__GPIO1_20 */
+       IMX_PIN_REG(MX51_PAD_UART2_RXD, 0x628, 0x238, 0, 0x9ec, 2), /* MX51_PAD_UART2_RXD__UART2_RXD */
+       IMX_PIN_REG(MX51_PAD_UART2_TXD, 0x62c, 0x23c, 1, 0x000, 0), /* MX51_PAD_UART2_TXD__FIRI_RXD */
+       IMX_PIN_REG(MX51_PAD_UART2_TXD, 0x62c, 0x23c, 3, 0x000, 0), /* MX51_PAD_UART2_TXD__GPIO1_21 */
+       IMX_PIN_REG(MX51_PAD_UART2_TXD, 0x62c, 0x23c, 0, 0x000, 0), /* MX51_PAD_UART2_TXD__UART2_TXD */
+       IMX_PIN_REG(MX51_PAD_UART3_RXD, 0x630, 0x240, 2, 0x000, 0), /* MX51_PAD_UART3_RXD__CSI1_D0 */
+       IMX_PIN_REG(MX51_PAD_UART3_RXD, 0x630, 0x240, 3, 0x000, 0), /* MX51_PAD_UART3_RXD__GPIO1_22 */
+       IMX_PIN_REG(MX51_PAD_UART3_RXD, 0x630, 0x240, 0, 0x000, 0), /* MX51_PAD_UART3_RXD__UART1_DTR */
+       IMX_PIN_REG(MX51_PAD_UART3_RXD, 0x630, 0x240, 1, 0x9f4, 4), /* MX51_PAD_UART3_RXD__UART3_RXD */
+       IMX_PIN_REG(MX51_PAD_UART3_TXD, 0x634, 0x244, 2, 0x000, 0), /* MX51_PAD_UART3_TXD__CSI1_D1 */
+       IMX_PIN_REG(MX51_PAD_UART3_TXD, 0x634, 0x244, 3, 0x000, 0), /* MX51_PAD_UART3_TXD__GPIO1_23 */
+       IMX_PIN_REG(MX51_PAD_UART3_TXD, 0x634, 0x244, 0, 0x000, 0), /* MX51_PAD_UART3_TXD__UART1_DSR */
+       IMX_PIN_REG(MX51_PAD_UART3_TXD, 0x634, 0x244, 1, 0x000, 0), /* MX51_PAD_UART3_TXD__UART3_TXD */
+       IMX_PIN_REG(MX51_PAD_OWIRE_LINE, 0x638, 0x248, 3, 0x000, 0), /* MX51_PAD_OWIRE_LINE__GPIO1_24 */
+       IMX_PIN_REG(MX51_PAD_OWIRE_LINE, 0x638, 0x248, 0, 0x000, 0), /* MX51_PAD_OWIRE_LINE__OWIRE_LINE */
+       IMX_PIN_REG(MX51_PAD_OWIRE_LINE, 0x638, 0x248, 6, 0x000, 0), /* MX51_PAD_OWIRE_LINE__SPDIF_OUT */
+       IMX_PIN_REG(MX51_PAD_KEY_ROW0, 0x63c, 0x24c, 0, 0x000, 0), /* MX51_PAD_KEY_ROW0__KEY_ROW0 */
+       IMX_PIN_REG(MX51_PAD_KEY_ROW1, 0x640, 0x250, 0, 0x000, 0), /* MX51_PAD_KEY_ROW1__KEY_ROW1 */
+       IMX_PIN_REG(MX51_PAD_KEY_ROW2, 0x644, 0x254, 0, 0x000, 0), /* MX51_PAD_KEY_ROW2__KEY_ROW2 */
+       IMX_PIN_REG(MX51_PAD_KEY_ROW3, 0x648, 0x258, 0, 0x000, 0), /* MX51_PAD_KEY_ROW3__KEY_ROW3 */
+       IMX_PIN_REG(MX51_PAD_KEY_COL0, 0x64c, 0x25c, 0, 0x000, 0), /* MX51_PAD_KEY_COL0__KEY_COL0 */
+       IMX_PIN_REG(MX51_PAD_KEY_COL0, 0x64c, 0x25c, 7, 0x90c, 0), /* MX51_PAD_KEY_COL0__PLL1_BYP */
+       IMX_PIN_REG(MX51_PAD_KEY_COL1, 0x650, 0x260, 0, 0x000, 0), /* MX51_PAD_KEY_COL1__KEY_COL1 */
+       IMX_PIN_REG(MX51_PAD_KEY_COL1, 0x650, 0x260, 7, 0x910, 0), /* MX51_PAD_KEY_COL1__PLL2_BYP */
+       IMX_PIN_REG(MX51_PAD_KEY_COL2, 0x654, 0x264, 0, 0x000, 0), /* MX51_PAD_KEY_COL2__KEY_COL2 */
+       IMX_PIN_REG(MX51_PAD_KEY_COL2, 0x654, 0x264, 7, 0x000, 0), /* MX51_PAD_KEY_COL2__PLL3_BYP */
+       IMX_PIN_REG(MX51_PAD_KEY_COL3, 0x658, 0x268, 0, 0x000, 0), /* MX51_PAD_KEY_COL3__KEY_COL3 */
+       IMX_PIN_REG(MX51_PAD_KEY_COL4, 0x65c, 0x26c, 3, 0x9b8, 1), /* MX51_PAD_KEY_COL4__I2C2_SCL */
+       IMX_PIN_REG(MX51_PAD_KEY_COL4, 0x65c, 0x26c, 0, 0x000, 0), /* MX51_PAD_KEY_COL4__KEY_COL4 */
+       IMX_PIN_REG(MX51_PAD_KEY_COL4, 0x65c, 0x26c, 6, 0x000, 0), /* MX51_PAD_KEY_COL4__SPDIF_OUT1 */
+       IMX_PIN_REG(MX51_PAD_KEY_COL4, 0x65c, 0x26c, 1, 0x000, 0), /* MX51_PAD_KEY_COL4__UART1_RI */
+       IMX_PIN_REG(MX51_PAD_KEY_COL4, 0x65c, 0x26c, 2, 0x9f0, 4), /* MX51_PAD_KEY_COL4__UART3_RTS */
+       IMX_PIN_REG(MX51_PAD_KEY_COL5, 0x660, 0x270, 3, 0x9bc, 1), /* MX51_PAD_KEY_COL5__I2C2_SDA */
+       IMX_PIN_REG(MX51_PAD_KEY_COL5, 0x660, 0x270, 0, 0x000, 0), /* MX51_PAD_KEY_COL5__KEY_COL5 */
+       IMX_PIN_REG(MX51_PAD_KEY_COL5, 0x660, 0x270, 1, 0x000, 0), /* MX51_PAD_KEY_COL5__UART1_DCD */
+       IMX_PIN_REG(MX51_PAD_KEY_COL5, 0x660, 0x270, 2, 0x000, 0), /* MX51_PAD_KEY_COL5__UART3_CTS */
+       IMX_PIN_REG(MX51_PAD_USBH1_CLK, 0x678, 0x278, 1, 0x914, 1), /* MX51_PAD_USBH1_CLK__CSPI_SCLK */
+       IMX_PIN_REG(MX51_PAD_USBH1_CLK, 0x678, 0x278, 2, 0x000, 0), /* MX51_PAD_USBH1_CLK__GPIO1_25 */
+       IMX_PIN_REG(MX51_PAD_USBH1_CLK, 0x678, 0x278, 5, 0x9b8, 2), /* MX51_PAD_USBH1_CLK__I2C2_SCL */
+       IMX_PIN_REG(MX51_PAD_USBH1_CLK, 0x678, 0x278, 0, 0x000, 0), /* MX51_PAD_USBH1_CLK__USBH1_CLK */
+       IMX_PIN_REG(MX51_PAD_USBH1_DIR, 0x67c, 0x27c, 1, 0x91c, 1), /* MX51_PAD_USBH1_DIR__CSPI_MOSI */
+       IMX_PIN_REG(MX51_PAD_USBH1_DIR, 0x67c, 0x27c, 2, 0x000, 0), /* MX51_PAD_USBH1_DIR__GPIO1_26 */
+       IMX_PIN_REG(MX51_PAD_USBH1_DIR, 0x67c, 0x27c, 5, 0x9bc, 2), /* MX51_PAD_USBH1_DIR__I2C2_SDA */
+       IMX_PIN_REG(MX51_PAD_USBH1_DIR, 0x67c, 0x27c, 0, 0x000, 0), /* MX51_PAD_USBH1_DIR__USBH1_DIR */
+       IMX_PIN_REG(MX51_PAD_USBH1_STP, 0x680, 0x280, 1, 0x000, 0), /* MX51_PAD_USBH1_STP__CSPI_RDY */
+       IMX_PIN_REG(MX51_PAD_USBH1_STP, 0x680, 0x280, 2, 0x000, 0), /* MX51_PAD_USBH1_STP__GPIO1_27 */
+       IMX_PIN_REG(MX51_PAD_USBH1_STP, 0x680, 0x280, 5, 0x9f4, 6), /* MX51_PAD_USBH1_STP__UART3_RXD */
+       IMX_PIN_REG(MX51_PAD_USBH1_STP, 0x680, 0x280, 0, 0x000, 0), /* MX51_PAD_USBH1_STP__USBH1_STP */
+       IMX_PIN_REG(MX51_PAD_USBH1_NXT, 0x684, 0x284, 1, 0x918, 0), /* MX51_PAD_USBH1_NXT__CSPI_MISO */
+       IMX_PIN_REG(MX51_PAD_USBH1_NXT, 0x684, 0x284, 2, 0x000, 0), /* MX51_PAD_USBH1_NXT__GPIO1_28 */
+       IMX_PIN_REG(MX51_PAD_USBH1_NXT, 0x684, 0x284, 5, 0x000, 0), /* MX51_PAD_USBH1_NXT__UART3_TXD */
+       IMX_PIN_REG(MX51_PAD_USBH1_NXT, 0x684, 0x284, 0, 0x000, 0), /* MX51_PAD_USBH1_NXT__USBH1_NXT */
+       IMX_PIN_REG(MX51_PAD_USBH1_DATA0, 0x688, 0x288, 2, 0x000, 0), /* MX51_PAD_USBH1_DATA0__GPIO1_11 */
+       IMX_PIN_REG(MX51_PAD_USBH1_DATA0, 0x688, 0x288, 1, 0x000, 0), /* MX51_PAD_USBH1_DATA0__UART2_CTS */
+       IMX_PIN_REG(MX51_PAD_USBH1_DATA0, 0x688, 0x288, 0, 0x000, 0), /* MX51_PAD_USBH1_DATA0__USBH1_DATA0 */
+       IMX_PIN_REG(MX51_PAD_USBH1_DATA1, 0x68c, 0x28c, 2, 0x000, 0), /* MX51_PAD_USBH1_DATA1__GPIO1_12 */
+       IMX_PIN_REG(MX51_PAD_USBH1_DATA1, 0x68c, 0x28c, 1, 0x9ec, 4), /* MX51_PAD_USBH1_DATA1__UART2_RXD */
+       IMX_PIN_REG(MX51_PAD_USBH1_DATA1, 0x68c, 0x28c, 0, 0x000, 0), /* MX51_PAD_USBH1_DATA1__USBH1_DATA1 */
+       IMX_PIN_REG(MX51_PAD_USBH1_DATA2, 0x690, 0x290, 2, 0x000, 0), /* MX51_PAD_USBH1_DATA2__GPIO1_13 */
+       IMX_PIN_REG(MX51_PAD_USBH1_DATA2, 0x690, 0x290, 1, 0x000, 0), /* MX51_PAD_USBH1_DATA2__UART2_TXD */
+       IMX_PIN_REG(MX51_PAD_USBH1_DATA2, 0x690, 0x290, 0, 0x000, 0), /* MX51_PAD_USBH1_DATA2__USBH1_DATA2 */
+       IMX_PIN_REG(MX51_PAD_USBH1_DATA3, 0x694, 0x294, 2, 0x000, 0), /* MX51_PAD_USBH1_DATA3__GPIO1_14 */
+       IMX_PIN_REG(MX51_PAD_USBH1_DATA3, 0x694, 0x294, 1, 0x9e8, 5), /* MX51_PAD_USBH1_DATA3__UART2_RTS */
+       IMX_PIN_REG(MX51_PAD_USBH1_DATA3, 0x694, 0x294, 0, 0x000, 0), /* MX51_PAD_USBH1_DATA3__USBH1_DATA3 */
+       IMX_PIN_REG(MX51_PAD_USBH1_DATA4, 0x698, 0x298, 1, 0x000, 0), /* MX51_PAD_USBH1_DATA4__CSPI_SS0 */
+       IMX_PIN_REG(MX51_PAD_USBH1_DATA4, 0x698, 0x298, 2, 0x000, 0), /* MX51_PAD_USBH1_DATA4__GPIO1_15 */
+       IMX_PIN_REG(MX51_PAD_USBH1_DATA4, 0x698, 0x298, 0, 0x000, 0), /* MX51_PAD_USBH1_DATA4__USBH1_DATA4 */
+       IMX_PIN_REG(MX51_PAD_USBH1_DATA5, 0x69c, 0x29c, 1, 0x920, 0), /* MX51_PAD_USBH1_DATA5__CSPI_SS1 */
+       IMX_PIN_REG(MX51_PAD_USBH1_DATA5, 0x69c, 0x29c, 2, 0x000, 0), /* MX51_PAD_USBH1_DATA5__GPIO1_16 */
+       IMX_PIN_REG(MX51_PAD_USBH1_DATA5, 0x69c, 0x29c, 0, 0x000, 0), /* MX51_PAD_USBH1_DATA5__USBH1_DATA5 */
+       IMX_PIN_REG(MX51_PAD_USBH1_DATA6, 0x6a0, 0x2a0, 1, 0x928, 1), /* MX51_PAD_USBH1_DATA6__CSPI_SS3 */
+       IMX_PIN_REG(MX51_PAD_USBH1_DATA6, 0x6a0, 0x2a0, 2, 0x000, 0), /* MX51_PAD_USBH1_DATA6__GPIO1_17 */
+       IMX_PIN_REG(MX51_PAD_USBH1_DATA6, 0x6a0, 0x2a0, 0, 0x000, 0), /* MX51_PAD_USBH1_DATA6__USBH1_DATA6 */
+       IMX_PIN_REG(MX51_PAD_USBH1_DATA7, 0x6a4, 0x2a4, 1, 0x000, 0), /* MX51_PAD_USBH1_DATA7__ECSPI1_SS3 */
+       IMX_PIN_REG(MX51_PAD_USBH1_DATA7, 0x6a4, 0x2a4, 5, 0x934, 1), /* MX51_PAD_USBH1_DATA7__ECSPI2_SS3 */
+       IMX_PIN_REG(MX51_PAD_USBH1_DATA7, 0x6a4, 0x2a4, 2, 0x000, 0), /* MX51_PAD_USBH1_DATA7__GPIO1_18 */
+       IMX_PIN_REG(MX51_PAD_USBH1_DATA7, 0x6a4, 0x2a4, 0, 0x000, 0), /* MX51_PAD_USBH1_DATA7__USBH1_DATA7 */
+       IMX_PIN_REG(MX51_PAD_DI1_PIN11, 0x6a8, 0x2a8, 0, 0x000, 0), /* MX51_PAD_DI1_PIN11__DI1_PIN11 */
+       IMX_PIN_REG(MX51_PAD_DI1_PIN11, 0x6a8, 0x2a8, 7, 0x000, 0), /* MX51_PAD_DI1_PIN11__ECSPI1_SS2 */
+       IMX_PIN_REG(MX51_PAD_DI1_PIN11, 0x6a8, 0x2a8, 4, 0x000, 0), /* MX51_PAD_DI1_PIN11__GPIO3_0 */
+       IMX_PIN_REG(MX51_PAD_DI1_PIN12, 0x6ac, 0x2ac, 0, 0x000, 0), /* MX51_PAD_DI1_PIN12__DI1_PIN12 */
+       IMX_PIN_REG(MX51_PAD_DI1_PIN12, 0x6ac, 0x2ac, 4, 0x978, 1), /* MX51_PAD_DI1_PIN12__GPIO3_1 */
+       IMX_PIN_REG(MX51_PAD_DI1_PIN13, 0x6b0, 0x2b0, 0, 0x000, 0), /* MX51_PAD_DI1_PIN13__DI1_PIN13 */
+       IMX_PIN_REG(MX51_PAD_DI1_PIN13, 0x6b0, 0x2b0, 4, 0x97c, 1), /* MX51_PAD_DI1_PIN13__GPIO3_2 */
+       IMX_PIN_REG(MX51_PAD_DI1_D0_CS, 0x6b4, 0x2b4, 0, 0x000, 0), /* MX51_PAD_DI1_D0_CS__DI1_D0_CS */
+       IMX_PIN_REG(MX51_PAD_DI1_D0_CS, 0x6b4, 0x2b4, 4, 0x980, 1), /* MX51_PAD_DI1_D0_CS__GPIO3_3 */
+       IMX_PIN_REG(MX51_PAD_DI1_D1_CS, 0x6b8, 0x2b8, 0, 0x000, 0), /* MX51_PAD_DI1_D1_CS__DI1_D1_CS */
+       IMX_PIN_REG(MX51_PAD_DI1_D1_CS, 0x6b8, 0x2b8, 2, 0x000, 0), /* MX51_PAD_DI1_D1_CS__DISP1_PIN14 */
+       IMX_PIN_REG(MX51_PAD_DI1_D1_CS, 0x6b8, 0x2b8, 3, 0x000, 0), /* MX51_PAD_DI1_D1_CS__DISP1_PIN5 */
+       IMX_PIN_REG(MX51_PAD_DI1_D1_CS, 0x6b8, 0x2b8, 4, 0x984, 1), /* MX51_PAD_DI1_D1_CS__GPIO3_4 */
+       IMX_PIN_REG(MX51_PAD_DISPB2_SER_DIN, 0x6bc, 0x2bc, 2, 0x9a4, 1), /* MX51_PAD_DISPB2_SER_DIN__DISP1_PIN1 */
+       IMX_PIN_REG(MX51_PAD_DISPB2_SER_DIN, 0x6bc, 0x2bc, 0, 0x9c4, 0), /* MX51_PAD_DISPB2_SER_DIN__DISPB2_SER_DIN */
+       IMX_PIN_REG(MX51_PAD_DISPB2_SER_DIN, 0x6bc, 0x2bc, 4, 0x988, 1), /* MX51_PAD_DISPB2_SER_DIN__GPIO3_5 */
+       IMX_PIN_REG(MX51_PAD_DISPB2_SER_DIO, 0x6c0, 0x2c0, 3, 0x000, 0), /* MX51_PAD_DISPB2_SER_DIO__DISP1_PIN6 */
+       IMX_PIN_REG(MX51_PAD_DISPB2_SER_DIO, 0x6c0, 0x2c0, 0, 0x9c4, 1), /* MX51_PAD_DISPB2_SER_DIO__DISPB2_SER_DIO */
+       IMX_PIN_REG(MX51_PAD_DISPB2_SER_DIO, 0x6c0, 0x2c0, 4, 0x98c, 1), /* MX51_PAD_DISPB2_SER_DIO__GPIO3_6 */
+       IMX_PIN_REG(MX51_PAD_DISPB2_SER_CLK, 0x6c4, 0x2c4, 2, 0x000, 0), /* MX51_PAD_DISPB2_SER_CLK__DISP1_PIN17 */
+       IMX_PIN_REG(MX51_PAD_DISPB2_SER_CLK, 0x6c4, 0x2c4, 3, 0x000, 0), /* MX51_PAD_DISPB2_SER_CLK__DISP1_PIN7 */
+       IMX_PIN_REG(MX51_PAD_DISPB2_SER_CLK, 0x6c4, 0x2c4, 0, 0x000, 0), /* MX51_PAD_DISPB2_SER_CLK__DISPB2_SER_CLK */
+       IMX_PIN_REG(MX51_PAD_DISPB2_SER_CLK, 0x6c4, 0x2c4, 4, 0x990, 1), /* MX51_PAD_DISPB2_SER_CLK__GPIO3_7 */
+       IMX_PIN_REG(MX51_PAD_DISPB2_SER_RS, 0x6c8, 0x2c8, 2, 0x000, 0), /* MX51_PAD_DISPB2_SER_RS__DISP1_EXT_CLK */
+       IMX_PIN_REG(MX51_PAD_DISPB2_SER_RS, 0x6c8, 0x2c8, 2, 0x000, 0), /* MX51_PAD_DISPB2_SER_RS__DISP1_PIN16 */
+       IMX_PIN_REG(MX51_PAD_DISPB2_SER_RS, 0x6c8, 0x2c8, 3, 0x000, 0), /* MX51_PAD_DISPB2_SER_RS__DISP1_PIN8 */
+       IMX_PIN_REG(MX51_PAD_DISPB2_SER_RS, 0x6c8, 0x2c8, 0, 0x000, 0), /* MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS */
+       IMX_PIN_REG(MX51_PAD_DISPB2_SER_RS, 0x6c8, 0x2c8, 0, 0x000, 0), /* MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS */
+       IMX_PIN_REG(MX51_PAD_DISPB2_SER_RS, 0x6c8, 0x2c8, 4, 0x994, 1), /* MX51_PAD_DISPB2_SER_RS__GPIO3_8 */
+       IMX_PIN_REG(MX51_PAD_DISP1_DAT0, 0x6cc, 0x2cc, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT0__DISP1_DAT0 */
+       IMX_PIN_REG(MX51_PAD_DISP1_DAT1, 0x6d0, 0x2d0, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT1__DISP1_DAT1 */
+       IMX_PIN_REG(MX51_PAD_DISP1_DAT2, 0x6d4, 0x2d4, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT2__DISP1_DAT2 */
+       IMX_PIN_REG(MX51_PAD_DISP1_DAT3, 0x6d8, 0x2d8, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT3__DISP1_DAT3 */
+       IMX_PIN_REG(MX51_PAD_DISP1_DAT4, 0x6dc, 0x2dc, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT4__DISP1_DAT4 */
+       IMX_PIN_REG(MX51_PAD_DISP1_DAT5, 0x6e0, 0x2e0, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT5__DISP1_DAT5 */
+       IMX_PIN_REG(MX51_PAD_DISP1_DAT6, 0x6e4, 0x2e4, 7, 0x000, 0), /* MX51_PAD_DISP1_DAT6__BOOT_USB_SRC */
+       IMX_PIN_REG(MX51_PAD_DISP1_DAT6, 0x6e4, 0x2e4, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT6__DISP1_DAT6 */
+       IMX_PIN_REG(MX51_PAD_DISP1_DAT7, 0x6e8, 0x2e8, 7, 0x000, 0), /* MX51_PAD_DISP1_DAT7__BOOT_EEPROM_CFG */
+       IMX_PIN_REG(MX51_PAD_DISP1_DAT7, 0x6e8, 0x2e8, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT7__DISP1_DAT7 */
+       IMX_PIN_REG(MX51_PAD_DISP1_DAT8, 0x6ec, 0x2ec, 7, 0x000, 0), /* MX51_PAD_DISP1_DAT8__BOOT_SRC0 */
+       IMX_PIN_REG(MX51_PAD_DISP1_DAT8, 0x6ec, 0x2ec, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT8__DISP1_DAT8 */
+       IMX_PIN_REG(MX51_PAD_DISP1_DAT9, 0x6f0, 0x2f0, 7, 0x000, 0), /* MX51_PAD_DISP1_DAT9__BOOT_SRC1 */
+       IMX_PIN_REG(MX51_PAD_DISP1_DAT9, 0x6f0, 0x2f0, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT9__DISP1_DAT9 */
+       IMX_PIN_REG(MX51_PAD_DISP1_DAT10, 0x6f4, 0x2f4, 7, 0x000, 0), /* MX51_PAD_DISP1_DAT10__BOOT_SPARE_SIZE */
+       IMX_PIN_REG(MX51_PAD_DISP1_DAT10, 0x6f4, 0x2f4, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT10__DISP1_DAT10 */
+       IMX_PIN_REG(MX51_PAD_DISP1_DAT11, 0x6f8, 0x2f8, 7, 0x000, 0), /* MX51_PAD_DISP1_DAT11__BOOT_LPB_FREQ2 */
+       IMX_PIN_REG(MX51_PAD_DISP1_DAT11, 0x6f8, 0x2f8, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT11__DISP1_DAT11 */
+       IMX_PIN_REG(MX51_PAD_DISP1_DAT12, 0x6fc, 0x2fc, 7, 0x000, 0), /* MX51_PAD_DISP1_DAT12__BOOT_MLC_SEL */
+       IMX_PIN_REG(MX51_PAD_DISP1_DAT12, 0x6fc, 0x2fc, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT12__DISP1_DAT12 */
+       IMX_PIN_REG(MX51_PAD_DISP1_DAT13, 0x700, 0x300, 7, 0x000, 0), /* MX51_PAD_DISP1_DAT13__BOOT_MEM_CTL0 */
+       IMX_PIN_REG(MX51_PAD_DISP1_DAT13, 0x700, 0x300, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT13__DISP1_DAT13 */
+       IMX_PIN_REG(MX51_PAD_DISP1_DAT14, 0x704, 0x304, 7, 0x000, 0), /* MX51_PAD_DISP1_DAT14__BOOT_MEM_CTL1 */
+       IMX_PIN_REG(MX51_PAD_DISP1_DAT14, 0x704, 0x304, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT14__DISP1_DAT14 */
+       IMX_PIN_REG(MX51_PAD_DISP1_DAT15, 0x708, 0x308, 7, 0x000, 0), /* MX51_PAD_DISP1_DAT15__BOOT_BUS_WIDTH */
+       IMX_PIN_REG(MX51_PAD_DISP1_DAT15, 0x708, 0x308, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT15__DISP1_DAT15 */
+       IMX_PIN_REG(MX51_PAD_DISP1_DAT16, 0x70c, 0x30c, 7, 0x000, 0), /* MX51_PAD_DISP1_DAT16__BOOT_PAGE_SIZE0 */
+       IMX_PIN_REG(MX51_PAD_DISP1_DAT16, 0x70c, 0x30c, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT16__DISP1_DAT16 */
+       IMX_PIN_REG(MX51_PAD_DISP1_DAT17, 0x710, 0x310, 7, 0x000, 0), /* MX51_PAD_DISP1_DAT17__BOOT_PAGE_SIZE1 */
+       IMX_PIN_REG(MX51_PAD_DISP1_DAT17, 0x710, 0x310, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT17__DISP1_DAT17 */
+       IMX_PIN_REG(MX51_PAD_DISP1_DAT18, 0x714, 0x314, 7, 0x000, 0), /* MX51_PAD_DISP1_DAT18__BOOT_WEIM_MUXED0 */
+       IMX_PIN_REG(MX51_PAD_DISP1_DAT18, 0x714, 0x314, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT18__DISP1_DAT18 */
+       IMX_PIN_REG(MX51_PAD_DISP1_DAT18, 0x714, 0x314, 5, 0x000, 0), /* MX51_PAD_DISP1_DAT18__DISP2_PIN11 */
+       IMX_PIN_REG(MX51_PAD_DISP1_DAT18, 0x714, 0x314, 4, 0x000, 0), /* MX51_PAD_DISP1_DAT18__DISP2_PIN5 */
+       IMX_PIN_REG(MX51_PAD_DISP1_DAT19, 0x718, 0x318, 7, 0x000, 0), /* MX51_PAD_DISP1_DAT19__BOOT_WEIM_MUXED1 */
+       IMX_PIN_REG(MX51_PAD_DISP1_DAT19, 0x718, 0x318, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT19__DISP1_DAT19 */
+       IMX_PIN_REG(MX51_PAD_DISP1_DAT19, 0x718, 0x318, 5, 0x000, 0), /* MX51_PAD_DISP1_DAT19__DISP2_PIN12 */
+       IMX_PIN_REG(MX51_PAD_DISP1_DAT19, 0x718, 0x318, 4, 0x000, 0), /* MX51_PAD_DISP1_DAT19__DISP2_PIN6 */
+       IMX_PIN_REG(MX51_PAD_DISP1_DAT20, 0x71c, 0x31c, 7, 0x000, 0), /* MX51_PAD_DISP1_DAT20__BOOT_MEM_TYPE0 */
+       IMX_PIN_REG(MX51_PAD_DISP1_DAT20, 0x71c, 0x31c, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT20__DISP1_DAT20 */
+       IMX_PIN_REG(MX51_PAD_DISP1_DAT20, 0x71c, 0x31c, 5, 0x000, 0), /* MX51_PAD_DISP1_DAT20__DISP2_PIN13 */
+       IMX_PIN_REG(MX51_PAD_DISP1_DAT20, 0x71c, 0x31c, 4, 0x000, 0), /* MX51_PAD_DISP1_DAT20__DISP2_PIN7 */
+       IMX_PIN_REG(MX51_PAD_DISP1_DAT21, 0x720, 0x320, 7, 0x000, 0), /* MX51_PAD_DISP1_DAT21__BOOT_MEM_TYPE1 */
+       IMX_PIN_REG(MX51_PAD_DISP1_DAT21, 0x720, 0x320, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT21__DISP1_DAT21 */
+       IMX_PIN_REG(MX51_PAD_DISP1_DAT21, 0x720, 0x320, 5, 0x000, 0), /* MX51_PAD_DISP1_DAT21__DISP2_PIN14 */
+       IMX_PIN_REG(MX51_PAD_DISP1_DAT21, 0x720, 0x320, 4, 0x000, 0), /* MX51_PAD_DISP1_DAT21__DISP2_PIN8 */
+       IMX_PIN_REG(MX51_PAD_DISP1_DAT22, 0x724, 0x324, 7, 0x000, 0), /* MX51_PAD_DISP1_DAT22__BOOT_LPB_FREQ0 */
+       IMX_PIN_REG(MX51_PAD_DISP1_DAT22, 0x724, 0x324, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT22__DISP1_DAT22 */
+       IMX_PIN_REG(MX51_PAD_DISP1_DAT22, 0x724, 0x324, 6, 0x000, 0), /* MX51_PAD_DISP1_DAT22__DISP2_D0_CS */
+       IMX_PIN_REG(MX51_PAD_DISP1_DAT22, 0x724, 0x324, 5, 0x000, 0), /* MX51_PAD_DISP1_DAT22__DISP2_DAT16 */
+       IMX_PIN_REG(MX51_PAD_DISP1_DAT23, 0x728, 0x328, 7, 0x000, 0), /* MX51_PAD_DISP1_DAT23__BOOT_LPB_FREQ1 */
+       IMX_PIN_REG(MX51_PAD_DISP1_DAT23, 0x728, 0x328, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT23__DISP1_DAT23 */
+       IMX_PIN_REG(MX51_PAD_DISP1_DAT23, 0x728, 0x328, 6, 0x000, 0), /* MX51_PAD_DISP1_DAT23__DISP2_D1_CS */
+       IMX_PIN_REG(MX51_PAD_DISP1_DAT23, 0x728, 0x328, 5, 0x000, 0), /* MX51_PAD_DISP1_DAT23__DISP2_DAT17 */
+       IMX_PIN_REG(MX51_PAD_DISP1_DAT23, 0x728, 0x328, 4, 0x000, 0), /* MX51_PAD_DISP1_DAT23__DISP2_SER_CS */
+       IMX_PIN_REG(MX51_PAD_DI1_PIN3, 0x72c, 0x32c, 0, 0x000, 0), /* MX51_PAD_DI1_PIN3__DI1_PIN3 */
+       IMX_PIN_REG(MX51_PAD_DI1_PIN2, 0x734, 0x330, 0, 0x000, 0), /* MX51_PAD_DI1_PIN2__DI1_PIN2 */
+       IMX_PIN_REG(MX51_PAD_DI_GP2, 0x740, 0x338, 0, 0x000, 0), /* MX51_PAD_DI_GP2__DISP1_SER_CLK */
+       IMX_PIN_REG(MX51_PAD_DI_GP2, 0x740, 0x338, 2, 0x9a8, 1), /* MX51_PAD_DI_GP2__DISP2_WAIT */
+       IMX_PIN_REG(MX51_PAD_DI_GP3, 0x744, 0x33c, 3, 0x9a0, 1), /* MX51_PAD_DI_GP3__CSI1_DATA_EN */
+       IMX_PIN_REG(MX51_PAD_DI_GP3, 0x744, 0x33c, 0, 0x9c0, 0), /* MX51_PAD_DI_GP3__DISP1_SER_DIO */
+       IMX_PIN_REG(MX51_PAD_DI_GP3, 0x744, 0x33c, 2, 0x000, 0), /* MX51_PAD_DI_GP3__FEC_TX_ER */
+       IMX_PIN_REG(MX51_PAD_DI2_PIN4, 0x748, 0x340, 3, 0x99c, 1), /* MX51_PAD_DI2_PIN4__CSI2_DATA_EN */
+       IMX_PIN_REG(MX51_PAD_DI2_PIN4, 0x748, 0x340, 0, 0x000, 0), /* MX51_PAD_DI2_PIN4__DI2_PIN4 */
+       IMX_PIN_REG(MX51_PAD_DI2_PIN4, 0x748, 0x340, 2, 0x950, 1), /* MX51_PAD_DI2_PIN4__FEC_CRS */
+       IMX_PIN_REG(MX51_PAD_DI2_PIN2, 0x74c, 0x344, 0, 0x000, 0), /* MX51_PAD_DI2_PIN2__DI2_PIN2 */
+       IMX_PIN_REG(MX51_PAD_DI2_PIN2, 0x74c, 0x344, 2, 0x000, 0), /* MX51_PAD_DI2_PIN2__FEC_MDC */
+       IMX_PIN_REG(MX51_PAD_DI2_PIN3, 0x750, 0x348, 0, 0x000, 0), /* MX51_PAD_DI2_PIN3__DI2_PIN3 */
+       IMX_PIN_REG(MX51_PAD_DI2_PIN3, 0x750, 0x348, 2, 0x954, 1), /* MX51_PAD_DI2_PIN3__FEC_MDIO */
+       IMX_PIN_REG(MX51_PAD_DI2_DISP_CLK, 0x754, 0x34c, 0, 0x000, 0), /* MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK */
+       IMX_PIN_REG(MX51_PAD_DI2_DISP_CLK, 0x754, 0x34c, 2, 0x95c, 1), /* MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 */
+       IMX_PIN_REG(MX51_PAD_DI_GP4, 0x758, 0x350, 4, 0x000, 0), /* MX51_PAD_DI_GP4__DI2_PIN15 */
+       IMX_PIN_REG(MX51_PAD_DI_GP4, 0x758, 0x350, 0, 0x9c0, 1), /* MX51_PAD_DI_GP4__DISP1_SER_DIN */
+       IMX_PIN_REG(MX51_PAD_DI_GP4, 0x758, 0x350, 3, 0x000, 0), /* MX51_PAD_DI_GP4__DISP2_PIN1 */
+       IMX_PIN_REG(MX51_PAD_DI_GP4, 0x758, 0x350, 2, 0x960, 1), /* MX51_PAD_DI_GP4__FEC_RDATA2 */
+       IMX_PIN_REG(MX51_PAD_DISP2_DAT0, 0x75c, 0x354, 0, 0x000, 0), /* MX51_PAD_DISP2_DAT0__DISP2_DAT0 */
+       IMX_PIN_REG(MX51_PAD_DISP2_DAT0, 0x75c, 0x354, 2, 0x964, 1), /* MX51_PAD_DISP2_DAT0__FEC_RDATA3 */
+       IMX_PIN_REG(MX51_PAD_DISP2_DAT0, 0x75c, 0x354, 4, 0x9c8, 1), /* MX51_PAD_DISP2_DAT0__KEY_COL6 */
+       IMX_PIN_REG(MX51_PAD_DISP2_DAT0, 0x75c, 0x354, 5, 0x9f4, 8), /* MX51_PAD_DISP2_DAT0__UART3_RXD */
+       IMX_PIN_REG(MX51_PAD_DISP2_DAT0, 0x75c, 0x354, 3, 0x9f8, 1), /* MX51_PAD_DISP2_DAT0__USBH3_CLK */
+       IMX_PIN_REG(MX51_PAD_DISP2_DAT1, 0x760, 0x358, 0, 0x000, 0), /* MX51_PAD_DISP2_DAT1__DISP2_DAT1 */
+       IMX_PIN_REG(MX51_PAD_DISP2_DAT1, 0x760, 0x358, 2, 0x970, 1), /* MX51_PAD_DISP2_DAT1__FEC_RX_ER */
+       IMX_PIN_REG(MX51_PAD_DISP2_DAT1, 0x760, 0x358, 4, 0x9cc, 1), /* MX51_PAD_DISP2_DAT1__KEY_COL7 */
+       IMX_PIN_REG(MX51_PAD_DISP2_DAT1, 0x760, 0x358, 5, 0x000, 0), /* MX51_PAD_DISP2_DAT1__UART3_TXD */
+       IMX_PIN_REG(MX51_PAD_DISP2_DAT1, 0x760, 0x358, 3, 0xa1c, 1), /* MX51_PAD_DISP2_DAT1__USBH3_DIR */
+       IMX_PIN_REG(MX51_PAD_DISP2_DAT2, 0x764, 0x35c, 0, 0x000, 0), /* MX51_PAD_DISP2_DAT2__DISP2_DAT2 */
+       IMX_PIN_REG(MX51_PAD_DISP2_DAT3, 0x768, 0x360, 0, 0x000, 0), /* MX51_PAD_DISP2_DAT3__DISP2_DAT3 */
+       IMX_PIN_REG(MX51_PAD_DISP2_DAT4, 0x76c, 0x364, 0, 0x000, 0), /* MX51_PAD_DISP2_DAT4__DISP2_DAT4 */
+       IMX_PIN_REG(MX51_PAD_DISP2_DAT5, 0x770, 0x368, 0, 0x000, 0), /* MX51_PAD_DISP2_DAT5__DISP2_DAT5 */
+       IMX_PIN_REG(MX51_PAD_DISP2_DAT6, 0x774, 0x36c, 0, 0x000, 0), /* MX51_PAD_DISP2_DAT6__DISP2_DAT6 */
+       IMX_PIN_REG(MX51_PAD_DISP2_DAT6, 0x774, 0x36c, 2, 0x000, 0), /* MX51_PAD_DISP2_DAT6__FEC_TDATA1 */
+       IMX_PIN_REG(MX51_PAD_DISP2_DAT6, 0x774, 0x36c, 5, 0x000, 0), /* MX51_PAD_DISP2_DAT6__GPIO1_19 */
+       IMX_PIN_REG(MX51_PAD_DISP2_DAT6, 0x774, 0x36c, 4, 0x9d0, 1), /* MX51_PAD_DISP2_DAT6__KEY_ROW4 */
+       IMX_PIN_REG(MX51_PAD_DISP2_DAT6, 0x774, 0x36c, 3, 0xa24, 1), /* MX51_PAD_DISP2_DAT6__USBH3_STP */
+       IMX_PIN_REG(MX51_PAD_DISP2_DAT7, 0x778, 0x370, 0, 0x000, 0), /* MX51_PAD_DISP2_DAT7__DISP2_DAT7 */
+       IMX_PIN_REG(MX51_PAD_DISP2_DAT7, 0x778, 0x370, 2, 0x000, 0), /* MX51_PAD_DISP2_DAT7__FEC_TDATA2 */
+       IMX_PIN_REG(MX51_PAD_DISP2_DAT7, 0x778, 0x370, 5, 0x000, 0), /* MX51_PAD_DISP2_DAT7__GPIO1_29 */
+       IMX_PIN_REG(MX51_PAD_DISP2_DAT7, 0x778, 0x370, 4, 0x9d4, 1), /* MX51_PAD_DISP2_DAT7__KEY_ROW5 */
+       IMX_PIN_REG(MX51_PAD_DISP2_DAT7, 0x778, 0x370, 3, 0xa20, 1), /* MX51_PAD_DISP2_DAT7__USBH3_NXT */
+       IMX_PIN_REG(MX51_PAD_DISP2_DAT8, 0x77c, 0x374, 0, 0x000, 0), /* MX51_PAD_DISP2_DAT8__DISP2_DAT8 */
+       IMX_PIN_REG(MX51_PAD_DISP2_DAT8, 0x77c, 0x374, 2, 0x000, 0), /* MX51_PAD_DISP2_DAT8__FEC_TDATA3 */
+       IMX_PIN_REG(MX51_PAD_DISP2_DAT8, 0x77c, 0x374, 5, 0x000, 0), /* MX51_PAD_DISP2_DAT8__GPIO1_30 */
+       IMX_PIN_REG(MX51_PAD_DISP2_DAT8, 0x77c, 0x374, 4, 0x9d8, 1), /* MX51_PAD_DISP2_DAT8__KEY_ROW6 */
+       IMX_PIN_REG(MX51_PAD_DISP2_DAT8, 0x77c, 0x374, 3, 0x9fc, 1), /* MX51_PAD_DISP2_DAT8__USBH3_DATA0 */
+       IMX_PIN_REG(MX51_PAD_DISP2_DAT9, 0x780, 0x378, 4, 0x8f4, 1), /* MX51_PAD_DISP2_DAT9__AUD6_RXC */
+       IMX_PIN_REG(MX51_PAD_DISP2_DAT9, 0x780, 0x378, 0, 0x000, 0), /* MX51_PAD_DISP2_DAT9__DISP2_DAT9 */
+       IMX_PIN_REG(MX51_PAD_DISP2_DAT9, 0x780, 0x378, 2, 0x000, 0), /* MX51_PAD_DISP2_DAT9__FEC_TX_EN */
+       IMX_PIN_REG(MX51_PAD_DISP2_DAT9, 0x780, 0x378, 5, 0x000, 0), /* MX51_PAD_DISP2_DAT9__GPIO1_31 */
+       IMX_PIN_REG(MX51_PAD_DISP2_DAT9, 0x780, 0x378, 3, 0xa00, 1), /* MX51_PAD_DISP2_DAT9__USBH3_DATA1 */
+       IMX_PIN_REG(MX51_PAD_DISP2_DAT10, 0x784, 0x37c, 0, 0x000, 0), /* MX51_PAD_DISP2_DAT10__DISP2_DAT10 */
+       IMX_PIN_REG(MX51_PAD_DISP2_DAT10, 0x784, 0x37c, 5, 0x000, 0), /* MX51_PAD_DISP2_DAT10__DISP2_SER_CS */
+       IMX_PIN_REG(MX51_PAD_DISP2_DAT10, 0x784, 0x37c, 2, 0x94c, 1), /* MX51_PAD_DISP2_DAT10__FEC_COL */
+       IMX_PIN_REG(MX51_PAD_DISP2_DAT10, 0x784, 0x37c, 4, 0x9dc, 1), /* MX51_PAD_DISP2_DAT10__KEY_ROW7 */
+       IMX_PIN_REG(MX51_PAD_DISP2_DAT10, 0x784, 0x37c, 3, 0xa04, 1), /* MX51_PAD_DISP2_DAT10__USBH3_DATA2 */
+       IMX_PIN_REG(MX51_PAD_DISP2_DAT11, 0x788, 0x380, 4, 0x8f0, 1), /* MX51_PAD_DISP2_DAT11__AUD6_TXD */
+       IMX_PIN_REG(MX51_PAD_DISP2_DAT11, 0x788, 0x380, 0, 0x000, 0), /* MX51_PAD_DISP2_DAT11__DISP2_DAT11 */
+       IMX_PIN_REG(MX51_PAD_DISP2_DAT11, 0x788, 0x380, 2, 0x968, 1), /* MX51_PAD_DISP2_DAT11__FEC_RX_CLK */
+       IMX_PIN_REG(MX51_PAD_DISP2_DAT11, 0x788, 0x380, 7, 0x000, 0), /* MX51_PAD_DISP2_DAT11__GPIO1_10 */
+       IMX_PIN_REG(MX51_PAD_DISP2_DAT11, 0x788, 0x380, 3, 0xa08, 1), /* MX51_PAD_DISP2_DAT11__USBH3_DATA3 */
+       IMX_PIN_REG(MX51_PAD_DISP2_DAT12, 0x78c, 0x384, 4, 0x8ec, 1), /* MX51_PAD_DISP2_DAT12__AUD6_RXD */
+       IMX_PIN_REG(MX51_PAD_DISP2_DAT12, 0x78c, 0x384, 0, 0x000, 0), /* MX51_PAD_DISP2_DAT12__DISP2_DAT12 */
+       IMX_PIN_REG(MX51_PAD_DISP2_DAT12, 0x78c, 0x384, 2, 0x96c, 1), /* MX51_PAD_DISP2_DAT12__FEC_RX_DV */
+       IMX_PIN_REG(MX51_PAD_DISP2_DAT12, 0x78c, 0x384, 3, 0xa0c, 1), /* MX51_PAD_DISP2_DAT12__USBH3_DATA4 */
+       IMX_PIN_REG(MX51_PAD_DISP2_DAT13, 0x790, 0x388, 4, 0x8fc, 1), /* MX51_PAD_DISP2_DAT13__AUD6_TXC */
+       IMX_PIN_REG(MX51_PAD_DISP2_DAT13, 0x790, 0x388, 0, 0x000, 0), /* MX51_PAD_DISP2_DAT13__DISP2_DAT13 */
+       IMX_PIN_REG(MX51_PAD_DISP2_DAT13, 0x790, 0x388, 2, 0x974, 1), /* MX51_PAD_DISP2_DAT13__FEC_TX_CLK */
+       IMX_PIN_REG(MX51_PAD_DISP2_DAT13, 0x790, 0x388, 3, 0xa10, 1), /* MX51_PAD_DISP2_DAT13__USBH3_DATA5 */
+       IMX_PIN_REG(MX51_PAD_DISP2_DAT14, 0x794, 0x38c, 4, 0x900, 1), /* MX51_PAD_DISP2_DAT14__AUD6_TXFS */
+       IMX_PIN_REG(MX51_PAD_DISP2_DAT14, 0x794, 0x38c, 0, 0x000, 0), /* MX51_PAD_DISP2_DAT14__DISP2_DAT14 */
+       IMX_PIN_REG(MX51_PAD_DISP2_DAT14, 0x794, 0x38c, 2, 0x958, 1), /* MX51_PAD_DISP2_DAT14__FEC_RDATA0 */
+       IMX_PIN_REG(MX51_PAD_DISP2_DAT14, 0x794, 0x38c, 3, 0xa14, 1), /* MX51_PAD_DISP2_DAT14__USBH3_DATA6 */
+       IMX_PIN_REG(MX51_PAD_DISP2_DAT15, 0x798, 0x390, 4, 0x8f8, 1), /* MX51_PAD_DISP2_DAT15__AUD6_RXFS */
+       IMX_PIN_REG(MX51_PAD_DISP2_DAT15, 0x798, 0x390, 5, 0x000, 0), /* MX51_PAD_DISP2_DAT15__DISP1_SER_CS */
+       IMX_PIN_REG(MX51_PAD_DISP2_DAT15, 0x798, 0x390, 0, 0x000, 0), /* MX51_PAD_DISP2_DAT15__DISP2_DAT15 */
+       IMX_PIN_REG(MX51_PAD_DISP2_DAT15, 0x798, 0x390, 2, 0x000, 0), /* MX51_PAD_DISP2_DAT15__FEC_TDATA0 */
+       IMX_PIN_REG(MX51_PAD_DISP2_DAT15, 0x798, 0x390, 3, 0xa18, 1), /* MX51_PAD_DISP2_DAT15__USBH3_DATA7 */
+       IMX_PIN_REG(MX51_PAD_SD1_CMD, 0x79c, 0x394, 1, 0x8e0, 1), /* MX51_PAD_SD1_CMD__AUD5_RXFS */
+       IMX_PIN_REG(MX51_PAD_SD1_CMD, 0x79c, 0x394, 2, 0x91c, 2), /* MX51_PAD_SD1_CMD__CSPI_MOSI */
+       IMX_PIN_REG(MX51_PAD_SD1_CMD, 0x79c, 0x394, 0, 0x000, 0), /* MX51_PAD_SD1_CMD__SD1_CMD */
+       IMX_PIN_REG(MX51_PAD_SD1_CLK, 0x7a0, 0x398, 1, 0x8dc, 1), /* MX51_PAD_SD1_CLK__AUD5_RXC */
+       IMX_PIN_REG(MX51_PAD_SD1_CLK, 0x7a0, 0x398, 2, 0x914, 2), /* MX51_PAD_SD1_CLK__CSPI_SCLK */
+       IMX_PIN_REG(MX51_PAD_SD1_CLK, 0x7a0, 0x398, 0, 0x000, 0), /* MX51_PAD_SD1_CLK__SD1_CLK */
+       IMX_PIN_REG(MX51_PAD_SD1_DATA0, 0x7a4, 0x39c, 1, 0x8d8, 2), /* MX51_PAD_SD1_DATA0__AUD5_TXD */
+       IMX_PIN_REG(MX51_PAD_SD1_DATA0, 0x7a4, 0x39c, 2, 0x918, 1), /* MX51_PAD_SD1_DATA0__CSPI_MISO */
+       IMX_PIN_REG(MX51_PAD_SD1_DATA0, 0x7a4, 0x39c, 0, 0x000, 0), /* MX51_PAD_SD1_DATA0__SD1_DATA0 */
+       IMX_PIN_REG(MX51_PAD_EIM_DA0, NO_PAD, 0x01c, 0, 0x000, 0), /* MX51_PAD_EIM_DA0__EIM_DA0 */
+       IMX_PIN_REG(MX51_PAD_EIM_DA1, NO_PAD, 0x020, 0, 0x000, 0), /* MX51_PAD_EIM_DA1__EIM_DA1 */
+       IMX_PIN_REG(MX51_PAD_EIM_DA2, NO_PAD, 0x024, 0, 0x000, 0), /* MX51_PAD_EIM_DA2__EIM_DA2 */
+       IMX_PIN_REG(MX51_PAD_EIM_DA3, NO_PAD, 0x028, 0, 0x000, 0), /* MX51_PAD_EIM_DA3__EIM_DA3 */
+       IMX_PIN_REG(MX51_PAD_SD1_DATA1, 0x7a8, 0x3a0, 1, 0x8d4, 2), /* MX51_PAD_SD1_DATA1__AUD5_RXD */
+       IMX_PIN_REG(MX51_PAD_SD1_DATA1, 0x7a8, 0x3a0, 0, 0x000, 0), /* MX51_PAD_SD1_DATA1__SD1_DATA1 */
+       IMX_PIN_REG(MX51_PAD_EIM_DA4, NO_PAD, 0x02c, 0, 0x000, 0), /* MX51_PAD_EIM_DA4__EIM_DA4 */
+       IMX_PIN_REG(MX51_PAD_EIM_DA5, NO_PAD, 0x030, 0, 0x000, 0), /* MX51_PAD_EIM_DA5__EIM_DA5 */
+       IMX_PIN_REG(MX51_PAD_EIM_DA6, NO_PAD, 0x034, 0, 0x000, 0), /* MX51_PAD_EIM_DA6__EIM_DA6 */
+       IMX_PIN_REG(MX51_PAD_EIM_DA7, NO_PAD, 0x038, 0, 0x000, 0), /* MX51_PAD_EIM_DA7__EIM_DA7 */
+       IMX_PIN_REG(MX51_PAD_SD1_DATA2, 0x7ac, 0x3a4, 1, 0x8e4, 2), /* MX51_PAD_SD1_DATA2__AUD5_TXC */
+       IMX_PIN_REG(MX51_PAD_SD1_DATA2, 0x7ac, 0x3a4, 0, 0x000, 0), /* MX51_PAD_SD1_DATA2__SD1_DATA2 */
+       IMX_PIN_REG(MX51_PAD_EIM_DA10, NO_PAD, 0x044, 0, 0x000, 0), /* MX51_PAD_EIM_DA10__EIM_DA10 */
+       IMX_PIN_REG(MX51_PAD_EIM_DA11, NO_PAD, 0x048, 0, 0x000, 0), /* MX51_PAD_EIM_DA11__EIM_DA11 */
+       IMX_PIN_REG(MX51_PAD_EIM_DA8, NO_PAD, 0x03c, 0, 0x000, 0), /* MX51_PAD_EIM_DA8__EIM_DA8 */
+       IMX_PIN_REG(MX51_PAD_EIM_DA9, NO_PAD, 0x040, 0, 0x000, 0), /* MX51_PAD_EIM_DA9__EIM_DA9 */
+       IMX_PIN_REG(MX51_PAD_SD1_DATA3, 0x7b0, 0x3a8, 1, 0x8e8, 2), /* MX51_PAD_SD1_DATA3__AUD5_TXFS */
+       IMX_PIN_REG(MX51_PAD_SD1_DATA3, 0x7b0, 0x3a8, 2, 0x920, 1), /* MX51_PAD_SD1_DATA3__CSPI_SS1 */
+       IMX_PIN_REG(MX51_PAD_SD1_DATA3, 0x7b0, 0x3a8, 0, 0x000, 0), /* MX51_PAD_SD1_DATA3__SD1_DATA3 */
+       IMX_PIN_REG(MX51_PAD_GPIO1_0, 0x7b4, 0x3ac, 2, 0x924, 0), /* MX51_PAD_GPIO1_0__CSPI_SS2 */
+       IMX_PIN_REG(MX51_PAD_GPIO1_0, 0x7b4, 0x3ac, 1, 0x000, 0), /* MX51_PAD_GPIO1_0__GPIO1_0 */
+       IMX_PIN_REG(MX51_PAD_GPIO1_0, 0x7b4, 0x3ac, 0, 0x000, 0), /* MX51_PAD_GPIO1_0__SD1_CD */
+       IMX_PIN_REG(MX51_PAD_GPIO1_1, 0x7b8, 0x3b0, 2, 0x918, 2), /* MX51_PAD_GPIO1_1__CSPI_MISO */
+       IMX_PIN_REG(MX51_PAD_GPIO1_1, 0x7b8, 0x3b0, 1, 0x000, 0), /* MX51_PAD_GPIO1_1__GPIO1_1 */
+       IMX_PIN_REG(MX51_PAD_GPIO1_1, 0x7b8, 0x3b0, 0, 0x000, 0), /* MX51_PAD_GPIO1_1__SD1_WP */
+       IMX_PIN_REG(MX51_PAD_EIM_DA12, NO_PAD, 0x04c, 0, 0x000, 0), /* MX51_PAD_EIM_DA12__EIM_DA12 */
+       IMX_PIN_REG(MX51_PAD_EIM_DA13, NO_PAD, 0x050, 0, 0x000, 0), /* MX51_PAD_EIM_DA13__EIM_DA13 */
+       IMX_PIN_REG(MX51_PAD_EIM_DA14, NO_PAD, 0x054, 0, 0x000, 0), /* MX51_PAD_EIM_DA14__EIM_DA14 */
+       IMX_PIN_REG(MX51_PAD_EIM_DA15, NO_PAD, 0x058, 0, 0x000, 0), /* MX51_PAD_EIM_DA15__EIM_DA15 */
+       IMX_PIN_REG(MX51_PAD_SD2_CMD, NO_PAD, 0x3b4, 2, 0x91c, 3), /* MX51_PAD_SD2_CMD__CSPI_MOSI */
+       IMX_PIN_REG(MX51_PAD_SD2_CMD, 0x7bc, 0x3b4, 1, 0x9b0, 2), /* MX51_PAD_SD2_CMD__I2C1_SCL */
+       IMX_PIN_REG(MX51_PAD_SD2_CMD, 0x7bc, 0x3b4, 0, 0x000, 0), /* MX51_PAD_SD2_CMD__SD2_CMD */
+       IMX_PIN_REG(MX51_PAD_SD2_CLK, 0x7c0, 0x3b8, 2, 0x914, 3), /* MX51_PAD_SD2_CLK__CSPI_SCLK */
+       IMX_PIN_REG(MX51_PAD_SD2_CLK, 0x7c0, 0x3b8, 1, 0x9b4, 2), /* MX51_PAD_SD2_CLK__I2C1_SDA */
+       IMX_PIN_REG(MX51_PAD_SD2_CLK, 0x7c0, 0x3b8, 0, 0x000, 0), /* MX51_PAD_SD2_CLK__SD2_CLK */
+       IMX_PIN_REG(MX51_PAD_SD2_DATA0, 0x7c4, 0x3bc, 2, 0x918, 3), /* MX51_PAD_SD2_DATA0__CSPI_MISO */
+       IMX_PIN_REG(MX51_PAD_SD2_DATA0, 0x7c4, 0x3bc, 1, 0x000, 0), /* MX51_PAD_SD2_DATA0__SD1_DAT4 */
+       IMX_PIN_REG(MX51_PAD_SD2_DATA0, 0x7c4, 0x3bc, 0, 0x000, 0), /* MX51_PAD_SD2_DATA0__SD2_DATA0 */
+       IMX_PIN_REG(MX51_PAD_SD2_DATA1, 0x7c8, 0x3c0, 1, 0x000, 0), /* MX51_PAD_SD2_DATA1__SD1_DAT5 */
+       IMX_PIN_REG(MX51_PAD_SD2_DATA1, 0x7c8, 0x3c0, 0, 0x000, 0), /* MX51_PAD_SD2_DATA1__SD2_DATA1 */
+       IMX_PIN_REG(MX51_PAD_SD2_DATA1, 0x7c8, 0x3c0, 2, 0x000, 0), /* MX51_PAD_SD2_DATA1__USBH3_H2_DP */
+       IMX_PIN_REG(MX51_PAD_SD2_DATA2, 0x7cc, 0x3c4, 1, 0x000, 0), /* MX51_PAD_SD2_DATA2__SD1_DAT6 */
+       IMX_PIN_REG(MX51_PAD_SD2_DATA2, 0x7cc, 0x3c4, 0, 0x000, 0), /* MX51_PAD_SD2_DATA2__SD2_DATA2 */
+       IMX_PIN_REG(MX51_PAD_SD2_DATA2, 0x7cc, 0x3c4, 2, 0x000, 0), /* MX51_PAD_SD2_DATA2__USBH3_H2_DM */
+       IMX_PIN_REG(MX51_PAD_SD2_DATA3, 0x7d0, 0x3c8, 2, 0x924, 1), /* MX51_PAD_SD2_DATA3__CSPI_SS2 */
+       IMX_PIN_REG(MX51_PAD_SD2_DATA3, 0x7d0, 0x3c8, 1, 0x000, 0), /* MX51_PAD_SD2_DATA3__SD1_DAT7 */
+       IMX_PIN_REG(MX51_PAD_SD2_DATA3, 0x7d0, 0x3c8, 0, 0x000, 0), /* MX51_PAD_SD2_DATA3__SD2_DATA3 */
+       IMX_PIN_REG(MX51_PAD_GPIO1_2, 0x7d4, 0x3cc, 5, 0x000, 0), /* MX51_PAD_GPIO1_2__CCM_OUT_2 */
+       IMX_PIN_REG(MX51_PAD_GPIO1_2, 0x7d4, 0x3cc, 0, 0x000, 0), /* MX51_PAD_GPIO1_2__GPIO1_2 */
+       IMX_PIN_REG(MX51_PAD_GPIO1_2, 0x7d4, 0x3cc, 2, 0x9b8, 3), /* MX51_PAD_GPIO1_2__I2C2_SCL */
+       IMX_PIN_REG(MX51_PAD_GPIO1_2, 0x7d4, 0x3cc, 7, 0x90c, 1), /* MX51_PAD_GPIO1_2__PLL1_BYP */
+       IMX_PIN_REG(MX51_PAD_GPIO1_2, 0x7d4, 0x3cc, 1, 0x000, 0), /* MX51_PAD_GPIO1_2__PWM1_PWMO */
+       IMX_PIN_REG(MX51_PAD_GPIO1_3, 0x7d8, 0x3d0, 0, 0x000, 0), /* MX51_PAD_GPIO1_3__GPIO1_3 */
+       IMX_PIN_REG(MX51_PAD_GPIO1_3, 0x7d8, 0x3d0, 2, 0x9bc, 3), /* MX51_PAD_GPIO1_3__I2C2_SDA */
+       IMX_PIN_REG(MX51_PAD_GPIO1_3, 0x7d8, 0x3d0, 7, 0x910, 1), /* MX51_PAD_GPIO1_3__PLL2_BYP */
+       IMX_PIN_REG(MX51_PAD_GPIO1_3, 0x7d8, 0x3d0, 1, 0x000, 0), /* MX51_PAD_GPIO1_3__PWM2_PWMO */
+       IMX_PIN_REG(MX51_PAD_PMIC_INT_REQ, 0x7fc, 0x3d4, 0, 0x000, 0), /* MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ */
+       IMX_PIN_REG(MX51_PAD_PMIC_INT_REQ, 0x7fc, 0x3d4, 1, 0x000, 0), /* MX51_PAD_PMIC_INT_REQ__PMIC_PMU_IRQ_B */
+       IMX_PIN_REG(MX51_PAD_GPIO1_4, 0x804, 0x3d8, 4, 0x908, 1), /* MX51_PAD_GPIO1_4__DISP2_EXT_CLK */
+       IMX_PIN_REG(MX51_PAD_GPIO1_4, 0x804, 0x3d8, 3, 0x938, 1), /* MX51_PAD_GPIO1_4__EIM_RDY */
+       IMX_PIN_REG(MX51_PAD_GPIO1_4, 0x804, 0x3d8, 0, 0x000, 0), /* MX51_PAD_GPIO1_4__GPIO1_4 */
+       IMX_PIN_REG(MX51_PAD_GPIO1_4, 0x804, 0x3d8, 2, 0x000, 0), /* MX51_PAD_GPIO1_4__WDOG1_WDOG_B */
+       IMX_PIN_REG(MX51_PAD_GPIO1_5, 0x808, 0x3dc, 6, 0x000, 0), /* MX51_PAD_GPIO1_5__CSI2_MCLK */
+       IMX_PIN_REG(MX51_PAD_GPIO1_5, 0x808, 0x3dc, 3, 0x000, 0), /* MX51_PAD_GPIO1_5__DISP2_PIN16 */
+       IMX_PIN_REG(MX51_PAD_GPIO1_5, 0x808, 0x3dc, 0, 0x000, 0), /* MX51_PAD_GPIO1_5__GPIO1_5 */
+       IMX_PIN_REG(MX51_PAD_GPIO1_5, 0x808, 0x3dc, 2, 0x000, 0), /* MX51_PAD_GPIO1_5__WDOG2_WDOG_B */
+       IMX_PIN_REG(MX51_PAD_GPIO1_6, 0x80c, 0x3e0, 4, 0x000, 0), /* MX51_PAD_GPIO1_6__DISP2_PIN17 */
+       IMX_PIN_REG(MX51_PAD_GPIO1_6, 0x80c, 0x3e0, 0, 0x000, 0), /* MX51_PAD_GPIO1_6__GPIO1_6 */
+       IMX_PIN_REG(MX51_PAD_GPIO1_6, 0x80c, 0x3e0, 3, 0x000, 0), /* MX51_PAD_GPIO1_6__REF_EN_B */
+       IMX_PIN_REG(MX51_PAD_GPIO1_7, 0x810, 0x3e4, 3, 0x000, 0), /* MX51_PAD_GPIO1_7__CCM_OUT_0 */
+       IMX_PIN_REG(MX51_PAD_GPIO1_7, 0x810, 0x3e4, 0, 0x000, 0), /* MX51_PAD_GPIO1_7__GPIO1_7 */
+       IMX_PIN_REG(MX51_PAD_GPIO1_7, 0x810, 0x3e4, 6, 0x000, 0), /* MX51_PAD_GPIO1_7__SD2_WP */
+       IMX_PIN_REG(MX51_PAD_GPIO1_7, 0x810, 0x3e4, 2, 0x000, 0), /* MX51_PAD_GPIO1_7__SPDIF_OUT1 */
+       IMX_PIN_REG(MX51_PAD_GPIO1_8, 0x814, 0x3e8, 2, 0x99c, 2), /* MX51_PAD_GPIO1_8__CSI2_DATA_EN */
+       IMX_PIN_REG(MX51_PAD_GPIO1_8, 0x814, 0x3e8, 0, 0x000, 0), /* MX51_PAD_GPIO1_8__GPIO1_8 */
+       IMX_PIN_REG(MX51_PAD_GPIO1_8, 0x814, 0x3e8, 6, 0x000, 0), /* MX51_PAD_GPIO1_8__SD2_CD */
+       IMX_PIN_REG(MX51_PAD_GPIO1_8, 0x814, 0x3e8, 1, 0x000, 0), /* MX51_PAD_GPIO1_8__USBH3_PWR */
+       IMX_PIN_REG(MX51_PAD_GPIO1_9, 0x818, 0x3ec, 3, 0x000, 0), /* MX51_PAD_GPIO1_9__CCM_OUT_1 */
+       IMX_PIN_REG(MX51_PAD_GPIO1_9, 0x818, 0x3ec, 2, 0x000, 0), /* MX51_PAD_GPIO1_9__DISP2_D1_CS */
+       IMX_PIN_REG(MX51_PAD_GPIO1_9, 0x818, 0x3ec, 7, 0x000, 0), /* MX51_PAD_GPIO1_9__DISP2_SER_CS */
+       IMX_PIN_REG(MX51_PAD_GPIO1_9, 0x818, 0x3ec, 0, 0x000, 0), /* MX51_PAD_GPIO1_9__GPIO1_9 */
+       IMX_PIN_REG(MX51_PAD_GPIO1_9, 0x818, 0x3ec, 6, 0x000, 0), /* MX51_PAD_GPIO1_9__SD2_LCTL */
+       IMX_PIN_REG(MX51_PAD_GPIO1_9, 0x818, 0x3ec, 1, 0x000, 0), /* MX51_PAD_GPIO1_9__USBH3_OC */
+};
+
+/* Pad names for the pinmux subsystem */
+static const struct pinctrl_pin_desc imx51_pinctrl_pads[] = {
+       IMX_PINCTRL_PIN(MX51_PAD_EIM_D16),
+       IMX_PINCTRL_PIN(MX51_PAD_EIM_D17),
+       IMX_PINCTRL_PIN(MX51_PAD_EIM_D18),
+       IMX_PINCTRL_PIN(MX51_PAD_EIM_D19),
+       IMX_PINCTRL_PIN(MX51_PAD_EIM_D20),
+       IMX_PINCTRL_PIN(MX51_PAD_EIM_D21),
+       IMX_PINCTRL_PIN(MX51_PAD_EIM_D22),
+       IMX_PINCTRL_PIN(MX51_PAD_EIM_D23),
+       IMX_PINCTRL_PIN(MX51_PAD_EIM_D24),
+       IMX_PINCTRL_PIN(MX51_PAD_EIM_D25),
+       IMX_PINCTRL_PIN(MX51_PAD_EIM_D26),
+       IMX_PINCTRL_PIN(MX51_PAD_EIM_D27),
+       IMX_PINCTRL_PIN(MX51_PAD_EIM_D28),
+       IMX_PINCTRL_PIN(MX51_PAD_EIM_D29),
+       IMX_PINCTRL_PIN(MX51_PAD_EIM_D30),
+       IMX_PINCTRL_PIN(MX51_PAD_EIM_D31),
+       IMX_PINCTRL_PIN(MX51_PAD_EIM_A16),
+       IMX_PINCTRL_PIN(MX51_PAD_EIM_A17),
+       IMX_PINCTRL_PIN(MX51_PAD_EIM_A18),
+       IMX_PINCTRL_PIN(MX51_PAD_EIM_A19),
+       IMX_PINCTRL_PIN(MX51_PAD_EIM_A20),
+       IMX_PINCTRL_PIN(MX51_PAD_EIM_A21),
+       IMX_PINCTRL_PIN(MX51_PAD_EIM_A22),
+       IMX_PINCTRL_PIN(MX51_PAD_EIM_A23),
+       IMX_PINCTRL_PIN(MX51_PAD_EIM_A24),
+       IMX_PINCTRL_PIN(MX51_PAD_EIM_A25),
+       IMX_PINCTRL_PIN(MX51_PAD_EIM_A26),
+       IMX_PINCTRL_PIN(MX51_PAD_EIM_A27),
+       IMX_PINCTRL_PIN(MX51_PAD_EIM_EB0),
+       IMX_PINCTRL_PIN(MX51_PAD_EIM_EB1),
+       IMX_PINCTRL_PIN(MX51_PAD_EIM_EB2),
+       IMX_PINCTRL_PIN(MX51_PAD_EIM_EB3),
+       IMX_PINCTRL_PIN(MX51_PAD_EIM_OE),
+       IMX_PINCTRL_PIN(MX51_PAD_EIM_CS0),
+       IMX_PINCTRL_PIN(MX51_PAD_EIM_CS1),
+       IMX_PINCTRL_PIN(MX51_PAD_EIM_CS2),
+       IMX_PINCTRL_PIN(MX51_PAD_EIM_CS3),
+       IMX_PINCTRL_PIN(MX51_PAD_EIM_CS4),
+       IMX_PINCTRL_PIN(MX51_PAD_EIM_CS5),
+       IMX_PINCTRL_PIN(MX51_PAD_EIM_DTACK),
+       IMX_PINCTRL_PIN(MX51_PAD_EIM_LBA),
+       IMX_PINCTRL_PIN(MX51_PAD_EIM_CRE),
+       IMX_PINCTRL_PIN(MX51_PAD_DRAM_CS1),
+       IMX_PINCTRL_PIN(MX51_PAD_NANDF_WE_B),
+       IMX_PINCTRL_PIN(MX51_PAD_NANDF_RE_B),
+       IMX_PINCTRL_PIN(MX51_PAD_NANDF_ALE),
+       IMX_PINCTRL_PIN(MX51_PAD_NANDF_CLE),
+       IMX_PINCTRL_PIN(MX51_PAD_NANDF_WP_B),
+       IMX_PINCTRL_PIN(MX51_PAD_NANDF_RB0),
+       IMX_PINCTRL_PIN(MX51_PAD_NANDF_RB1),
+       IMX_PINCTRL_PIN(MX51_PAD_NANDF_RB2),
+       IMX_PINCTRL_PIN(MX51_PAD_NANDF_RB3),
+       IMX_PINCTRL_PIN(MX51_PAD_GPIO_NAND),
+       IMX_PINCTRL_PIN(MX51_PAD_NANDF_CS0),
+       IMX_PINCTRL_PIN(MX51_PAD_NANDF_CS1),
+       IMX_PINCTRL_PIN(MX51_PAD_NANDF_CS2),
+       IMX_PINCTRL_PIN(MX51_PAD_NANDF_CS3),
+       IMX_PINCTRL_PIN(MX51_PAD_NANDF_CS4),
+       IMX_PINCTRL_PIN(MX51_PAD_NANDF_CS5),
+       IMX_PINCTRL_PIN(MX51_PAD_NANDF_CS6),
+       IMX_PINCTRL_PIN(MX51_PAD_NANDF_CS7),
+       IMX_PINCTRL_PIN(MX51_PAD_NANDF_RDY_INT),
+       IMX_PINCTRL_PIN(MX51_PAD_NANDF_D15),
+       IMX_PINCTRL_PIN(MX51_PAD_NANDF_D14),
+       IMX_PINCTRL_PIN(MX51_PAD_NANDF_D13),
+       IMX_PINCTRL_PIN(MX51_PAD_NANDF_D12),
+       IMX_PINCTRL_PIN(MX51_PAD_NANDF_D11),
+       IMX_PINCTRL_PIN(MX51_PAD_NANDF_D10),
+       IMX_PINCTRL_PIN(MX51_PAD_NANDF_D9),
+       IMX_PINCTRL_PIN(MX51_PAD_NANDF_D8),
+       IMX_PINCTRL_PIN(MX51_PAD_NANDF_D7),
+       IMX_PINCTRL_PIN(MX51_PAD_NANDF_D6),
+       IMX_PINCTRL_PIN(MX51_PAD_NANDF_D5),
+       IMX_PINCTRL_PIN(MX51_PAD_NANDF_D4),
+       IMX_PINCTRL_PIN(MX51_PAD_NANDF_D3),
+       IMX_PINCTRL_PIN(MX51_PAD_NANDF_D2),
+       IMX_PINCTRL_PIN(MX51_PAD_NANDF_D1),
+       IMX_PINCTRL_PIN(MX51_PAD_NANDF_D0),
+       IMX_PINCTRL_PIN(MX51_PAD_CSI1_D8),
+       IMX_PINCTRL_PIN(MX51_PAD_CSI1_D9),
+       IMX_PINCTRL_PIN(MX51_PAD_CSI1_D10),
+       IMX_PINCTRL_PIN(MX51_PAD_CSI1_D11),
+       IMX_PINCTRL_PIN(MX51_PAD_CSI1_D12),
+       IMX_PINCTRL_PIN(MX51_PAD_CSI1_D13),
+       IMX_PINCTRL_PIN(MX51_PAD_CSI1_D14),
+       IMX_PINCTRL_PIN(MX51_PAD_CSI1_D15),
+       IMX_PINCTRL_PIN(MX51_PAD_CSI1_D16),
+       IMX_PINCTRL_PIN(MX51_PAD_CSI1_D17),
+       IMX_PINCTRL_PIN(MX51_PAD_CSI1_D18),
+       IMX_PINCTRL_PIN(MX51_PAD_CSI1_D19),
+       IMX_PINCTRL_PIN(MX51_PAD_CSI1_VSYNC),
+       IMX_PINCTRL_PIN(MX51_PAD_CSI1_HSYNC),
+       IMX_PINCTRL_PIN(MX51_PAD_CSI1_PIXCLK),
+       IMX_PINCTRL_PIN(MX51_PAD_CSI1_MCLK),
+       IMX_PINCTRL_PIN(MX51_PAD_CSI2_D12),
+       IMX_PINCTRL_PIN(MX51_PAD_CSI2_D13),
+       IMX_PINCTRL_PIN(MX51_PAD_CSI2_D14),
+       IMX_PINCTRL_PIN(MX51_PAD_CSI2_D15),
+       IMX_PINCTRL_PIN(MX51_PAD_CSI2_D16),
+       IMX_PINCTRL_PIN(MX51_PAD_CSI2_D17),
+       IMX_PINCTRL_PIN(MX51_PAD_CSI2_D18),
+       IMX_PINCTRL_PIN(MX51_PAD_CSI2_D19),
+       IMX_PINCTRL_PIN(MX51_PAD_CSI2_VSYNC),
+       IMX_PINCTRL_PIN(MX51_PAD_CSI2_HSYNC),
+       IMX_PINCTRL_PIN(MX51_PAD_CSI2_PIXCLK),
+       IMX_PINCTRL_PIN(MX51_PAD_I2C1_CLK),
+       IMX_PINCTRL_PIN(MX51_PAD_I2C1_DAT),
+       IMX_PINCTRL_PIN(MX51_PAD_AUD3_BB_TXD),
+       IMX_PINCTRL_PIN(MX51_PAD_AUD3_BB_RXD),
+       IMX_PINCTRL_PIN(MX51_PAD_AUD3_BB_CK),
+       IMX_PINCTRL_PIN(MX51_PAD_AUD3_BB_FS),
+       IMX_PINCTRL_PIN(MX51_PAD_CSPI1_MOSI),
+       IMX_PINCTRL_PIN(MX51_PAD_CSPI1_MISO),
+       IMX_PINCTRL_PIN(MX51_PAD_CSPI1_SS0),
+       IMX_PINCTRL_PIN(MX51_PAD_CSPI1_SS1),
+       IMX_PINCTRL_PIN(MX51_PAD_CSPI1_RDY),
+       IMX_PINCTRL_PIN(MX51_PAD_CSPI1_SCLK),
+       IMX_PINCTRL_PIN(MX51_PAD_UART1_RXD),
+       IMX_PINCTRL_PIN(MX51_PAD_UART1_TXD),
+       IMX_PINCTRL_PIN(MX51_PAD_UART1_RTS),
+       IMX_PINCTRL_PIN(MX51_PAD_UART1_CTS),
+       IMX_PINCTRL_PIN(MX51_PAD_UART2_RXD),
+       IMX_PINCTRL_PIN(MX51_PAD_UART2_TXD),
+       IMX_PINCTRL_PIN(MX51_PAD_UART3_RXD),
+       IMX_PINCTRL_PIN(MX51_PAD_UART3_TXD),
+       IMX_PINCTRL_PIN(MX51_PAD_OWIRE_LINE),
+       IMX_PINCTRL_PIN(MX51_PAD_KEY_ROW0),
+       IMX_PINCTRL_PIN(MX51_PAD_KEY_ROW1),
+       IMX_PINCTRL_PIN(MX51_PAD_KEY_ROW2),
+       IMX_PINCTRL_PIN(MX51_PAD_KEY_ROW3),
+       IMX_PINCTRL_PIN(MX51_PAD_KEY_COL0),
+       IMX_PINCTRL_PIN(MX51_PAD_KEY_COL1),
+       IMX_PINCTRL_PIN(MX51_PAD_KEY_COL2),
+       IMX_PINCTRL_PIN(MX51_PAD_KEY_COL3),
+       IMX_PINCTRL_PIN(MX51_PAD_KEY_COL4),
+       IMX_PINCTRL_PIN(MX51_PAD_KEY_COL5),
+       IMX_PINCTRL_PIN(MX51_PAD_USBH1_CLK),
+       IMX_PINCTRL_PIN(MX51_PAD_USBH1_DIR),
+       IMX_PINCTRL_PIN(MX51_PAD_USBH1_STP),
+       IMX_PINCTRL_PIN(MX51_PAD_USBH1_NXT),
+       IMX_PINCTRL_PIN(MX51_PAD_USBH1_DATA0),
+       IMX_PINCTRL_PIN(MX51_PAD_USBH1_DATA1),
+       IMX_PINCTRL_PIN(MX51_PAD_USBH1_DATA2),
+       IMX_PINCTRL_PIN(MX51_PAD_USBH1_DATA3),
+       IMX_PINCTRL_PIN(MX51_PAD_USBH1_DATA4),
+       IMX_PINCTRL_PIN(MX51_PAD_USBH1_DATA5),
+       IMX_PINCTRL_PIN(MX51_PAD_USBH1_DATA6),
+       IMX_PINCTRL_PIN(MX51_PAD_USBH1_DATA7),
+       IMX_PINCTRL_PIN(MX51_PAD_DI1_PIN11),
+       IMX_PINCTRL_PIN(MX51_PAD_DI1_PIN12),
+       IMX_PINCTRL_PIN(MX51_PAD_DI1_PIN13),
+       IMX_PINCTRL_PIN(MX51_PAD_DI1_D0_CS),
+       IMX_PINCTRL_PIN(MX51_PAD_DI1_D1_CS),
+       IMX_PINCTRL_PIN(MX51_PAD_DISPB2_SER_DIN),
+       IMX_PINCTRL_PIN(MX51_PAD_DISPB2_SER_DIO),
+       IMX_PINCTRL_PIN(MX51_PAD_DISPB2_SER_CLK),
+       IMX_PINCTRL_PIN(MX51_PAD_DISPB2_SER_RS),
+       IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT0),
+       IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT1),
+       IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT2),
+       IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT3),
+       IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT4),
+       IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT5),
+       IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT6),
+       IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT7),
+       IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT8),
+       IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT9),
+       IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT10),
+       IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT11),
+       IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT12),
+       IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT13),
+       IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT14),
+       IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT15),
+       IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT16),
+       IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT17),
+       IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT18),
+       IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT19),
+       IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT20),
+       IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT21),
+       IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT22),
+       IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT23),
+       IMX_PINCTRL_PIN(MX51_PAD_DI1_PIN3),
+       IMX_PINCTRL_PIN(MX51_PAD_DI1_PIN2),
+       IMX_PINCTRL_PIN(MX51_PAD_DI_GP2),
+       IMX_PINCTRL_PIN(MX51_PAD_DI_GP3),
+       IMX_PINCTRL_PIN(MX51_PAD_DI2_PIN4),
+       IMX_PINCTRL_PIN(MX51_PAD_DI2_PIN2),
+       IMX_PINCTRL_PIN(MX51_PAD_DI2_PIN3),
+       IMX_PINCTRL_PIN(MX51_PAD_DI2_DISP_CLK),
+       IMX_PINCTRL_PIN(MX51_PAD_DI_GP4),
+       IMX_PINCTRL_PIN(MX51_PAD_DISP2_DAT0),
+       IMX_PINCTRL_PIN(MX51_PAD_DISP2_DAT1),
+       IMX_PINCTRL_PIN(MX51_PAD_DISP2_DAT2),
+       IMX_PINCTRL_PIN(MX51_PAD_DISP2_DAT3),
+       IMX_PINCTRL_PIN(MX51_PAD_DISP2_DAT4),
+       IMX_PINCTRL_PIN(MX51_PAD_DISP2_DAT5),
+       IMX_PINCTRL_PIN(MX51_PAD_DISP2_DAT6),
+       IMX_PINCTRL_PIN(MX51_PAD_DISP2_DAT7),
+       IMX_PINCTRL_PIN(MX51_PAD_DISP2_DAT8),
+       IMX_PINCTRL_PIN(MX51_PAD_DISP2_DAT9),
+       IMX_PINCTRL_PIN(MX51_PAD_DISP2_DAT10),
+       IMX_PINCTRL_PIN(MX51_PAD_DISP2_DAT11),
+       IMX_PINCTRL_PIN(MX51_PAD_DISP2_DAT12),
+       IMX_PINCTRL_PIN(MX51_PAD_DISP2_DAT13),
+       IMX_PINCTRL_PIN(MX51_PAD_DISP2_DAT14),
+       IMX_PINCTRL_PIN(MX51_PAD_DISP2_DAT15),
+       IMX_PINCTRL_PIN(MX51_PAD_SD1_CMD),
+       IMX_PINCTRL_PIN(MX51_PAD_SD1_CLK),
+       IMX_PINCTRL_PIN(MX51_PAD_SD1_DATA0),
+       IMX_PINCTRL_PIN(MX51_PAD_EIM_DA0),
+       IMX_PINCTRL_PIN(MX51_PAD_EIM_DA1),
+       IMX_PINCTRL_PIN(MX51_PAD_EIM_DA2),
+       IMX_PINCTRL_PIN(MX51_PAD_EIM_DA3),
+       IMX_PINCTRL_PIN(MX51_PAD_SD1_DATA1),
+       IMX_PINCTRL_PIN(MX51_PAD_EIM_DA4),
+       IMX_PINCTRL_PIN(MX51_PAD_EIM_DA5),
+       IMX_PINCTRL_PIN(MX51_PAD_EIM_DA6),
+       IMX_PINCTRL_PIN(MX51_PAD_EIM_DA7),
+       IMX_PINCTRL_PIN(MX51_PAD_SD1_DATA2),
+       IMX_PINCTRL_PIN(MX51_PAD_EIM_DA10),
+       IMX_PINCTRL_PIN(MX51_PAD_EIM_DA11),
+       IMX_PINCTRL_PIN(MX51_PAD_EIM_DA8),
+       IMX_PINCTRL_PIN(MX51_PAD_EIM_DA9),
+       IMX_PINCTRL_PIN(MX51_PAD_SD1_DATA3),
+       IMX_PINCTRL_PIN(MX51_PAD_GPIO1_0),
+       IMX_PINCTRL_PIN(MX51_PAD_GPIO1_1),
+       IMX_PINCTRL_PIN(MX51_PAD_EIM_DA12),
+       IMX_PINCTRL_PIN(MX51_PAD_EIM_DA13),
+       IMX_PINCTRL_PIN(MX51_PAD_EIM_DA14),
+       IMX_PINCTRL_PIN(MX51_PAD_EIM_DA15),
+       IMX_PINCTRL_PIN(MX51_PAD_SD2_CMD),
+       IMX_PINCTRL_PIN(MX51_PAD_SD2_CLK),
+       IMX_PINCTRL_PIN(MX51_PAD_SD2_DATA0),
+       IMX_PINCTRL_PIN(MX51_PAD_SD2_DATA1),
+       IMX_PINCTRL_PIN(MX51_PAD_SD2_DATA2),
+       IMX_PINCTRL_PIN(MX51_PAD_SD2_DATA3),
+       IMX_PINCTRL_PIN(MX51_PAD_GPIO1_2),
+       IMX_PINCTRL_PIN(MX51_PAD_GPIO1_3),
+       IMX_PINCTRL_PIN(MX51_PAD_PMIC_INT_REQ),
+       IMX_PINCTRL_PIN(MX51_PAD_GPIO1_4),
+       IMX_PINCTRL_PIN(MX51_PAD_GPIO1_5),
+       IMX_PINCTRL_PIN(MX51_PAD_GPIO1_6),
+       IMX_PINCTRL_PIN(MX51_PAD_GPIO1_7),
+       IMX_PINCTRL_PIN(MX51_PAD_GPIO1_8),
+       IMX_PINCTRL_PIN(MX51_PAD_GPIO1_9),
+};
+
+static struct imx_pinctrl_soc_info imx51_pinctrl_info = {
+       .pins = imx51_pinctrl_pads,
+       .npins = ARRAY_SIZE(imx51_pinctrl_pads),
+       .pin_regs = imx51_pin_regs,
+       .npin_regs = ARRAY_SIZE(imx51_pin_regs),
+};
+
+static struct of_device_id imx51_pinctrl_of_match[] __devinitdata = {
+       { .compatible = "fsl,imx51-iomuxc", },
+       { /* sentinel */ }
+};
+
+static int __devinit imx51_pinctrl_probe(struct platform_device *pdev)
+{
+       return imx_pinctrl_probe(pdev, &imx51_pinctrl_info);
+}
+
+static struct platform_driver imx51_pinctrl_driver = {
+       .driver = {
+               .name = "imx51-pinctrl",
+               .owner = THIS_MODULE,
+               .of_match_table = of_match_ptr(imx51_pinctrl_of_match),
+       },
+       .probe = imx51_pinctrl_probe,
+       .remove = __devexit_p(imx_pinctrl_remove),
+};
+
+static int __init imx51_pinctrl_init(void)
+{
+       return platform_driver_register(&imx51_pinctrl_driver);
+}
+arch_initcall(imx51_pinctrl_init);
+
+static void __exit imx51_pinctrl_exit(void)
+{
+       platform_driver_unregister(&imx51_pinctrl_driver);
+}
+module_exit(imx51_pinctrl_exit);
+MODULE_AUTHOR("Dong Aisheng <dong.aisheng@linaro.org>");
+MODULE_DESCRIPTION("Freescale IMX51 pinctrl driver");
+MODULE_LICENSE("GPL v2");