Cleaned up a bit the code removing unnecessary defines and structs from Mesa

diff --git a/kernels/test_copy_image.cl b/kernels/test_copy_image.cl
index 647557f..e14ce68 100644 (file)
--- a/kernels/test_copy_image.cl
+++ b/kernels/test_copy_image.cl
@@ -1,6 +1,9 @@
 __constant sampler_t s0 = CLK_NORMALIZED_COORDS_FALSE |
                           CLK_ADDRESS_CLAMP |
                           CLK_FILTER_NEAREST;
+__constant sampler_t s1 = CLK_NORMALIZED_COORDS_TRUE |
+                          CLK_ADDRESS_CLAMP |
+                          CLK_FILTER_NEAREST;
 __kernel void
 test_copy_image(__read_only image2d_t src,
                 __global uchar4 *dst)
@@ -9,6 +12,7 @@ test_copy_image(__read_only image2d_t src,
     const int y = (int) get_global_id(1);
     const int id = x + y * get_image_width(src);
     const uchar4 from = convert_uchar4(read_imageui(src, s0, (int2)(x,y)));
-    dst[id] = from;
+    const uchar4 from0 = convert_uchar4(read_imageui(src, s1, (int2)(x,y)));
+    dst[id] = from + from0;
 }
 

diff --git a/src/intel/intel_defines.h b/src/intel/intel_defines.h
index 753bfc1..4e40f4a 100644 (file)
--- a/src/intel/intel_defines.h
+++ b/src/intel/intel_defines.h
@@ -20,10 +20,10 @@
 #ifndef __GENX_DEFINES_H__
 #define __GENX_DEFINES_H__
 
-#define CMD(pipeline,op,sub_op)                ((3 << 29) | \
-                                  ((pipeline) << 27) | \
-                                  ((op) << 24) | \
-                                  ((sub_op) << 16))
+#define CMD(PIPELINE,OP,SUB_OP) ((3 << 29) |          \
+                                ((PIPELINE) << 27) |  \
+                                ((OP) << 24) |        \
+                                ((SUB_OP) << 16))
 
 #define CMD_URB_FENCE                           CMD(0, 0, 0)
 #define CMD_CS_URB_STATE                        CMD(0, 0, 1)
@@ -57,7 +57,6 @@
 #define PIPELINE_SELECT_3D              0
 #define PIPELINE_SELECT_MEDIA           1
 
-
 #define UF0_CS_REALLOC                  (1 << 13)
 #define UF0_VFE_REALLOC                 (1 << 12)
 #define UF0_SF_REALLOC                  (1 << 11)
@@ -71,16 +70,9 @@
 #define UF2_VFE_FENCE_SHIFT             10
 #define UF2_SF_FENCE_SHIFT              0
 
-#define VFE_GENERIC_MODE        0x0
-#define VFE_VLD_MODE            0x1
-#define VFE_IS_MODE             0x2
-#define VFE_AVC_MC_MODE         0x4
-#define VFE_AVC_IT_MODE         0x7
-
 #define FLOATING_POINT_IEEE_754        0
 #define FLOATING_POINT_NON_IEEE_754    1
 
-
 #define I965_SURFACE_1D      0
 #define I965_SURFACE_2D      1
 #define I965_SURFACE_3D      2
@@ -244,17 +236,12 @@
 #define I965_SURFACEFORMAT_R16G16B16_USCALED              0x19F
 #define I965_SURFACEFORMAT_RAW                            0x1FF
 
-#define I965_CULLMODE_BOTH      0
-#define I965_CULLMODE_NONE      1
-#define I965_CULLMODE_FRONT     2
-#define I965_CULLMODE_BACK      3
-
 #define I965_MAPFILTER_NEAREST        0x0 
 #define I965_MAPFILTER_LINEAR         0x1 
 #define I965_MAPFILTER_ANISOTROPIC    0x2
 
-#define I965_MIPFILTER_NONE        0   
-#define I965_MIPFILTER_NEAREST     1   
+#define I965_MIPFILTER_NONE        0
+#define I965_MIPFILTER_NEAREST     1
 #define I965_MIPFILTER_LINEAR      3
 
 #define I965_TEXCOORDMODE_WRAP            0
@@ -264,88 +251,13 @@
 #define I965_TEXCOORDMODE_CLAMP_BORDER    4
 #define I965_TEXCOORDMODE_MIRROR_ONCE     5
 
-#define I965_BLENDFACTOR_ONE                 0x1
-#define I965_BLENDFACTOR_SRC_COLOR           0x2
-#define I965_BLENDFACTOR_SRC_ALPHA           0x3
-#define I965_BLENDFACTOR_DST_ALPHA           0x4
-#define I965_BLENDFACTOR_DST_COLOR           0x5
-#define I965_BLENDFACTOR_SRC_ALPHA_SATURATE  0x6
-#define I965_BLENDFACTOR_CONST_COLOR         0x7
-#define I965_BLENDFACTOR_CONST_ALPHA         0x8
-#define I965_BLENDFACTOR_SRC1_COLOR          0x9
-#define I965_BLENDFACTOR_SRC1_ALPHA          0x0A
-#define I965_BLENDFACTOR_ZERO                0x11
-#define I965_BLENDFACTOR_INV_SRC_COLOR       0x12
-#define I965_BLENDFACTOR_INV_SRC_ALPHA       0x13
-#define I965_BLENDFACTOR_INV_DST_ALPHA       0x14
-#define I965_BLENDFACTOR_INV_DST_COLOR       0x15
-#define I965_BLENDFACTOR_INV_CONST_COLOR     0x17
-#define I965_BLENDFACTOR_INV_CONST_ALPHA     0x18
-#define I965_BLENDFACTOR_INV_SRC1_COLOR      0x19
-#define I965_BLENDFACTOR_INV_SRC1_ALPHA      0x1A
-
-#define I965_BLENDFUNCTION_ADD               0
-#define I965_BLENDFUNCTION_SUBTRACT          1
-#define I965_BLENDFUNCTION_REVERSE_SUBTRACT  2
-#define I965_BLENDFUNCTION_MIN               3
-#define I965_BLENDFUNCTION_MAX               4
-
 #define I965_SURFACERETURNFORMAT_FLOAT32  0
 #define I965_SURFACERETURNFORMAT_S1       1
 
-#define I965_VFCOMPONENT_NOSTORE      0
-#define I965_VFCOMPONENT_STORE_SRC    1
-#define I965_VFCOMPONENT_STORE_0      2
-#define I965_VFCOMPONENT_STORE_1_FLT  3
-#define I965_VFCOMPONENT_STORE_1_INT  4
-#define I965_VFCOMPONENT_STORE_VID    5
-#define I965_VFCOMPONENT_STORE_IID    6
-#define I965_VFCOMPONENT_STORE_PID    7
-
-#define VE0_VERTEX_BUFFER_INDEX_SHIFT  27
-#define VE0_VALID                      (1 << 26)
-#define VE0_FORMAT_SHIFT               16
-#define VE0_OFFSET_SHIFT               0
-#define VE1_VFCOMPONENT_0_SHIFT                28
-#define VE1_VFCOMPONENT_1_SHIFT                24
-#define VE1_VFCOMPONENT_2_SHIFT                20
-#define VE1_VFCOMPONENT_3_SHIFT                16
-#define VE1_DESTINATION_ELEMENT_OFFSET_SHIFT   0
-
-#define VB0_BUFFER_INDEX_SHIFT          27
-#define VB0_VERTEXDATA                  (0 << 26)
-#define VB0_INSTANCEDATA                (1 << 26)
-#define VB0_BUFFER_PITCH_SHIFT          0
-
-#define _3DPRIMITIVE_VERTEX_SEQUENTIAL  (0 << 15)
-#define _3DPRIMITIVE_VERTEX_RANDOM      (1 << 15)
-#define _3DPRIMITIVE_TOPOLOGY_SHIFT     10
-
-#define _3DPRIM_POINTLIST         0x01
-#define _3DPRIM_LINELIST          0x02
-#define _3DPRIM_LINESTRIP         0x03
-#define _3DPRIM_TRILIST           0x04
-#define _3DPRIM_TRISTRIP          0x05
-#define _3DPRIM_TRIFAN            0x06
-#define _3DPRIM_QUADLIST          0x07
-#define _3DPRIM_QUADSTRIP         0x08
-#define _3DPRIM_LINELIST_ADJ      0x09
-#define _3DPRIM_LINESTRIP_ADJ     0x0A
-#define _3DPRIM_TRILIST_ADJ       0x0B
-#define _3DPRIM_TRISTRIP_ADJ      0x0C
-#define _3DPRIM_TRISTRIP_REVERSE  0x0D
-#define _3DPRIM_POLYGON           0x0E
-#define _3DPRIM_RECTLIST          0x0F
-#define _3DPRIM_LINELOOP          0x10
-#define _3DPRIM_POINTLIST_BF      0x11
-#define _3DPRIM_LINESTRIP_CONT    0x12
-#define _3DPRIM_LINESTRIP_BF      0x13
-#define _3DPRIM_LINESTRIP_CONT_BF 0x14
-#define _3DPRIM_TRIFAN_NOSTIPPLE  0x15
-
 #define I965_TILEWALK_XMAJOR                 0
 #define I965_TILEWALK_YMAJOR                 1
 
 #define URB_SIZE(intel)         (IS_IGDNG(intel->device_id) ? 1024 : \
                                  IS_G4X(intel->device_id) ? 384 : 256)
 #endif /* __GENX_DEFINES_H__ */
+

diff --git a/src/intel/intel_gpgpu.c b/src/intel/intel_gpgpu.c
index 92a6116..a4b476b 100644 (file)
--- a/src/intel/intel_gpgpu.c
+++ b/src/intel/intel_gpgpu.c
@@ -778,28 +778,6 @@ gpgpu_bind_buf(intel_gpgpu_t *state,
 
 }
 
-LOCAL void
-gpgpu_set_sampler(intel_gpgpu_t *state, uint32_t index, uint32_t non_normalized)
-{
-  struct i965_sampler_state *sampler = NULL;
-  assert(index < (int) MAX_SAMPLERS);
-
-#ifndef NDEBUG
-  if (non_normalized && state->drv->gen_ver == 5)
-    assert("Non normalized coordinates are unsupported on Gen5" && 0);
-#endif /* NDEBUG */
-
-  sampler = (struct i965_sampler_state *) state->samplers[index].opaque;
-  if (non_normalized) {
-    sampler->ss3.gen6_non_normalized = 1;
-    sampler->ss1.r_wrap_mode = I965_TEXCOORDMODE_CLAMP;
-    sampler->ss1.t_wrap_mode = I965_TEXCOORDMODE_CLAMP;
-    sampler->ss1.s_wrap_mode = I965_TEXCOORDMODE_CLAMP;
-  }
-  else
-    sampler->ss3.gen6_non_normalized = 0;
-}
-
 static void
 gpgpu_build_sampler_table(intel_gpgpu_t *state)
 {

diff --git a/src/intel/intel_gpgpu.h b/src/intel/intel_gpgpu.h
index b6a820d..3ab7274 100644 (file)
--- a/src/intel/intel_gpgpu.h
+++ b/src/intel/intel_gpgpu.h
@@ -32,7 +32,7 @@ enum gen6_cache_control {
   cc_llc_mlc    = 0x3,
 };
 
-#define MAX_SURFACES   128 
+#define MAX_SURFACES   128
 #define MAX_SAMPLERS   16
 
 /* Use this structure to bind kernels in the gpgpu state */

diff --git a/src/intel/intel_structs.h b/src/intel/intel_structs.h
index 7b873dd..f19c1b9 100644 (file)
--- a/src/intel/intel_structs.h
+++ b/src/intel/intel_structs.h
@@ -247,400 +247,6 @@ struct i965_surface_state
   } ss5;
 };
 
-struct thread0
-{
-  uint32_t pad0:1;
-  uint32_t grf_reg_count:3; 
-  uint32_t pad1:2;
-  uint32_t kernel_start_pointer:26; 
-};
-
-struct thread1
-{
-  uint32_t ext_halt_exception_enable:1; 
-  uint32_t sw_exception_enable:1; 
-  uint32_t mask_stack_exception_enable:1; 
-  uint32_t timeout_exception_enable:1; 
-  uint32_t illegal_op_exception_enable:1; 
-  uint32_t pad0:3;
-  uint32_t depth_coef_urb_read_offset:6;       /* WM only */
-  uint32_t pad1:2;
-  uint32_t floating_point_mode:1; 
-  uint32_t thread_priority:1; 
-  uint32_t binding_table_entry_count:8; 
-  uint32_t pad3:5;
-  uint32_t single_program_flow:1; 
-};
-
-struct thread2
-{
-  uint32_t per_thread_scratch_space:4; 
-  uint32_t pad0:6;
-  uint32_t scratch_space_base_pointer:22; 
-};
-
-struct thread3
-{
-  uint32_t dispatch_grf_start_reg:4; 
-  uint32_t urb_entry_read_offset:6; 
-  uint32_t pad0:1;
-  uint32_t urb_entry_read_length:6; 
-  uint32_t pad1:1;
-  uint32_t const_urb_entry_read_offset:6; 
-  uint32_t pad2:1;
-  uint32_t const_urb_entry_read_length:6; 
-  uint32_t pad3:1;
-};
-
-struct i965_vs_unit_state
-{
-  struct thread0 thread0;
-  struct thread1 thread1;
-  struct thread2 thread2;
-  struct thread3 thread3;
-
-  struct {
-    uint32_t pad0:10;
-    uint32_t stats_enable:1; 
-    uint32_t nr_urb_entries:7; 
-    uint32_t pad1:1;
-    uint32_t urb_entry_allocation_size:5; 
-    uint32_t pad2:1;
-    uint32_t max_threads:4; 
-    uint32_t pad3:3;
-  } thread4;   
-
-  struct {
-    uint32_t sampler_count:3; 
-    uint32_t pad0:2;
-    uint32_t sampler_state_pointer:27; 
-  } vs5;
-
-  struct {
-    uint32_t vs_enable:1; 
-    uint32_t vert_cache_disable:1; 
-    uint32_t pad0:30;
-  } vs6;
-};
-
-struct i965_gs_unit_state
-{
-  struct thread0 thread0;
-  struct thread1 thread1;
-  struct thread2 thread2;
-  struct thread3 thread3;
-
-  struct {
-    uint32_t pad0:10;
-    uint32_t stats_enable:1; 
-    uint32_t nr_urb_entries:7; 
-    uint32_t pad1:1;
-    uint32_t urb_entry_allocation_size:5; 
-    uint32_t pad2:1;
-    uint32_t max_threads:1; 
-    uint32_t pad3:6;
-  } thread4;   
-
-  struct {
-    uint32_t sampler_count:3; 
-    uint32_t pad0:2;
-    uint32_t sampler_state_pointer:27; 
-  } gs5;
-
-
-  struct {
-    uint32_t max_vp_index:4; 
-    uint32_t pad0:26;
-    uint32_t reorder_enable:1; 
-    uint32_t pad1:1;
-  } gs6;
-};
-
-struct i965_clip_unit_state
-{
-  struct thread0 thread0;
-  struct thread1 thread1;
-  struct thread2 thread2;
-  struct thread3 thread3;
-
-  struct {
-    uint32_t pad0:9;
-    uint32_t gs_output_stats:1; /* not always */
-    uint32_t stats_enable:1; 
-    uint32_t nr_urb_entries:7; 
-    uint32_t pad1:1;
-    uint32_t urb_entry_allocation_size:5; 
-    uint32_t pad2:1;
-    uint32_t max_threads:6;    /* may be less */
-    uint32_t pad3:1;
-  } thread4;   
-
-  struct {
-    uint32_t pad0:13;
-    uint32_t clip_mode:3; 
-    uint32_t userclip_enable_flags:8; 
-    uint32_t userclip_must_clip:1; 
-    uint32_t pad1:1;
-    uint32_t guard_band_enable:1; 
-    uint32_t viewport_z_clip_enable:1; 
-    uint32_t viewport_xy_clip_enable:1; 
-    uint32_t vertex_position_space:1; 
-    uint32_t api_mode:1; 
-    uint32_t pad2:1;
-  } clip5;
-
-  struct {
-    uint32_t pad0:5;
-    uint32_t clipper_viewport_state_ptr:27; 
-  } clip6;
-
-
-  float viewport_xmin;  
-  float viewport_xmax;  
-  float viewport_ymin;  
-  float viewport_ymax;  
-};
-
-struct i965_sf_unit_state
-{
-  struct thread0 thread0;
-  struct {
-    uint32_t pad0:7;
-    uint32_t sw_exception_enable:1; 
-    uint32_t pad1:3;
-    uint32_t mask_stack_exception_enable:1; 
-    uint32_t pad2:1;
-    uint32_t illegal_op_exception_enable:1; 
-    uint32_t pad3:2;
-    uint32_t floating_point_mode:1; 
-    uint32_t thread_priority:1; 
-    uint32_t binding_table_entry_count:8; 
-    uint32_t pad4:5;
-    uint32_t single_program_flow:1; 
-  } sf1;
-
-  struct thread2 thread2;
-  struct thread3 thread3;
-
-  struct {
-    uint32_t pad0:10;
-    uint32_t stats_enable:1; 
-    uint32_t nr_urb_entries:7; 
-    uint32_t pad1:1;
-    uint32_t urb_entry_allocation_size:5; 
-    uint32_t pad2:1;
-    uint32_t max_threads:6; 
-    uint32_t pad3:1;
-  } thread4;   
-
-  struct {
-    uint32_t front_winding:1; 
-    uint32_t viewport_transform:1; 
-    uint32_t pad0:3;
-    uint32_t sf_viewport_state_offset:27; 
-  } sf5;
-
-  struct {
-    uint32_t pad0:9;
-    uint32_t dest_org_vbias:4; 
-    uint32_t dest_org_hbias:4; 
-    uint32_t scissor:1; 
-    uint32_t disable_2x2_trifilter:1; 
-    uint32_t disable_zero_pix_trifilter:1; 
-    uint32_t point_rast_rule:2; 
-    uint32_t line_endcap_aa_region_width:2; 
-    uint32_t line_width:4; 
-    uint32_t fast_scissor_disable:1; 
-    uint32_t cull_mode:2; 
-    uint32_t aa_enable:1; 
-  } sf6;
-
-  struct {
-    uint32_t point_size:11; 
-    uint32_t use_point_size_state:1; 
-    uint32_t subpixel_precision:1; 
-    uint32_t sprite_point:1; 
-    uint32_t pad0:11;
-    uint32_t trifan_pv:2; 
-    uint32_t linestrip_pv:2; 
-    uint32_t tristrip_pv:2; 
-    uint32_t line_last_pixel_enable:1; 
-  } sf7;
-};
-
-struct i965_sampler_state
-{
-  struct {
-    uint32_t shadow_function:3; 
-    uint32_t lod_bias:11; 
-    uint32_t min_filter:3; 
-    uint32_t mag_filter:3; 
-    uint32_t mip_filter:2; 
-    uint32_t base_level:5; 
-    uint32_t pad:1;
-    uint32_t lod_preclamp:1; 
-    uint32_t border_color_mode:1; 
-    uint32_t pad0:1;
-    uint32_t disable:1; 
-  } ss0;
-
-  struct {
-    uint32_t r_wrap_mode:3; 
-    uint32_t t_wrap_mode:3; 
-    uint32_t s_wrap_mode:3; 
-    uint32_t pad:3;
-    uint32_t max_lod:10; 
-    uint32_t min_lod:10; 
-  } ss1;
-
-
-  struct {
-    uint32_t pad:5;
-    uint32_t border_color_pointer:27; 
-  } ss2;
-
-  struct {
-    uint32_t gen6_non_normalized:1;
-    uint32_t pad:18;
-    uint32_t max_aniso:3; 
-    uint32_t chroma_key_mode:1; 
-    uint32_t chroma_key_index:2; 
-    uint32_t chroma_key_enable:1; 
-    uint32_t monochrome_filter_width:3; 
-    uint32_t monochrome_filter_height:3; 
-  } ss3;
-};
-
-struct i965_wm_unit_state
-{
-  struct thread0 thread0;
-  struct thread1 thread1;
-  struct thread2 thread2;
-  struct thread3 thread3;
-
-  struct {
-    uint32_t stats_enable:1; 
-    uint32_t pad0:1;
-    uint32_t sampler_count:3; 
-    uint32_t sampler_state_pointer:27; 
-  } wm4;
-
-  struct {
-    uint32_t enable_8_pix:1; 
-    uint32_t enable_16_pix:1; 
-    uint32_t enable_32_pix:1; 
-    uint32_t pad0:7;
-    uint32_t legacy_global_depth_bias:1; 
-    uint32_t line_stipple:1; 
-    uint32_t depth_offset:1; 
-    uint32_t polygon_stipple:1; 
-    uint32_t line_aa_region_width:2; 
-    uint32_t line_endcap_aa_region_width:2; 
-    uint32_t early_depth_test:1; 
-    uint32_t thread_dispatch_enable:1; 
-    uint32_t program_uses_depth:1; 
-    uint32_t program_computes_depth:1; 
-    uint32_t program_uses_killpixel:1; 
-    uint32_t legacy_line_rast: 1; 
-    uint32_t transposed_urb_read:1; 
-    uint32_t max_threads:7; 
-  } wm5;
-
-  float global_depth_offset_constant;  
-  float global_depth_offset_scale;   
-};
-
-struct i965_cc_viewport
-{
-  float min_depth;  
-  float max_depth;  
-};
-
-struct i965_cc_unit_state
-{
-  struct {
-    uint32_t pad0:3;
-    uint32_t bf_stencil_pass_depth_pass_op:3; 
-    uint32_t bf_stencil_pass_depth_fail_op:3; 
-    uint32_t bf_stencil_fail_op:3; 
-    uint32_t bf_stencil_func:3; 
-    uint32_t bf_stencil_enable:1; 
-    uint32_t pad1:2;
-    uint32_t stencil_write_enable:1; 
-    uint32_t stencil_pass_depth_pass_op:3; 
-    uint32_t stencil_pass_depth_fail_op:3; 
-    uint32_t stencil_fail_op:3; 
-    uint32_t stencil_func:3; 
-    uint32_t stencil_enable:1; 
-  } cc0;
-
-
-  struct {
-    uint32_t bf_stencil_ref:8; 
-    uint32_t stencil_write_mask:8; 
-    uint32_t stencil_test_mask:8; 
-    uint32_t stencil_ref:8; 
-  } cc1;
-
-
-  struct {
-    uint32_t logicop_enable:1; 
-    uint32_t pad0:10;
-    uint32_t depth_write_enable:1; 
-    uint32_t depth_test_function:3; 
-    uint32_t depth_test:1; 
-    uint32_t bf_stencil_write_mask:8; 
-    uint32_t bf_stencil_test_mask:8; 
-  } cc2;
-
-
-  struct {
-    uint32_t pad0:8;
-    uint32_t alpha_test_func:3; 
-    uint32_t alpha_test:1; 
-    uint32_t blend_enable:1; 
-    uint32_t ia_blend_enable:1; 
-    uint32_t pad1:1;
-    uint32_t alpha_test_format:1;
-    uint32_t pad2:16;
-  } cc3;
-
-  struct {
-    uint32_t pad0:5; 
-    uint32_t cc_viewport_state_offset:27; 
-  } cc4;
-
-  struct {
-    uint32_t pad0:2;
-    uint32_t ia_dest_blend_factor:5; 
-    uint32_t ia_src_blend_factor:5; 
-    uint32_t ia_blend_function:3; 
-    uint32_t statistics_enable:1; 
-    uint32_t logicop_func:4; 
-    uint32_t pad1:11;
-    uint32_t dither_enable:1; 
-  } cc5;
-
-  struct {
-    uint32_t clamp_post_alpha_blend:1; 
-    uint32_t clamp_pre_alpha_blend:1; 
-    uint32_t clamp_range:2; 
-    uint32_t pad0:11;
-    uint32_t y_dither_offset:2; 
-    uint32_t x_dither_offset:2; 
-    uint32_t dest_blend_factor:5; 
-    uint32_t src_blend_factor:5; 
-    uint32_t blend_function:3; 
-  } cc6;
-
-  struct {
-    union {
-      float f;  
-      unsigned char ub[4];
-    } alpha_ref;
-  } cc7;
-};
-
 #define BITFIELD_BIT(X) 1
 #define BITFIELD_RANGE(X,Y) ((Y) - (X) + 1)
 
@@ -696,6 +302,104 @@ typedef struct i965_pipe_control
   } qw0;
 } i965_pipe_control_t;
 
+typedef struct i965_sampler_state
+{
+  struct
+  {
+    uint32_t shadow_function:3; 
+    uint32_t lod_bias:11; 
+    uint32_t min_filter:3; 
+    uint32_t mag_filter:3; 
+    uint32_t mip_filter:2; 
+    uint32_t base_level:5; 
+    uint32_t min_mag_neq:1;
+    uint32_t lod_preclamp:1; 
+    uint32_t default_color_mode:1; 
+    uint32_t pad0:1;
+    uint32_t disable:1; 
+  } ss0;
+
+  struct
+  {
+    uint32_t r_wrap_mode:3; 
+    uint32_t t_wrap_mode:3; 
+    uint32_t s_wrap_mode:3; 
+    uint32_t cube_control_mode:1;
+    uint32_t pad:2;
+    uint32_t max_lod:10; 
+    uint32_t min_lod:10; 
+  } ss1;
+
+
+  struct
+  {
+    uint32_t pad:5;
+    uint32_t default_color_pointer:27; 
+  } ss2;
+
+  struct
+  {
+    uint32_t non_normalized_coord:1;
+    uint32_t pad:12;
+    uint32_t address_round:6;
+    uint32_t max_aniso:3; 
+    uint32_t chroma_key_mode:1; 
+    uint32_t chroma_key_index:2; 
+    uint32_t chroma_key_enable:1; 
+    uint32_t monochrome_filter_width:3; 
+    uint32_t monochrome_filter_height:3; 
+  } ss3;
+} i965_sampler_state_t;
+
+typedef struct gen7_sampler_state
+{
+  struct
+  {
+    uint32_t aniso_algorithm:1;
+    uint32_t lod_bias:13;
+    uint32_t min_filter:3;
+    uint32_t mag_filter:3;
+    uint32_t mip_filter:2;
+    uint32_t base_level:5;
+    uint32_t pad1:1;
+    uint32_t lod_preclamp:1;
+    uint32_t default_color_mode:1;
+    uint32_t pad0:1;
+    uint32_t disable:1;
+  } ss0;
+
+  struct
+  {
+    uint32_t cube_control_mode:1;
+    uint32_t shadow_function:3;
+    uint32_t pad:4;
+    uint32_t max_lod:12;
+    uint32_t min_lod:12;
+  } ss1;
+
+  struct
+  {
+    uint32_t pad:5;
+    uint32_t default_color_pointer:27;
+  } ss2;
+
+  struct
+  {
+    uint32_t r_wrap_mode:3;
+    uint32_t t_wrap_mode:3;
+    uint32_t s_wrap_mode:3;
+    uint32_t pad:1;
+    uint32_t non_normalized_coord:1;
+    uint32_t trilinear_quality:2;
+    uint32_t address_round:6;
+    uint32_t max_aniso:3;
+    uint32_t chroma_key_mode:1;
+    uint32_t chroma_key_index:2;
+    uint32_t chroma_key_enable:1;
+    uint32_t pad0:6;
+  } ss3;
+} gen7_sampler_state_t;
+
 #undef BITFIELD_BIT
 #undef BITFIELD_RANGE