Fix alignment of arm64 fpu register context structure
authorJason Molenda <jmolenda@apple.com>
Thu, 16 Nov 2017 00:50:29 +0000 (00:50 +0000)
committerJason Molenda <jmolenda@apple.com>
Thu, 16 Nov 2017 00:50:29 +0000 (00:50 +0000)
so it has the same padding as the kernel's definition
which is written in terms of uint128_t.  Original patch
by Ryan Mansfield.

<rdar://problem/35468499>

llvm-svn: 318357

lldb/source/Plugins/ObjectFile/Mach-O/ObjectFileMachO.cpp
lldb/source/Plugins/Process/Utility/RegisterContextDarwin_arm64.cpp
lldb/source/Plugins/Process/Utility/RegisterContextDarwin_arm64.h

index 0b62591..df334f8 100644 (file)
@@ -686,7 +686,7 @@ public:
       case FPURegSet: {
         uint8_t *fpu_reg_buf = (uint8_t *)&fpu.v[0];
         const int fpu_reg_buf_size = sizeof(fpu);
-        if (fpu_reg_buf_size == count &&
+        if (fpu_reg_buf_size == count * sizeof(uint32_t) &&
             data.ExtractBytes(offset, fpu_reg_buf_size, eByteOrderLittle,
                               fpu_reg_buf) == fpu_reg_buf_size) {
           SetError(FPURegSet, Read, 0);
index 0c36f1a..344c089 100644 (file)
@@ -426,7 +426,7 @@ bool RegisterContextDarwin_arm64::ReadRegister(const RegisterInfo *reg_info,
   case fpu_v29:
   case fpu_v30:
   case fpu_v31:
-    value.SetBytes(fpu.v[reg].bytes, reg_info->byte_size,
+    value.SetBytes(fpu.v[reg].bytes.buffer, reg_info->byte_size,
                    endian::InlHostByteOrder());
     break;
 
@@ -618,7 +618,7 @@ bool RegisterContextDarwin_arm64::WriteRegister(const RegisterInfo *reg_info,
   case fpu_v29:
   case fpu_v30:
   case fpu_v31:
-    ::memcpy(fpu.v[reg].bytes, value.GetBytes(), value.GetByteSize());
+    ::memcpy(fpu.v[reg].bytes.buffer, value.GetBytes(), value.GetByteSize());
     break;
 
   case fpu_fpsr:
index 2d1fe05..4a0e509 100644 (file)
@@ -78,7 +78,7 @@ public:
   };
 
   struct VReg {
-    uint8_t bytes[16];
+    llvm::AlignedCharArray<16, 16> bytes;
   };
 
   // mirrors <mach/arm/thread_status.h> arm_neon_state64_t