arm64: dts: rockchip: Add RK3328 idle state

Downstream RK3328 DTBs describe a CPU idle state matching that present
on other SoCs like RK3399. This works with upstream Trusted Firmware-A
too, so let's add it here.

Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Link: https://lore.kernel.org/r/a8c83e705d387446ea8121516d410e38b2d9c57b.1577640736.git.robin.murphy@arm.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
index 91306eb..c9ff118 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
@@ -41,6 +41,7 @@
                        reg = <0x0 0x0>;
                        clocks = <&cru ARMCLK>;
                        #cooling-cells = <2>;
+                       cpu-idle-states = <&CPU_SLEEP>;
                        dynamic-power-coefficient = <120>;
                        enable-method = "psci";
                        next-level-cache = <&l2>;
@@ -53,6 +54,7 @@
                        reg = <0x0 0x1>;
                        clocks = <&cru ARMCLK>;
                        #cooling-cells = <2>;
+                       cpu-idle-states = <&CPU_SLEEP>;
                        dynamic-power-coefficient = <120>;
                        enable-method = "psci";
                        next-level-cache = <&l2>;
@@ -65,6 +67,7 @@
                        reg = <0x0 0x2>;
                        clocks = <&cru ARMCLK>;
                        #cooling-cells = <2>;
+                       cpu-idle-states = <&CPU_SLEEP>;
                        dynamic-power-coefficient = <120>;
                        enable-method = "psci";
                        next-level-cache = <&l2>;
@@ -77,12 +80,26 @@
                        reg = <0x0 0x3>;
                        clocks = <&cru ARMCLK>;
                        #cooling-cells = <2>;
+                       cpu-idle-states = <&CPU_SLEEP>;
                        dynamic-power-coefficient = <120>;
                        enable-method = "psci";
                        next-level-cache = <&l2>;
                        operating-points-v2 = <&cpu0_opp_table>;
                };
 
+               idle-states {
+                       entry-method = "psci";
+
+                       CPU_SLEEP: cpu-sleep {
+                               compatible = "arm,idle-state";
+                               local-timer-stop;
+                               arm,psci-suspend-param = <0x0010000>;
+                               entry-latency-us = <120>;
+                               exit-latency-us = <250>;
+                               min-residency-us = <900>;
+                       };
+               };
+
                l2: l2-cache0 {
                        compatible = "cache";
                };