dt-bindings: ti-serdes-mux: Add defines for J721S2 SoC
authorAswath Govindraju <a-govindraju@ti.com>
Tue, 25 Jan 2022 15:26:38 +0000 (20:56 +0530)
committerTom Rini <trini@konsulko.com>
Tue, 8 Feb 2022 14:41:27 +0000 (09:41 -0500)
There are 4 lanes in the single instance of J721S2 SERDES. Each SERDES
lane mux can select upto 4 different IPs. Define all the possible
functions.

Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
include/dt-bindings/mux/ti-serdes.h

index d417b92..d3116c5 100644 (file)
 #define AM64_SERDES0_LANE0_PCIE0               0x0
 #define AM64_SERDES0_LANE0_USB                 0x1
 
+/* J721S2 */
+
+#define J721S2_SERDES0_LANE0_EDP_LANE0         0x0
+#define J721S2_SERDES0_LANE0_PCIE1_LANE0       0x1
+#define J721S2_SERDES0_LANE0_IP3_UNUSED                0x2
+#define J721S2_SERDES0_LANE0_IP4_UNUSED                0x3
+
+#define J721S2_SERDES0_LANE1_EDP_LANE1         0x0
+#define J721S2_SERDES0_LANE1_PCIE1_LANE1       0x1
+#define J721S2_SERDES0_LANE1_USB               0x2
+#define J721S2_SERDES0_LANE1_IP4_UNUSED                0x3
+
+#define J721S2_SERDES0_LANE2_EDP_LANE2         0x0
+#define J721S2_SERDES0_LANE2_PCIE1_LANE2       0x1
+#define J721S2_SERDES0_LANE2_IP3_UNUSED                0x2
+#define J721S2_SERDES0_LANE2_IP4_UNUSED                0x3
+
+#define J721S2_SERDES0_LANE3_EDP_LANE3         0x0
+#define J721S2_SERDES0_LANE3_PCIE1_LANE3       0x1
+#define J721S2_SERDES0_LANE3_USB               0x2
+#define J721S2_SERDES0_LANE3_IP4_UNUSED                0x3
+
 #endif /* _DT_BINDINGS_MUX_TI_SERDES */