ARM: dts: exynos: Add support of bus frequency for exynos4412-trats/odroidu3
authorChanwoo Choi <cw00.choi@samsung.com>
Mon, 11 Apr 2016 03:57:58 +0000 (12:57 +0900)
committerKrzysztof Kozlowski <k.kozlowski@samsung.com>
Tue, 3 May 2016 10:22:59 +0000 (12:22 +0200)
This patch adds the bus device tree nodes for both MIF (Memory) and INT
(Internal) block to enable the bus frequency.

The DMC bus is parent device in MIF block using VDD_MIF and the LEFTBUS
bus is parent device in INT block using VDD_INT.

Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
[m.reichl and linux.amoon: Tested it on exynos4412-odroidu3 board]
Tested-by: Markus Reichl <m.reichl@fivetechno.de>
Tested-by: Anand Moon <linux.amoon@gmail.com>
Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
arch/arm/boot/dts/exynos4412-odroid-common.dtsi
arch/arm/boot/dts/exynos4412-trats2.dts

index b4983cb..2015f10 100644 (file)
        };
 };
 
+&bus_dmc {
+       devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>;
+       vdd-supply = <&buck1_reg>;
+       status = "okay";
+};
+
+&bus_acp {
+       devfreq = <&bus_dmc>;
+       status = "okay";
+};
+
+&bus_c2c {
+       devfreq = <&bus_dmc>;
+       status = "okay";
+};
+
+&bus_leftbus {
+       devfreq-events = <&ppmu_leftbus_3>, <&ppmu_rightbus_3>;
+       vdd-supply = <&buck3_reg>;
+       status = "okay";
+};
+
+&bus_rightbus {
+       devfreq = <&bus_leftbus>;
+       status = "okay";
+};
+
+&bus_display {
+       devfreq = <&bus_leftbus>;
+       status = "okay";
+};
+
+&bus_fsys {
+       devfreq = <&bus_leftbus>;
+       status = "okay";
+};
+
+&bus_peri {
+       devfreq = <&bus_leftbus>;
+       status = "okay";
+};
+
+&bus_mfc {
+       devfreq = <&bus_leftbus>;
+       status = "okay";
+};
+
 &cpu0 {
        cpu0-supply = <&buck2_reg>;
 };
index dce3ceb..9f3fb9a 100644 (file)
        status = "okay";
 };
 
+&bus_dmc {
+       devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>;
+       vdd-supply = <&buck1_reg>;
+       status = "okay";
+};
+
+&bus_acp {
+       devfreq = <&bus_dmc>;
+       status = "okay";
+};
+
+&bus_c2c {
+       devfreq = <&bus_dmc>;
+       status = "okay";
+};
+
+&bus_leftbus {
+       devfreq-events = <&ppmu_leftbus_3>, <&ppmu_rightbus_3>;
+       vdd-supply = <&buck3_reg>;
+       status = "okay";
+};
+
+&bus_rightbus {
+       devfreq = <&bus_leftbus>;
+       status = "okay";
+};
+
+&bus_display {
+       devfreq = <&bus_leftbus>;
+       status = "okay";
+};
+
+&bus_fsys {
+       devfreq = <&bus_leftbus>;
+       status = "okay";
+};
+
+&bus_peri {
+       devfreq = <&bus_leftbus>;
+       status = "okay";
+};
+
+&bus_mfc {
+       devfreq = <&bus_leftbus>;
+       status = "okay";
+};
+
 &cpu0 {
        cpu0-supply = <&buck2_reg>;
 };