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MIPS: mm: c-r4k: Set the correct ISA level
author
Markos Chandras
<markos.chandras@imgtec.com>
Tue, 2 Dec 2014 15:30:19 +0000
(15:30 +0000)
committer
Markos Chandras
<markos.chandras@imgtec.com>
Tue, 17 Feb 2015 15:37:31 +0000
(15:37 +0000)
The local_r4k_flush_cache_sigtramp function uses the 'cache'
instruction inside an asm block. However, MIPS R6 changed the
opcode for the cache instruction and as a result of which we
need to set the correct ISA level.
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
arch/mips/mm/c-r4k.c
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diff --git
a/arch/mips/mm/c-r4k.c
b/arch/mips/mm/c-r4k.c
index
b806deb
..
7ecee76
100644
(file)
--- a/
arch/mips/mm/c-r4k.c
+++ b/
arch/mips/mm/c-r4k.c
@@
-794,7
+794,7
@@
static void local_r4k_flush_cache_sigtramp(void * arg)
__asm__ __volatile__ (
".set push\n\t"
".set noat\n\t"
- ".set
mips3
\n\t"
+ ".set
"MIPS_ISA_LEVEL"
\n\t"
#ifdef CONFIG_32BIT
"la $at,1f\n\t"
#endif