.boot_params = 0x00000100,
.init_machine = cm_a510_init,
.map_io = dove_map_io,
+ .init_early = dove_init_early,
.init_irq = dove_init_irq,
.timer = &dove_timer,
MACHINE_END
/*****************************************************************************
* Time handling
****************************************************************************/
+void __init dove_init_early(void)
+{
+ orion_time_set_base(TIMER_VIRT_BASE);
+}
+
static int get_tclk(void)
{
/* use DOVE_RESET_SAMPLE_HI/LO to detect tclk */
static void dove_timer_init(void)
{
- orion_time_init(IRQ_DOVE_BRIDGE, get_tclk());
+ orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
+ IRQ_DOVE_BRIDGE, get_tclk());
}
struct sys_timer dove_timer = {
*/
void dove_map_io(void);
void dove_init(void);
+void dove_init_early(void);
void dove_init_irq(void);
void dove_setup_cpu_mbus(void);
void dove_ge00_init(struct mv643xx_eth_platform_data *eth_data);
.boot_params = 0x00000100,
.init_machine = dove_db_init,
.map_io = dove_map_io,
+ .init_early = dove_init_early,
.init_irq = dove_init_irq,
.timer = &dove_timer,
MACHINE_END
#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE | 0x010c)
#define SOFT_RESET 0x00000001
-#define BRIDGE_CAUSE (BRIDGE_VIRT_BASE | 0x0110)
-#define BRIDGE_MASK (BRIDGE_VIRT_BASE | 0x0114)
-#define BRIDGE_INT_TIMER0 0x0002
-#define BRIDGE_INT_TIMER1 0x0004
#define BRIDGE_INT_TIMER1_CLR (~0x0004)
#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0200)
/*****************************************************************************
* Time handling
****************************************************************************/
+void __init kirkwood_init_early(void)
+{
+ orion_time_set_base(TIMER_VIRT_BASE);
+}
+
int kirkwood_tclk;
static int __init kirkwood_find_tclk(void)
static void __init kirkwood_timer_init(void)
{
kirkwood_tclk = kirkwood_find_tclk();
- orion_time_init(IRQ_KIRKWOOD_BRIDGE, kirkwood_tclk);
+
+ orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
+ IRQ_KIRKWOOD_BRIDGE, kirkwood_tclk);
}
struct sys_timer kirkwood_timer = {
*/
void kirkwood_map_io(void);
void kirkwood_init(void);
+void kirkwood_init_early(void);
void kirkwood_init_irq(void);
extern struct mbus_dram_target_info kirkwood_mbus_dram_info;
.boot_params = 0x00000100,
.init_machine = d2net_v2_init,
.map_io = kirkwood_map_io,
+ .init_early = kirkwood_init_early,
.init_irq = kirkwood_init_irq,
.timer = &kirkwood_timer,
MACHINE_END
.boot_params = 0x00000100,
.init_machine = db88f6281_init,
.map_io = kirkwood_map_io,
+ .init_early = kirkwood_init_early,
.init_irq = kirkwood_init_irq,
.timer = &kirkwood_timer,
MACHINE_END
.boot_params = 0x00000100,
.init_machine = dockstar_init,
.map_io = kirkwood_map_io,
+ .init_early = kirkwood_init_early,
.init_irq = kirkwood_init_irq,
.timer = &kirkwood_timer,
MACHINE_END
.boot_params = 0x00000100,
.init_machine = guruplug_init,
.map_io = kirkwood_map_io,
+ .init_early = kirkwood_init_early,
.init_irq = kirkwood_init_irq,
.timer = &kirkwood_timer,
MACHINE_END
#define BRIDGE_CAUSE (BRIDGE_VIRT_BASE | 0x0110)
#define WDT_INT_REQ 0x0008
-#define BRIDGE_MASK (BRIDGE_VIRT_BASE | 0x0114)
-#define BRIDGE_INT_TIMER0 0x0002
-#define BRIDGE_INT_TIMER1 0x0004
#define BRIDGE_INT_TIMER1_CLR (~0x0004)
#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0200)
.boot_params = 0x00000100,
.init_machine = mv88f6281gtw_ge_init,
.map_io = kirkwood_map_io,
+ .init_early = kirkwood_init_early,
.init_irq = kirkwood_init_irq,
.timer = &kirkwood_timer,
MACHINE_END
.boot_params = 0x00000100,
.init_machine = netspace_v2_init,
.map_io = kirkwood_map_io,
+ .init_early = kirkwood_init_early,
.init_irq = kirkwood_init_irq,
.timer = &kirkwood_timer,
MACHINE_END
.boot_params = 0x00000100,
.init_machine = netspace_v2_init,
.map_io = kirkwood_map_io,
+ .init_early = kirkwood_init_early,
.init_irq = kirkwood_init_irq,
.timer = &kirkwood_timer,
MACHINE_END
.boot_params = 0x00000100,
.init_machine = netspace_v2_init,
.map_io = kirkwood_map_io,
+ .init_early = kirkwood_init_early,
.init_irq = kirkwood_init_irq,
.timer = &kirkwood_timer,
MACHINE_END
.boot_params = 0x00000100,
.init_machine = netxbig_v2_init,
.map_io = kirkwood_map_io,
+ .init_early = kirkwood_init_early,
.init_irq = kirkwood_init_irq,
.timer = &kirkwood_timer,
MACHINE_END
.boot_params = 0x00000100,
.init_machine = netxbig_v2_init,
.map_io = kirkwood_map_io,
+ .init_early = kirkwood_init_early,
.init_irq = kirkwood_init_irq,
.timer = &kirkwood_timer,
MACHINE_END
.boot_params = 0x00000100,
.init_machine = openrd_init,
.map_io = kirkwood_map_io,
+ .init_early = kirkwood_init_early,
.init_irq = kirkwood_init_irq,
.timer = &kirkwood_timer,
MACHINE_END
.boot_params = 0x00000100,
.init_machine = openrd_init,
.map_io = kirkwood_map_io,
+ .init_early = kirkwood_init_early,
.init_irq = kirkwood_init_irq,
.timer = &kirkwood_timer,
MACHINE_END
.boot_params = 0x00000100,
.init_machine = openrd_init,
.map_io = kirkwood_map_io,
+ .init_early = kirkwood_init_early,
.init_irq = kirkwood_init_irq,
.timer = &kirkwood_timer,
MACHINE_END
.boot_params = 0x00000100,
.init_machine = rd88f6192_init,
.map_io = kirkwood_map_io,
+ .init_early = kirkwood_init_early,
.init_irq = kirkwood_init_irq,
.timer = &kirkwood_timer,
MACHINE_END
.boot_params = 0x00000100,
.init_machine = rd88f6281_init,
.map_io = kirkwood_map_io,
+ .init_early = kirkwood_init_early,
.init_irq = kirkwood_init_irq,
.timer = &kirkwood_timer,
MACHINE_END
.boot_params = 0x00000100,
.init_machine = sheevaplug_init,
.map_io = kirkwood_map_io,
+ .init_early = kirkwood_init_early,
.init_irq = kirkwood_init_irq,
.timer = &kirkwood_timer,
MACHINE_END
.boot_params = 0x00000100,
.init_machine = sheevaplug_init,
.map_io = kirkwood_map_io,
+ .init_early = kirkwood_init_early,
.init_irq = kirkwood_init_irq,
.timer = &kirkwood_timer,
MACHINE_END
.boot_params = 0x00000100,
.init_machine = hp_t5325_init,
.map_io = kirkwood_map_io,
+ .init_early = kirkwood_init_early,
.init_irq = kirkwood_init_irq,
.timer = &kirkwood_timer,
MACHINE_END
.boot_params = 0x00000100,
.init_machine = qnap_ts219_init,
.map_io = kirkwood_map_io,
+ .init_early = kirkwood_init_early,
.init_irq = kirkwood_init_irq,
.timer = &kirkwood_timer,
MACHINE_END
.boot_params = 0x00000100,
.init_machine = qnap_ts41x_init,
.map_io = kirkwood_map_io,
+ .init_early = kirkwood_init_early,
.init_irq = kirkwood_init_irq,
.timer = &kirkwood_timer,
MACHINE_END
#include <asm/timex.h>
#include <asm/mach/map.h>
#include <asm/mach/time.h>
+#include <mach/bridge-regs.h>
#include <mach/loki.h>
#include <plat/orion_nand.h>
#include <plat/time.h>
/*****************************************************************************
* Time handling
****************************************************************************/
+void __init loki_init_early(void)
+{
+ orion_time_set_base(TIMER_VIRT_BASE);
+}
+
static void loki_timer_init(void)
{
- orion_time_init(IRQ_LOKI_BRIDGE, LOKI_TCLK);
+ orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
+ IRQ_LOKI_BRIDGE, LOKI_TCLK);
}
struct sys_timer loki_timer = {
*/
void loki_map_io(void);
void loki_init(void);
+void loki_init_early(void);
void loki_init_irq(void);
extern struct mbus_dram_target_info loki_mbus_dram_info;
#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE | 0x010c)
#define SOFT_RESET 0x00000001
-#define BRIDGE_CAUSE (BRIDGE_VIRT_BASE | 0x0110)
-
-#define BRIDGE_MASK (BRIDGE_VIRT_BASE | 0x0114)
-#define BRIDGE_INT_TIMER0 0x0002
-#define BRIDGE_INT_TIMER1 0x0004
#define BRIDGE_INT_TIMER1_CLR 0x0004
#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0200)
.boot_params = 0x00000100,
.init_machine = lb88rc8480_init,
.map_io = loki_map_io,
+ .init_early = loki_init_early,
.init_irq = loki_init_irq,
.timer = &loki_timer,
MACHINE_END
.boot_params = 0x00000100,
.init_machine = wxl_init,
.map_io = mv78xx0_map_io,
+ .init_early = mv78xx0_init_early,
.init_irq = mv78xx0_init_irq,
.timer = &mv78xx0_timer,
MACHINE_END
/*****************************************************************************
* Time handling
****************************************************************************/
+void __init mv78xx0_init_early(void)
+{
+ orion_time_set_base(TIMER_VIRT_BASE);
+}
+
static void mv78xx0_timer_init(void)
{
- orion_time_init(IRQ_MV78XX0_TIMER_1, get_tclk());
+ orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
+ IRQ_MV78XX0_TIMER_1, get_tclk());
}
struct sys_timer mv78xx0_timer = {
int mv78xx0_core_index(void);
void mv78xx0_map_io(void);
void mv78xx0_init(void);
+void mv78xx0_init_early(void);
void mv78xx0_init_irq(void);
extern struct mbus_dram_target_info mv78xx0_mbus_dram_info;
.boot_params = 0x00000100,
.init_machine = db78x00_init,
.map_io = mv78xx0_map_io,
+ .init_early = mv78xx0_init_early,
.init_irq = mv78xx0_init_irq,
.timer = &mv78xx0_timer,
MACHINE_END
#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE | 0x010c)
#define SOFT_RESET 0x00000001
-#define BRIDGE_CAUSE (BRIDGE_VIRT_BASE | 0x0110)
-#define BRIDGE_MASK (BRIDGE_VIRT_BASE | 0x0114)
-#define BRIDGE_INT_TIMER0 0x0002
-#define BRIDGE_INT_TIMER1 0x0004
#define BRIDGE_INT_TIMER1_CLR (~0x0004)
#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0200)
.boot_params = 0x00000100,
.init_machine = rd78x00_masa_init,
.map_io = mv78xx0_map_io,
+ .init_early = mv78xx0_init_early,
.init_irq = mv78xx0_init_irq,
.timer = &mv78xx0_timer,
MACHINE_END
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/time.h>
+#include <mach/bridge-regs.h>
#include <mach/hardware.h>
#include <mach/orion5x.h>
#include <plat/ehci-orion.h>
/*****************************************************************************
* Time handling
****************************************************************************/
+void __init orion5x_init_early(void)
+{
+ orion_time_set_base(TIMER_VIRT_BASE);
+}
+
int orion5x_tclk;
int __init orion5x_find_tclk(void)
static void orion5x_timer_init(void)
{
orion5x_tclk = orion5x_find_tclk();
- orion_time_init(IRQ_ORION5X_BRIDGE, orion5x_tclk);
+
+ orion_time_init(ORION5X_BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
+ IRQ_ORION5X_BRIDGE, orion5x_tclk);
}
struct sys_timer orion5x_timer = {
* Basic Orion init functions used early by machine-setup.
*/
void orion5x_map_io(void);
+void orion5x_init_early(void);
void orion5x_init_irq(void);
void orion5x_init(void);
extern int orion5x_tclk;
.boot_params = 0x00000100,
.init_machine = d2net_init,
.map_io = orion5x_map_io,
+ .init_early = orion5x_init_early,
.init_irq = orion5x_init_irq,
.timer = &orion5x_timer,
.fixup = tag_fixup_mem32,
.boot_params = 0x00000100,
.init_machine = d2net_init,
.map_io = orion5x_map_io,
+ .init_early = orion5x_init_early,
.init_irq = orion5x_init_irq,
.timer = &orion5x_timer,
.fixup = tag_fixup_mem32,
.boot_params = 0x00000100,
.init_machine = db88f5281_init,
.map_io = orion5x_map_io,
+ .init_early = orion5x_init_early,
.init_irq = orion5x_init_irq,
.timer = &orion5x_timer,
MACHINE_END
.boot_params = 0x00000100,
.init_machine = dns323_init,
.map_io = orion5x_map_io,
+ .init_early = orion5x_init_early,
.init_irq = orion5x_init_irq,
.timer = &orion5x_timer,
.fixup = tag_fixup_mem32,
.boot_params = 0x00000100,
.init_machine = edmini_v2_init,
.map_io = orion5x_map_io,
+ .init_early = orion5x_init_early,
.init_irq = orion5x_init_irq,
.timer = &orion5x_timer,
.fixup = tag_fixup_mem32,
#define CPU_SOFT_RESET (ORION5X_BRIDGE_VIRT_BASE | 0x10c)
+#define BRIDGE_CAUSE (ORION5X_BRIDGE_VIRT_BASE | 0x110)
+
#define POWER_MNG_CTRL_REG (ORION5X_BRIDGE_VIRT_BASE | 0x11C)
-#define BRIDGE_CAUSE (ORION5X_BRIDGE_VIRT_BASE | 0x110)
#define WDT_INT_REQ 0x0008
-#define BRIDGE_MASK (ORION5X_BRIDGE_VIRT_BASE | 0x114)
-#define BRIDGE_INT_TIMER0 0x0002
-#define BRIDGE_INT_TIMER1 0x0004
#define BRIDGE_INT_TIMER1_CLR (~0x0004)
#define MAIN_IRQ_CAUSE (ORION5X_BRIDGE_VIRT_BASE | 0x200)
.boot_params = 0x00000100,
.init_machine = kurobox_pro_init,
.map_io = orion5x_map_io,
+ .init_early = orion5x_init_early,
.init_irq = orion5x_init_irq,
.timer = &orion5x_timer,
.fixup = tag_fixup_mem32,
.boot_params = 0x00000100,
.init_machine = kurobox_pro_init,
.map_io = orion5x_map_io,
+ .init_early = orion5x_init_early,
.init_irq = orion5x_init_irq,
.timer = &orion5x_timer,
.fixup = tag_fixup_mem32,
.boot_params = 0x00000100,
.init_machine = lschl_init,
.map_io = orion5x_map_io,
+ .init_early = orion5x_init_early,
.init_irq = orion5x_init_irq,
.timer = &orion5x_timer,
.fixup = tag_fixup_mem32,
.boot_params = 0x00000100,
.init_machine = ls_hgl_init,
.map_io = orion5x_map_io,
+ .init_early = orion5x_init_early,
.init_irq = orion5x_init_irq,
.timer = &orion5x_timer,
.fixup = tag_fixup_mem32,
.boot_params = 0x00000100,
.init_machine = lsmini_init,
.map_io = orion5x_map_io,
+ .init_early = orion5x_init_early,
.init_irq = orion5x_init_irq,
.timer = &orion5x_timer,
.fixup = tag_fixup_mem32,
.boot_params = 0x00000100,
.init_machine = mss2_init,
.map_io = orion5x_map_io,
+ .init_early = orion5x_init_early,
.init_irq = orion5x_init_irq,
.timer = &orion5x_timer,
.fixup = tag_fixup_mem32
.boot_params = 0x00000100,
.init_machine = mv2120_init,
.map_io = orion5x_map_io,
+ .init_early = orion5x_init_early,
.init_irq = orion5x_init_irq,
.timer = &orion5x_timer,
.fixup = tag_fixup_mem32
.boot_params = 0x00000100,
.init_machine = net2big_init,
.map_io = orion5x_map_io,
+ .init_early = orion5x_init_early,
.init_irq = orion5x_init_irq,
.timer = &orion5x_timer,
.fixup = tag_fixup_mem32,
.boot_params = 0x00000100,
.init_machine = rd88f5181l_fxo_init,
.map_io = orion5x_map_io,
+ .init_early = orion5x_init_early,
.init_irq = orion5x_init_irq,
.timer = &orion5x_timer,
.fixup = tag_fixup_mem32,
.boot_params = 0x00000100,
.init_machine = rd88f5181l_ge_init,
.map_io = orion5x_map_io,
+ .init_early = orion5x_init_early,
.init_irq = orion5x_init_irq,
.timer = &orion5x_timer,
.fixup = tag_fixup_mem32,
.boot_params = 0x00000100,
.init_machine = rd88f5182_init,
.map_io = orion5x_map_io,
+ .init_early = orion5x_init_early,
.init_irq = orion5x_init_irq,
.timer = &orion5x_timer,
MACHINE_END
.boot_params = 0x00000100,
.init_machine = rd88f6183ap_ge_init,
.map_io = orion5x_map_io,
+ .init_early = orion5x_init_early,
.init_irq = orion5x_init_irq,
.timer = &orion5x_timer,
.fixup = tag_fixup_mem32,
.boot_params = 0x00000100,
.init_machine = tsp2_init,
.map_io = orion5x_map_io,
+ .init_early = orion5x_init_early,
.init_irq = orion5x_init_irq,
.timer = &orion5x_timer,
.fixup = tag_fixup_mem32,
.boot_params = 0x00000100,
.init_machine = qnap_ts209_init,
.map_io = orion5x_map_io,
+ .init_early = orion5x_init_early,
.init_irq = orion5x_init_irq,
.timer = &orion5x_timer,
.fixup = tag_fixup_mem32,
.boot_params = 0x00000100,
.init_machine = qnap_ts409_init,
.map_io = orion5x_map_io,
+ .init_early = orion5x_init_early,
.init_irq = orion5x_init_irq,
.timer = &orion5x_timer,
.fixup = tag_fixup_mem32,
.boot_params = 0x00000100,
.init_machine = ts78xx_init,
.map_io = ts78xx_map_io,
+ .init_early = orion5x_init_early,
.init_irq = orion5x_init_irq,
.timer = &orion5x_timer,
MACHINE_END
.boot_params = 0x00000100,
.init_machine = wnr854t_init,
.map_io = orion5x_map_io,
+ .init_early = orion5x_init_early,
.init_irq = orion5x_init_irq,
.timer = &orion5x_timer,
.fixup = tag_fixup_mem32,
.boot_params = 0x00000100,
.init_machine = wrt350n_v2_init,
.map_io = orion5x_map_io,
+ .init_early = orion5x_init_early,
.init_irq = orion5x_init_irq,
.timer = &orion5x_timer,
.fixup = tag_fixup_mem32,
#ifndef __PLAT_TIME_H
#define __PLAT_TIME_H
-void orion_time_init(unsigned int irq, unsigned int tclk);
+void orion_time_set_base(u32 timer_base);
+
+void orion_time_init(u32 bridge_base, u32 bridge_timer1_clr_mask,
+ unsigned int irq, unsigned int tclk);
#endif
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <asm/sched_clock.h>
-#include <asm/mach/time.h>
-#include <mach/bridge-regs.h>
-#include <mach/hardware.h>
/*
- * Number of timer ticks per jiffy.
+ * MBus bridge block registers.
*/
-static u32 ticks_per_jiffy;
+#define BRIDGE_CAUSE_OFF 0x0110
+#define BRIDGE_MASK_OFF 0x0114
+#define BRIDGE_INT_TIMER0 0x0002
+#define BRIDGE_INT_TIMER1 0x0004
/*
* Timer block registers.
*/
-#define TIMER_CTRL (TIMER_VIRT_BASE + 0x0000)
-#define TIMER0_EN 0x0001
-#define TIMER0_RELOAD_EN 0x0002
-#define TIMER1_EN 0x0004
-#define TIMER1_RELOAD_EN 0x0008
-#define TIMER0_RELOAD (TIMER_VIRT_BASE + 0x0010)
-#define TIMER0_VAL (TIMER_VIRT_BASE + 0x0014)
-#define TIMER1_RELOAD (TIMER_VIRT_BASE + 0x0018)
-#define TIMER1_VAL (TIMER_VIRT_BASE + 0x001c)
+#define TIMER_CTRL_OFF 0x0000
+#define TIMER0_EN 0x0001
+#define TIMER0_RELOAD_EN 0x0002
+#define TIMER1_EN 0x0004
+#define TIMER1_RELOAD_EN 0x0008
+#define TIMER0_RELOAD_OFF 0x0010
+#define TIMER0_VAL_OFF 0x0014
+#define TIMER1_RELOAD_OFF 0x0018
+#define TIMER1_VAL_OFF 0x001c
+
+
+/*
+ * SoC-specific data.
+ */
+static void __iomem *bridge_base;
+static u32 bridge_timer1_clr_mask;
+static void __iomem *timer_base;
+
+
+/*
+ * Number of timer ticks per jiffy.
+ */
+static u32 ticks_per_jiffy;
/*
unsigned long long notrace sched_clock(void)
{
- u32 cyc = 0xffffffff - readl(TIMER0_VAL);
+ u32 cyc = ~readl(timer_base + TIMER0_VAL_OFF);
return cyc_to_sched_clock(&cd, cyc, (u32)~0);
}
static void notrace orion_update_sched_clock(void)
{
- u32 cyc = 0xffffffff - readl(TIMER0_VAL);
+ u32 cyc = ~readl(timer_base + TIMER0_VAL_OFF);
update_sched_clock(&cd, cyc, (u32)~0);
}
*/
static cycle_t orion_clksrc_read(struct clocksource *cs)
{
- return 0xffffffff - readl(TIMER0_VAL);
+ return 0xffffffff - readl(timer_base + TIMER0_VAL_OFF);
}
static struct clocksource orion_clksrc = {
/*
* Clear and enable clockevent timer interrupt.
*/
- writel(BRIDGE_INT_TIMER1_CLR, BRIDGE_CAUSE);
+ writel(bridge_timer1_clr_mask, bridge_base + BRIDGE_CAUSE_OFF);
- u = readl(BRIDGE_MASK);
+ u = readl(bridge_base + BRIDGE_MASK_OFF);
u |= BRIDGE_INT_TIMER1;
- writel(u, BRIDGE_MASK);
+ writel(u, bridge_base + BRIDGE_MASK_OFF);
/*
* Setup new clockevent timer value.
*/
- writel(delta, TIMER1_VAL);
+ writel(delta, timer_base + TIMER1_VAL_OFF);
/*
* Enable the timer.
*/
- u = readl(TIMER_CTRL);
+ u = readl(timer_base + TIMER_CTRL_OFF);
u = (u & ~TIMER1_RELOAD_EN) | TIMER1_EN;
- writel(u, TIMER_CTRL);
+ writel(u, timer_base + TIMER_CTRL_OFF);
local_irq_restore(flags);
/*
* Setup timer to fire at 1/HZ intervals.
*/
- writel(ticks_per_jiffy - 1, TIMER1_RELOAD);
- writel(ticks_per_jiffy - 1, TIMER1_VAL);
+ writel(ticks_per_jiffy - 1, timer_base + TIMER1_RELOAD_OFF);
+ writel(ticks_per_jiffy - 1, timer_base + TIMER1_VAL_OFF);
/*
* Enable timer interrupt.
*/
- u = readl(BRIDGE_MASK);
- writel(u | BRIDGE_INT_TIMER1, BRIDGE_MASK);
+ u = readl(bridge_base + BRIDGE_MASK_OFF);
+ writel(u | BRIDGE_INT_TIMER1, bridge_base + BRIDGE_MASK_OFF);
/*
* Enable timer.
*/
- u = readl(TIMER_CTRL);
- writel(u | TIMER1_EN | TIMER1_RELOAD_EN, TIMER_CTRL);
+ u = readl(timer_base + TIMER_CTRL_OFF);
+ writel(u | TIMER1_EN | TIMER1_RELOAD_EN,
+ timer_base + TIMER_CTRL_OFF);
} else {
/*
* Disable timer.
*/
- u = readl(TIMER_CTRL);
- writel(u & ~TIMER1_EN, TIMER_CTRL);
+ u = readl(timer_base + TIMER_CTRL_OFF);
+ writel(u & ~TIMER1_EN, timer_base + TIMER_CTRL_OFF);
/*
* Disable timer interrupt.
*/
- u = readl(BRIDGE_MASK);
- writel(u & ~BRIDGE_INT_TIMER1, BRIDGE_MASK);
+ u = readl(bridge_base + BRIDGE_MASK_OFF);
+ writel(u & ~BRIDGE_INT_TIMER1, bridge_base + BRIDGE_MASK_OFF);
/*
* ACK pending timer interrupt.
*/
- writel(BRIDGE_INT_TIMER1_CLR, BRIDGE_CAUSE);
+ writel(bridge_timer1_clr_mask, bridge_base + BRIDGE_CAUSE_OFF);
}
local_irq_restore(flags);
/*
* ACK timer interrupt and call event handler.
*/
- writel(BRIDGE_INT_TIMER1_CLR, BRIDGE_CAUSE);
+ writel(bridge_timer1_clr_mask, bridge_base + BRIDGE_CAUSE_OFF);
orion_clkevt.event_handler(&orion_clkevt);
return IRQ_HANDLED;
.handler = orion_timer_interrupt
};
-void __init orion_time_init(unsigned int irq, unsigned int tclk)
+void __init
+orion_time_set_base(u32 _timer_base)
+{
+ timer_base = (void __iomem *)_timer_base;
+}
+
+void __init
+orion_time_init(u32 _bridge_base, u32 _bridge_timer1_clr_mask,
+ unsigned int irq, unsigned int tclk)
{
u32 u;
+ /*
+ * Set SoC-specific data.
+ */
+ bridge_base = (void __iomem *)_bridge_base;
+ bridge_timer1_clr_mask = _bridge_timer1_clr_mask;
+
ticks_per_jiffy = (tclk + HZ/2) / HZ;
/*
- * Set scale and timer for sched_clock
+ * Set scale and timer for sched_clock.
*/
setup_sched_clock(tclk);
/*
* Setup free-running clocksource timer (interrupts
- * disabled.)
+ * disabled).
*/
- writel(0xffffffff, TIMER0_VAL);
- writel(0xffffffff, TIMER0_RELOAD);
- u = readl(BRIDGE_MASK);
- writel(u & ~BRIDGE_INT_TIMER0, BRIDGE_MASK);
- u = readl(TIMER_CTRL);
- writel(u | TIMER0_EN | TIMER0_RELOAD_EN, TIMER_CTRL);
+ writel(0xffffffff, timer_base + TIMER0_VAL_OFF);
+ writel(0xffffffff, timer_base + TIMER0_RELOAD_OFF);
+ u = readl(bridge_base + BRIDGE_MASK_OFF);
+ writel(u & ~BRIDGE_INT_TIMER0, bridge_base + BRIDGE_MASK_OFF);
+ u = readl(timer_base + TIMER_CTRL_OFF);
+ writel(u | TIMER0_EN | TIMER0_RELOAD_EN, timer_base + TIMER_CTRL_OFF);
clocksource_register_hz(&orion_clksrc, tclk);
/*
- * Setup clockevent timer (interrupt-driven.)
+ * Setup clockevent timer (interrupt-driven).
*/
setup_irq(irq, &orion_timer_irq);
orion_clkevt.mult = div_sc(tclk, NSEC_PER_SEC, orion_clkevt.shift);