clk: renesas: r8a779g0: Add SDHI clocks

Add the SD0H core clock and the SDHI module clock, which are used by the
SD Card/MMC Interface on the Renesas R-Car V4H (R8A779G0) SoC.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/e9b05d102160cc3f7395ac53a533e81c07307d5e.1665558175.git.geert+renesas@glider.be

diff --git a/drivers/clk/renesas/r8a779g0-cpg-mssr.c b/drivers/clk/renesas/r8a779g0-cpg-mssr.c
index 5cc5ee1..390162a 100644 (file)
--- a/drivers/clk/renesas/r8a779g0-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a779g0-cpg-mssr.c
@@ -144,7 +144,8 @@ static const struct cpg_core_clk r8a779g0_core_clks[] __initconst = {
        DEF_FIXED("vcbus",      R8A779G0_CLK_VCBUS,     CLK_VC,         1, 1),
        DEF_FIXED("vcbusd2",    R8A779G0_CLK_VCBUSD2,   CLK_VC,         2, 1),
 
-       DEF_GEN4_SD("sd0",      R8A779G0_CLK_SD0,       CLK_SDSRC,      0x870),
+       DEF_GEN4_SDH("sd0h",    R8A779G0_CLK_SD0H,      CLK_SDSRC,         0x870),
+       DEF_GEN4_SD("sd0",      R8A779G0_CLK_SD0,       R8A779G0_CLK_SD0H, 0x870),
        DEF_DIV6P1("mso",       R8A779G0_CLK_MSO,       CLK_PLL5_DIV4,  0x87c),
 
        DEF_BASE("rpc",         R8A779G0_CLK_RPC,       CLK_TYPE_GEN4_RPC, CLK_RPCSRC),
@@ -180,6 +181,7 @@ static const struct mssr_mod_clk r8a779g0_mod_clks[] __initconst = {
        DEF_MOD("scif1",        703,    R8A779G0_CLK_SASYNCPERD4),
        DEF_MOD("scif3",        704,    R8A779G0_CLK_SASYNCPERD4),
        DEF_MOD("scif4",        705,    R8A779G0_CLK_SASYNCPERD4),
+       DEF_MOD("sdhi",         706,    R8A779G0_CLK_SD0),
        DEF_MOD("sydm0",        709,    R8A779G0_CLK_S0D6_PER),
        DEF_MOD("sydm1",        710,    R8A779G0_CLK_S0D6_PER),
        DEF_MOD("tpu0",         718,    R8A779G0_CLK_SASYNCPERD4),